run("synth -run coarse");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/gowin/bram.txt");
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
run("techmap -map +/gowin/cells_map.v");
run("setundef -undriven -params -zero");
run("hilomap -singleton -hicell VCC V -locell GND G");
- run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
+ run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
run("dffinit -ff DFF Q INIT");
run("clean");
--- /dev/null
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:TBUF
+select -assert-count 2 t:IBUF
+select -assert-none t:TBUF t:IBUF %% t:* %D