r600: add support for ARB_shader_clock.

Reviewed-by: Gert Wollny <gw.fossedev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/docs/features.txt b/docs/features.txt
index 980140f60dac204465ccb1dcb4a9009d2f8ce713..e9b7be554b5413e257867f863a5e05cebca70edc 100644 (file)
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -305,7 +305,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_sample_locations                               not started
   GL_ARB_seamless_cubemap_per_texture                   DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
   GL_ARB_shader_ballot                                  DONE (i965/gen8+, nvc0, radeonsi)
-  GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, radeonsi)
+  GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, r600, radeonsi)
   GL_ARB_shader_stencil_export                          DONE (i965/gen9+, r600, radeonsi, softpipe, llvmpipe, swr)
   GL_ARB_shader_viewport_layer_array                    DONE (i965/gen6+, nvc0, radeonsi)
   GL_ARB_sparse_buffer                                  DONE (radeonsi/CIK+)

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 6572d76d64ae5d689d56fde5f22f7952d427c806..c146383360a961837a75e10924453806b378679a 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -350,6 +350,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
        case PIPE_CAP_SAMPLER_VIEW_TARGET:
        case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
+       case PIPE_CAP_TGSI_CLOCK:
                return family >= CHIP_CEDAR ? 1 : 0;
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
                return family >= CHIP_CEDAR ? 4 : 0;
@@ -394,7 +395,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_INT64:
        case PIPE_CAP_INT64_DIVMOD:
        case PIPE_CAP_TGSI_TEX_TXF_LZ:
-       case PIPE_CAP_TGSI_CLOCK:
        case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
        case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
        case PIPE_CAP_TGSI_BALLOT:

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index ab18a6e08ea16c8bb8efd2995b7ee2a8515302dd..623e6f7f70473a6ce0e83926b55ea8159a6e07c1 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -10190,6 +10190,29 @@ static int tgsi_bfe(struct r600_shader_ctx *ctx)
        return 0;
 }
 
+static int tgsi_clock(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int r;
+
+       memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+       alu.op = ALU_OP1_MOV;
+       tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+       alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
+       r = r600_bytecode_add_alu(ctx->bc, &alu);
+       if (r)
+               return r;
+       memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+       alu.op = ALU_OP1_MOV;
+       tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+       alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
+       r = r600_bytecode_add_alu(ctx->bc, &alu);
+       if (r)
+               return r;
+       return 0;
+}
+
 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        [TGSI_OPCODE_ARL]       = { ALU_OP0_NOP, tgsi_r600_arl},
        [TGSI_OPCODE_MOV]       = { ALU_OP1_MOV, tgsi_op2},
@@ -10226,7 +10249,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
        [TGSI_OPCODE_POW]       = { ALU_OP0_NOP, tgsi_pow},
        [31]    = { ALU_OP0_NOP, tgsi_unsupported},
        [32]                    = { ALU_OP0_NOP, tgsi_unsupported},
-       [33]                    = { ALU_OP0_NOP, tgsi_unsupported},
+       [TGSI_OPCODE_CLOCK]     = { ALU_OP0_NOP, tgsi_unsupported},
        [34]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [35]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [TGSI_OPCODE_COS]       = { ALU_OP1_COS, tgsi_trig},
@@ -10424,7 +10447,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
        [TGSI_OPCODE_POW]       = { ALU_OP0_NOP, tgsi_pow},
        [31]    = { ALU_OP0_NOP, tgsi_unsupported},
        [32]                    = { ALU_OP0_NOP, tgsi_unsupported},
-       [33]                    = { ALU_OP0_NOP, tgsi_unsupported},
+       [TGSI_OPCODE_CLOCK]     = { ALU_OP0_NOP, tgsi_clock},
        [34]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [35]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [TGSI_OPCODE_COS]       = { ALU_OP1_COS, tgsi_trig},
@@ -10646,7 +10669,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
        [TGSI_OPCODE_POW]       = { ALU_OP0_NOP, cayman_pow},
        [31]    = { ALU_OP0_NOP, tgsi_unsupported},
        [32]                    = { ALU_OP0_NOP, tgsi_unsupported},
-       [33]                    = { ALU_OP0_NOP, tgsi_unsupported},
+       [TGSI_OPCODE_CLOCK]     = { ALU_OP0_NOP, tgsi_clock},
        [34]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [35]                    = { ALU_OP0_NOP, tgsi_unsupported},
        [TGSI_OPCODE_COS]       = { ALU_OP1_COS, cayman_trig},

diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index aa38381328c1d3173107de6bc2ed4756cd60ac40..f51ffcf9e23a2a1bf7631d89440502b9bc44b980 100644 (file)
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -196,7 +196,8 @@
 #define     EG_V_SQ_ALU_SRC_LDS_OQ_B_POP                             0x000000DE
 #define     EG_V_SQ_ALU_SRC_LDS_DIRECT_A                             0x000000DF
 #define     EG_V_SQ_ALU_SRC_LDS_DIRECT_B                             0x000000E0
-
+#define     EG_V_SQ_ALU_SRC_TIME_HI                                  0x000000E3
+#define     EG_V_SQ_ALU_SRC_TIME_LO                                  0x000000E4
 #define     EG_V_SQ_ALU_SRC_HW_WAVE_ID                               0x000000E7
 #define     EG_V_SQ_ALU_SRC_SIMD_ID                                  0x000000E8
 #define     EG_V_SQ_ALU_SRC_SE_ID                                    0x000000E9