Re: [libre-riscv-dev] Introduction and Questions
authorStaf Verhaegen <staf@fibraservi.eu>
Sat, 16 May 2020 11:30:51 +0000 (13:30 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 16 May 2020 11:31:02 +0000 (12:31 +0100)
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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Date: Sat, 16 May 2020 13:30:51 +0200
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+Subject: Re: [libre-riscv-dev] Introduction and Questions
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+
+Op 16/05/2020 om 11:47 schreef Staf Verhaegen:
+> Jeremy Singher schreef op vr 15-05-2020 om 16:49 [-0700]:
+>>
+>> Hmmm, ignoring WAW will significantly limit the ability of the core to=
+
+>> exploit ILP, which is one of the fundamental reasons for going OOO.
+> I've wondered about this myself. Can you give concrete example of where=
+
+> not supporting a WAW hazard blocks ILP ?
+> I am asking because just a WAW hazard could be easily avoided by a good=
+
+> peep hole optimizer in software because it would see that the output of=
+
+> the first write is never used.
+
+Ok after some reflection I do see the most possible performance
+difference in procedures calls. Most of the time in procedures some
+scratch registers are pushed on the stack at entering.
+
+Assume a write to a scratch register is still pending when doing a
+procedure. With real register renaming the register stack push does not
+need to block until write to register is complete, if it doesn't the
+register push will block.
+
+The question is special hardware provision need to be done to optimize
+this case or if one would rely on proper inlining of functions by the
+compiler for performance critical code. Personally I don't see a problem
+with relying on the latter.
+
+greets,
+Staf.
+
+
+
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