}
void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;
};
struct si_blend_color {
- struct r600_atom atom;
+ struct si_atom atom;
struct pipe_blend_color state;
bool any_nonzeros;
};
};
struct si_framebuffer {
- struct r600_atom atom;
+ struct si_atom atom;
struct pipe_framebuffer_state state;
unsigned colorbuf_enabled_4bit;
unsigned spi_shader_col_format;
};
struct si_scissors {
- struct r600_atom atom;
+ struct si_atom atom;
unsigned dirty_mask;
struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
};
struct si_viewports {
- struct r600_atom atom;
+ struct si_atom atom;
unsigned dirty_mask;
unsigned depth_range_dirty_mask;
struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
};
struct si_clip_state {
- struct r600_atom atom;
+ struct si_atom atom;
struct pipe_clip_state state;
bool any_nonzeros;
};
struct si_sample_locs {
- struct r600_atom atom;
+ struct si_atom atom;
unsigned nr_samples;
};
struct si_sample_mask {
- struct r600_atom atom;
+ struct si_atom atom;
uint16_t sample_mask;
};
};
struct si_streamout {
- struct r600_atom begin_atom;
+ struct si_atom begin_atom;
bool begin_emitted;
unsigned enabled_mask;
unsigned hw_enabled_mask;
/* The state of VGT_STRMOUT_(CONFIG|EN). */
- struct r600_atom enable_atom;
+ struct si_atom enable_atom;
bool streamout_enabled;
bool prims_gen_query_enabled;
int num_prims_gen_queries;
/* Atom declarations. */
struct si_framebuffer framebuffer;
struct si_sample_locs msaa_sample_locs;
- struct r600_atom db_render_state;
- struct r600_atom dpbb_state;
- struct r600_atom msaa_config;
+ struct si_atom db_render_state;
+ struct si_atom dpbb_state;
+ struct si_atom msaa_config;
struct si_sample_mask sample_mask;
- struct r600_atom cb_render_state;
+ struct si_atom cb_render_state;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
- struct r600_atom clip_regs;
+ struct si_atom clip_regs;
struct si_clip_state clip_state;
struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
- struct r600_atom spi_map;
+ struct si_atom spi_map;
struct si_scissors scissors;
struct si_streamout streamout;
struct si_viewports viewports;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
/* Scratch buffer */
- struct r600_atom scratch_state;
+ struct si_atom scratch_state;
struct r600_resource *scratch_buffer;
unsigned scratch_waves;
unsigned spi_tmpring_size;
unsigned num_cs_dw_queries_suspend;
/* Render condition. */
- struct r600_atom render_cond_atom;
+ struct si_atom render_cond_atom;
struct pipe_query *render_cond;
unsigned render_cond_mode;
bool render_cond_invert;
static inline void
si_set_atom_dirty(struct si_context *sctx,
- struct r600_atom *atom, bool dirty)
+ struct si_atom *atom, bool dirty)
{
unsigned bit = 1 << atom->id;
static inline bool
si_is_atom_dirty(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
unsigned bit = 1 << atom->id;
static inline void
si_mark_atom_dirty(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
si_set_atom_dirty(sctx, atom, true);
}
}
static void si_emit_query_predication(struct si_context *ctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
struct si_query_buffer *qbuf;
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_query_hw *rquery = (struct si_query_hw *)query;
- struct r600_atom *atom = &sctx->render_cond_atom;
+ struct si_atom *atom = &sctx->render_cond_atom;
if (query) {
bool needs_workaround = false;
/* Initialize an external atom (owned by ../radeon). */
static void
-si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
- struct r600_atom **list_elem)
+si_init_external_atom(struct si_context *sctx, struct si_atom *atom,
+ struct si_atom **list_elem)
{
atom->id = list_elem - sctx->atoms.array;
*list_elem = atom;
}
/* Initialize an atom owned by radeonsi. */
-void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
- struct r600_atom **list_elem,
- void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
+void si_init_atom(struct si_context *sctx, struct si_atom *atom,
+ struct si_atom **list_elem,
+ void (*emit_func)(struct si_context *ctx, struct si_atom *state))
{
atom->emit = emit_func;
atom->id = list_elem - sctx->atoms.array;
* CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
* if there is not enough PS outputs.
*/
-static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_cb_render_state(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_blend *blend = sctx->queued.named.blend;
si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
}
-static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_blend_color(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
pipe_resource_reference(&cb.buffer, NULL);
}
-static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
}
-static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_clip_regs(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *vs = si_get_vs_state(sctx);
/*
* infeered state between dsa and stencil ref
*/
-static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_stencil_ref(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
}
-static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
+static void si_emit_db_render_state(struct si_context *sctx, struct si_atom *state)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
}
}
-static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
}
static void si_emit_msaa_sample_locs(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned nr_samples = sctx->framebuffer.nr_samples;
return true;
}
-static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_msaa_config(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
}
-static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_sample_mask(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned mask = sctx->sample_mask.sample_mask;
/* This encapsulates a state or an operation which can emitted into the GPU
* command stream. */
-struct r600_atom {
- void (*emit)(struct si_context *ctx, struct r600_atom *state);
+struct si_atom {
+ void (*emit)(struct si_context *ctx, struct si_atom *state);
unsigned short id;
};
};
struct si_stencil_ref {
- struct r600_atom atom;
+ struct si_atom atom;
struct pipe_stencil_ref state;
struct si_dsa_stencil_ref_part dsa_part;
};
union si_state_atoms {
struct {
/* The order matters. */
- struct r600_atom *render_cond;
- struct r600_atom *streamout_begin;
- struct r600_atom *streamout_enable; /* must be after streamout_begin */
- struct r600_atom *framebuffer;
- struct r600_atom *msaa_sample_locs;
- struct r600_atom *db_render_state;
- struct r600_atom *dpbb_state;
- struct r600_atom *msaa_config;
- struct r600_atom *sample_mask;
- struct r600_atom *cb_render_state;
- struct r600_atom *blend_color;
- struct r600_atom *clip_regs;
- struct r600_atom *clip_state;
- struct r600_atom *shader_pointers;
- struct r600_atom *scissors;
- struct r600_atom *viewports;
- struct r600_atom *stencil_ref;
- struct r600_atom *spi_map;
- struct r600_atom *scratch_state;
+ struct si_atom *render_cond;
+ struct si_atom *streamout_begin;
+ struct si_atom *streamout_enable; /* must be after streamout_begin */
+ struct si_atom *framebuffer;
+ struct si_atom *msaa_sample_locs;
+ struct si_atom *db_render_state;
+ struct si_atom *dpbb_state;
+ struct si_atom *msaa_config;
+ struct si_atom *sample_mask;
+ struct si_atom *cb_render_state;
+ struct si_atom *blend_color;
+ struct si_atom *clip_regs;
+ struct si_atom *clip_state;
+ struct si_atom *shader_pointers;
+ struct si_atom *scissors;
+ struct si_atom *viewports;
+ struct si_atom *stencil_ref;
+ struct si_atom *spi_map;
+ struct si_atom *scratch_state;
} s;
- struct r600_atom *array[0];
+ struct si_atom *array[0];
};
-#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
+#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
struct si_shader_data {
- struct r600_atom atom;
+ struct si_atom atom;
uint32_t sh_base[SI_NUM_SHADERS];
};
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
void si_emit_graphics_shader_pointers(struct si_context *sctx,
- struct r600_atom *atom);
+ struct si_atom *atom);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
/* si_state.c */
struct si_shader_selector;
-void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
- struct r600_atom **list_elem,
- void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
+void si_init_atom(struct si_context *sctx, struct si_atom *atom,
+ struct si_atom **list_elem,
+ void (*emit_func)(struct si_context *ctx, struct si_atom *state));
void si_init_state_functions(struct si_context *sctx);
void si_init_screen_state_functions(struct si_screen *sscreen);
void
bool old_perfect_enable);
/* si_state_binning.c */
-void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state);
+void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state);
/* si_state_shaders.c */
bool si_update_shaders(struct si_context *sctx);
S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
}
-void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state)
+void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state)
{
struct si_screen *sscreen = sctx->screen;
struct si_state_blend *blend = sctx->queued.named.blend;
/* Emit state atoms. */
unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
while (mask) {
- struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
+ struct si_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
atom->emit(sctx, atom);
}
return ps_input_cntl;
}
-static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_spi_map(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *ps = sctx->ps_shader.current;
}
static void si_emit_scratch_state(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_emit(cs, 4); /* poll interval */
}
-static void si_emit_streamout_begin(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_streamout_begin(struct si_context *sctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_streamout_target **t = sctx->streamout.targets;
*/
static void si_emit_streamout_enable(struct si_context *sctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(sctx->gfx_cs,
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
-static void si_emit_scissors(struct si_context *ctx, struct r600_atom *atom)
+static void si_emit_scissors(struct si_context *ctx, struct si_atom *atom)
{
struct radeon_winsys_cs *cs = ctx->gfx_cs;
struct pipe_scissor_state *states = ctx->scissors.states;
}
static void si_emit_viewport_states(struct si_context *ctx,
- struct r600_atom *atom)
+ struct si_atom *atom)
{
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);