[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Mon, 16 Mar 2020 09:59:04 +0000 (09:59 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Mon, 16 Mar 2020 09:59:05 +0000 (09:59 +0000)
a5/f076f91f447e46a28da3cfb809aa17b08777ac [new file with mode: 0644]

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+Date: Mon, 16 Mar 2020 09:59:04 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-241-13-w7rPsBqN4n@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of
+ standards
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