(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index aed1adabcaf195ec2ec659fe6e664340c0342d38..7284a21473d6fb0f3f20ff8cf13ee89b8a88e6b6 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -32,11 +32,12 @@ Other "modifications" such as saturation or Data-dependent Fail-First
 likewise are post-augmentation or post-analysis, and do not actually
 fundamentally change an add operation into a subtract for example.
 
-*(An experiment was attempted to modify LD-immediate instructions
+*(In an early Draft of SVP64,
+an experiment was attempted, to modify LD-immediate instructions
 to include a
 third RC register i.e. reinterpret the normal
-v3.0 32-bit instruction as a
-different encoding if SVP64-prefixed: it did not go well.
+v3.0 32-bit instruction as a completely
+different encoding if SVP64-prefixed. It did not go well.
 The complexity that resulted
 in the decode phase was too great. The lesson was learned, the
 hard way: it is infinitely preferable to add a 32-bit Scalar Load-with-Shift