Implement adc and sbb instructions and microops.

--HG--
extra : convert_revision : a2d3068c5b487f4fa7bf5c9cebba7753bc390bfa

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index d1ef8d48e66d76a79bec6b999f4e527be7111cbe..11d8425cea140ec1af2d75f8d4e6c5d6821e9bcf 100644 (file)
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -88,12 +88,6 @@
                                    [rAl,Ib], [rAx,Iz]);
         }
         0x02: decode OPCODE_OP_BOTTOM3 {
-            0x0: adc_Eb_Gb();
-            0x1: adc_Ev_Gv();
-            0x2: adc_Gb_Eb();
-            0x3: adc_Gv_Ev();
-            0x4: adc_Al_Ib();
-            0x5: adc_rAX_Iz();
             0x6: decode MODE_SUBMODE {
                 0x0: This_should_be_an_illegal_instruction();
                 default: push_SS();
@@ -102,14 +96,12 @@
                 0x0: This_should_be_an_illegal_instruction();
                 default: pop_SS();
             }
+            default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
+                                    [Eb,Gb], [Ev,Gv],
+                                    [Gb,Eb], [Gv,Ev],
+                                    [rAl,Ib], [rAx,Iz]);
         }
         0x03: decode OPCODE_OP_BOTTOM3 {
-            0x0: sbb_Eb_Gb();
-            0x1: sbb_Ev_Gv();
-            0x2: sbb_Gb_Eb();
-            0x3: sbb_Gv_Ev();
-            0x4: sbb_Al_Ib();
-            0x5: sbb_rAX_Iz();
             0x6: decode MODE_SUBMODE {
                 0x0: This_should_be_an_illegal_instruction();
                 default: push_DS();
@@ -118,6 +110,10 @@
                 0x0: This_should_be_an_illegal_instruction();
                 default: pop_DS();
             }
+            default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
+                                    [Eb,Gb], [Ev,Gv],
+                                    [Gb,Eb], [Gv,Ev],
+                                    [rAl,Ib], [rAx,Iz]);
         }
         0x04: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -237,52 +233,54 @@
             }
         }
         0x10: decode OPCODE_OP_BOTTOM3 {
-            //0x0: group1_Eb_Ib();
-            0x0: decode MODRM_REG {
-                0x0: Inst::ADD(Eb,Ib);
-                0x1: Inst::OR(Eb,Ib);
-                0x2: adc_Eb_Ib();
-                0x3: sbb_Eb_Ib();
-                0x4: Inst::AND(Eb,Ib);
-                0x5: Inst::SUB(Eb,Ib);
-                0x6: Inst::XOR(Eb,Ib);
-                0x7: Inst::CMP(Eb,Ib);
-            }
-            //0x1: group1_Ev_Iz();
-            0x1: decode MODRM_REG {
-                0x0: Inst::ADD(Ev,Iz);
-                0x1: Inst::OR(Ev,Iz);
-                0x2: adc_Ev_Iz();
-                0x3: sbb_Ev_Iz();
-                0x4: Inst::AND(Ev,Iz);
-                0x5: Inst::SUB(Ev,Iz);
-                0x6: Inst::XOR(Ev,Iz);
-                0x7: Inst::CMP(Ev,Iz);
-            }
-            0x2: decode MODE_SUBMODE {
-                0x0: This_should_be_an_illegal_instruction();
-                //default: group1_Eb_Ib();
-                default: decode MODRM_REG {
-                    0x0: Inst::ADD(Eb,Ib);
-                    0x1: Inst::OR(Eb,Ib);
-                    0x2: adc_Eb_Ib();
-                    0x3: sbb_Eb_Ib();
-                    0x4: Inst::AND(Eb,Ib);
-                    0x5: Inst::SUB(Eb,Ib);
-                    0x6: Inst::XOR(Eb,Ib);
-                    0x7: Inst::CMP(Eb,Ib);
+            format Inst {
+                //0x0: group1_Eb_Ib();
+                0x0: decode MODRM_REG {
+                    0x0: ADD(Eb,Ib);
+                    0x1: OR(Eb,Ib);
+                    0x2: ADC(Eb,Ib);
+                    0x3: SBB(Eb,Ib);
+                    0x4: AND(Eb,Ib);
+                    0x5: SUB(Eb,Ib);
+                    0x6: XOR(Eb,Ib);
+                    0x7: CMP(Eb,Ib);
+                }
+                //0x1: group1_Ev_Iz();
+                0x1: decode MODRM_REG {
+                    0x0: ADD(Ev,Iz);
+                    0x1: OR(Ev,Iz);
+                    0x2: ADC(Ev,Iz);
+                    0x3: SBB(Ev,Iz);
+                    0x4: AND(Ev,Iz);
+                    0x5: SUB(Ev,Iz);
+                    0x6: XOR(Ev,Iz);
+                    0x7: CMP(Ev,Iz);
+                }
+                0x2: decode MODE_SUBMODE {
+                    0x0: WarnUnimpl::This_should_be_an_illegal_instruction();
+                    //default: group1_Eb_Ib();
+                    default: decode MODRM_REG {
+                        0x0: ADD(Eb,Ib);
+                        0x1: OR(Eb,Ib);
+                        0x2: ADC(Eb,Ib);
+                        0x3: SBB(Eb,Ib);
+                        0x4: AND(Eb,Ib);
+                        0x5: SUB(Eb,Ib);
+                        0x6: XOR(Eb,Ib);
+                        0x7: CMP(Eb,Ib);
+                    }
+                }
+                //0x3: group1_Ev_Ib();
+                0x3: decode MODRM_REG {
+                    0x0: ADD(Ev,Ib);
+                    0x1: OR(Ev,Ib);
+                    0x2: ADC(Ev,Ib);
+                    0x3: SBB(Ev,Ib);
+                    0x4: AND(Ev,Ib);
+                    0x5: SUB(Ev,Ib);
+                    0x6: XOR(Ev,Ib);
+                    0x7: CMP(Ev,Ib);
                 }
-            }
-            //0x3: group1_Ev_Ib();
-            0x3: decode MODRM_REG {
-                0x0: Inst::ADD(Ev,Ib);
-                0x1: Inst::OR(Ev,Ib);
-                0x2: adc_Ev_Ib();
-                0x3: sbb_Ev_Ib();
-                0x4: Inst::AND(Ev,Ib);
-                0x5: Inst::SUB(Ev,Ib);
-                0x6: Inst::XOR(Ev,Ib);
-                0x7: Inst::CMP(Ev,Ib);
             }
             0x4: Inst::TEST(Eb,Gb);
             0x5: Inst::TEST(Ev,Gv);
@@ -492,7 +490,7 @@
                 0x4: jmp_Ev();
                 0x5: jmp_Mp();
                 0x6: push_Ev();
-                0x7: This_should_be_an_illegal_instruction();
+                0x7: WarnUnimpl::This_should_be_an_illegal_instruction();
             }
         }
     }

diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index a8bad46532f6971e999be286ed3951690ab5fdc2..05aa6cd69e69c0ddd707263bd52b4dce2f8eee46 100644 (file)
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -165,6 +165,118 @@ def macroop SUB_P_R
     sub t1, t1, reg
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop ADC_R_R
+{
+    adc reg, reg, regm
+};
+
+def macroop ADC_R_I
+{
+    limm t1, imm
+    adc reg, reg, t1
+};
+
+def macroop ADC_M_I
+{
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    adc t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_P_I
+{
+    rdip t7
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    adc t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    adc t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_P_R
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    adc t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ADC_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    adc reg, reg, t1
+};
+
+def macroop ADC_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    adc reg, reg, t1
+};
+
+def macroop SBB_R_R
+{
+    sbb reg, reg, regm
+};
+
+def macroop SBB_R_I
+{
+    limm t1, imm
+    sbb reg, reg, t1
+};
+
+def macroop SBB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sbb reg, reg, t1
+};
+
+def macroop SBB_R_P
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    sbb reg, reg, t1
+};
+
+def macroop SBB_M_I
+{
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    sbb t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_P_I
+{
+    rdip t7
+    limm t2, imm
+    ld t1, ds, [scale, index, base], disp
+    sbb t1, t1, t2
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sbb t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SBB_P_R
+{
+    rdip t7
+    ld t1, ds, [scale, index, base], disp
+    sbb t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
 '''
 #let {{
 #    class ADC(Inst):

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 31ca8344de359aca1c1288f306e69c1597e4091e..d2002b4fb267e59ce52c50be65ffca97187a7504 100644 (file)
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -383,12 +383,18 @@ let {{
 
     defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
     defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
-    defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
-    defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
+    defineMicroRegOp('Adc', '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize);
+            ''')
+    defineMicroRegOp('Sbb', '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize);
+            ''', True)
     defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
     defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
     defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
-    defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
+    # defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
     defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
     defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
             elseCode='DestReg=DestReg;', cc=True)