i965: Mark TCS URB writes as having side effects.

This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing
reads and writes from being incorrectly scheduled.

Fixes rendering in GFXBench 4.0's tessellation demo.

For some reason, we haven't ever listed URB writes as having
side-effects.  This hasn't been a problem because in most stages, we
never read from the URB, and only write to each location once.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93526
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index efc24f92f586cca3542fd30853799263610c79be..0ac3f4a30fc7dfd91cf2cdf2cc2461cb9f7c430a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1022,6 +1022,7 @@ backend_instruction::has_side_effects() const
    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
    case FS_OPCODE_FB_WRITE:
    case SHADER_OPCODE_BARRIER:
+   case TCS_OPCODE_URB_WRITE:
    case TCS_OPCODE_RELEASE_INPUT:
       return true;
    default: