initial changes to decoder.hh and copied files from arch/sparc directory
authorKorey Sewell <ksewell@umich.edu>
Wed, 25 Jan 2006 19:43:47 +0000 (14:43 -0500)
committerKorey Sewell <ksewell@umich.edu>
Wed, 25 Jan 2006 19:43:47 +0000 (14:43 -0500)
arch/mips/isa_desc/bitfields.h:
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_desc/includes.h:
arch/mips/isa_desc/operands.h:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    copied from sparc ISA directory
arch/mips/isa_desc/decoder.h:
    decoder I started to work on...

--HG--
rename : arch/sparc/isa_desc/bitfields.h => arch/mips/isa_desc/bitfields.h
rename : arch/sparc/isa_desc/decoder.h => arch/mips/isa_desc/decoder.h
rename : arch/sparc/isa_desc/formats.h => arch/mips/isa_desc/formats.h
rename : arch/sparc/isa_desc/formats/basic.format => arch/mips/isa_desc/formats/basic.format
rename : arch/sparc/isa_desc/formats/branch.format => arch/mips/isa_desc/formats/branch.format
rename : arch/sparc/isa_desc/formats/integerop.format => arch/mips/isa_desc/formats/integerop.format
rename : arch/sparc/isa_desc/formats/mem.format => arch/mips/isa_desc/formats/mem.format
rename : arch/sparc/isa_desc/formats/noop.format => arch/mips/isa_desc/formats/noop.format
rename : arch/sparc/isa_desc/formats/trap.format => arch/mips/isa_desc/formats/trap.format
rename : arch/sparc/isa_desc/includes.h => arch/mips/isa_desc/includes.h
rename : arch/sparc/isa_desc/operands.h => arch/mips/isa_desc/operands.h
rename : arch/sparc/isa_traits.cc => arch/mips/isa_traits.cc
rename : arch/sparc/isa_traits.hh => arch/mips/isa_traits.hh
extra : convert_revision : d4f281960ecf2dce479fb665469c6f2c5dd3063e

26 files changed:
arch/mips/isa_desc/bitfields.h [new file with mode: 0644]
arch/mips/isa_desc/decoder.h [new file with mode: 0644]
arch/mips/isa_desc/formats.h [new file with mode: 0644]
arch/mips/isa_desc/formats/basic.format [new file with mode: 0644]
arch/mips/isa_desc/formats/branch.format [new file with mode: 0644]
arch/mips/isa_desc/formats/integerop.format [new file with mode: 0644]
arch/mips/isa_desc/formats/mem.format [new file with mode: 0644]
arch/mips/isa_desc/formats/noop.format [new file with mode: 0644]
arch/mips/isa_desc/formats/trap.format [new file with mode: 0644]
arch/mips/isa_desc/includes.h [new file with mode: 0644]
arch/mips/isa_desc/operands.h [new file with mode: 0644]
arch/mips/isa_traits.cc [new file with mode: 0644]
arch/mips/isa_traits.hh [new file with mode: 0644]
arch/sparc/isa_desc/bitfields.h [deleted file]
arch/sparc/isa_desc/decoder.h [deleted file]
arch/sparc/isa_desc/formats.h [deleted file]
arch/sparc/isa_desc/formats/basic.format [deleted file]
arch/sparc/isa_desc/formats/branch.format [deleted file]
arch/sparc/isa_desc/formats/integerop.format [deleted file]
arch/sparc/isa_desc/formats/mem.format [deleted file]
arch/sparc/isa_desc/formats/noop.format [deleted file]
arch/sparc/isa_desc/formats/trap.format [deleted file]
arch/sparc/isa_desc/includes.h [deleted file]
arch/sparc/isa_desc/operands.h [deleted file]
arch/sparc/isa_traits.cc [deleted file]
arch/sparc/isa_traits.hh [deleted file]

diff --git a/arch/mips/isa_desc/bitfields.h b/arch/mips/isa_desc/bitfields.h
new file mode 100644 (file)
index 0000000..b0ac575
--- /dev/null
@@ -0,0 +1,50 @@
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+// Bitfields are shared liberally between instruction formats, so they are
+// simply defined alphabetically
+
+def bitfield A         <29>;
+def bitfield CC02      <20>;
+def bitfield CC03      <25>;
+def bitfield CC04      <11>;
+def bitfield CC12      <21>;
+def bitfield CC13      <26>;
+def bitfield CC14      <12>;
+def bitfield CC2       <18>;
+def bitfield CMASK     <6:4>;
+def bitfield COND2     <28:25>;
+def bitfield COND4     <17:14>;
+def bitfield D16HI     <21:20>;
+def bitfield D16LO     <13:0>;
+def bitfield DISP19    <18:0>;
+def bitfield DISP22    <21:0>;
+def bitfield DISP30    <29:0>;
+def bitfield FCN       <29:26>;
+def bitfield I         <13>;
+def bitfield IMM_ASI   <12:5>;
+def bitfield IMM22     <21:0>;
+def bitfield MMASK     <3:0>;
+def bitfield OP                <31:30>;
+def bitfield OP2       <24:22>;
+def bitfield OP3       <24:19>;
+def bitfield OPF       <13:5>;
+def bitfield OPF_CC    <13:11>;
+def bitfield OPF_LOW5  <9:5>;
+def bitfield OPF_LOW6  <10:5>;
+def bitfield P         <19>;
+def bitfield RCOND2    <27:25>;
+def bitfield RCOND3    <12:10>;
+def bitfield RCOND4    <12:10>;
+def bitfield RD                <29:25>;
+def bitfield RS1       <18:14>;
+def bitfield RS2       <4:0>;
+def bitfield SHCNT32   <4:0>;
+def bitfield SHCNT64   <5:0>;
+def bitfield SIMM10    <9:0>;
+def bitfield SIMM11    <10:0>;
+def bitfield SIMM13    <12:0>;
+def bitfield SW_TRAP   <6:0>;
+def bitfield X         <12>;
diff --git a/arch/mips/isa_desc/decoder.h b/arch/mips/isa_desc/decoder.h
new file mode 100644 (file)
index 0000000..5d71968
--- /dev/null
@@ -0,0 +1,991 @@
+////////////////////////////////////////////////////////////////////
+//
+// The actual MIPS32 ISA decoder
+// -----------------------------
+// The following instructions are specified in the MIPS32 ISA
+// Specification. Decoding closely follows the style specified
+// in the MIPS32 ISAthe specification document starting with Table
+// A-2 (document available @ www.mips.com)
+//
+//
+decode OPCODE_HI default FailUnimpl::unknown() {
+
+    // Derived From ... Table A-2 MIPS32 ISA Manual
+    0x0: decode OPCODE_LO {
+
+        0x0: decode SPECIAL {
+            0x0:;
+            0x1:;
+            0x2:;
+            0x3:;
+            0x4:;
+            0x5:;
+            0x6:;
+        }
+
+        0x1: decode REGIMM {
+            0x0:;
+            0x1:;
+            0x2:;
+            0x3:;
+            0x4:;
+            0x5:;
+            0x6:;
+        }
+
+        format Jump {
+            0x2: j({{ }});
+            0x3: jal({{ }});
+        }
+
+        format Branch {
+            0x4: beq({{ }});
+            0x5: bne({{ }});
+            0x6: blez({{ }});
+            0x7: bgtz({{ }});
+        }
+    };
+
+    0x1: decode OPCODE_LO {
+        format IntImmediate {
+            0x0: addi({{ }});
+            0x1: addiu({{ }});
+            0x2: slti({{ }});
+            0x3: sltiu({{ }});
+            0x4: andi({{ }});
+            0x5: ori({{ }});
+            0x6: xori({{ }});
+            0x7: lui({{ }});
+        };
+    };
+
+    0x2: decode OPCODE_LO {
+        format FailUnimpl{
+            0x0: coprocessor_op({{ }});
+            0x1: coprocessor_op({{ }});
+            0x2: coprocessor_op({{ }});
+            0x3: coprocessor_op({{ }});
+        };
+
+        //MIPS obsolete instructions
+        0x4: beql({{ }});
+        0x5: bnel({{ }});
+        0x6: blezl({{ }});
+        0x7: bgtzl({{ }});
+    };
+
+    0x3: decode OPCODE_LO {
+        format FailUnimpl{
+            0x0: reserved({{ }})
+            0x1: reserved({{ }})
+            0x2: reserved({{ }})
+            0x3: reserved({{ }})
+            0x5: reserved({{ }})
+            0x6: reserved({{ }})
+        };
+
+        4: decode SPECIAL2 {
+            0x0:;
+            0x1:;
+            0x2:;
+            0x3:;
+            0x4:;
+            0x5:;
+            0x6:;
+        }
+
+        7: decode SPECIAL3 {
+            0x0:;
+            0x1:;
+            0x2:;
+            0x3:;
+            0x4:;
+            0x5:;
+            0x6:;
+        }
+    };
+
+    0x4: decode OPCODE_LO {
+        format LoadMemory{
+            0x0: lb({{ }});
+            0x1: lh({{ }});
+            0x2: lwl({{ }});
+            0x3: lw({{ }});
+            0x4: lbu({{ }});
+            0x5: lhu({{ }});
+            0x6: lhu({{ }});
+        };
+
+        0x7: FailUnimpl::reserved({{ }});
+    };
+
+    0x5: decode OPCODE_LO {
+        format StoreMemory{
+            0x0: sb({{ }});
+            0x1: sh({{ }});
+            0x2: swl({{ }});
+            0x3: sw({{ }});
+            0x6: swr({{ }});
+        };
+
+        format FailUnimpl{
+            0x4: reserved({{ }});
+            0x5: reserved({{ }});
+            0x2: cache({{ }});
+        };
+
+    };
+
+    0x6: decode OPCODE_LO {
+        format LoadMemory{
+            0x0: ll({{ }});
+            0x1: lwc1({{ }});
+            0x5: ldc1({{ }});
+        };
+
+        format FailUnimpl{
+            0x2: lwc2({{ }});
+            0x3: pref({{ }});
+            0x4: reserved({{ }});
+            0x6: ldc2({{ }});
+            0x7: reserved({{ }});
+        };
+
+    };
+
+    0x7: decode OPCODE_LO {
+        format StoreMemory{
+            0x0: sc({{ }});
+            0x1: swc1({{ }});
+            0x5: sdc1({{ }});
+        };
+
+        format FailUnimpl{
+            0x2: swc2({{ }});
+            0x3: reserved({{ }});
+            0x4: reserved({{ }});
+            0x6: sdc2({{ }});
+            0x7: reserved({{ }});
+        };
+
+    };
+
+
+    //Table 3-1 CPU Arithmetic Instructions ( )
+    format IntegerOperate {
+
+        0x10: decode INTFUNC { // integer arithmetic operations
+
+           //ADD Add Word
+
+           //ADDI Add Immediate Word
+
+           //ADDIU Add Immediate Unsigned Word
+
+           //ADDU Add Unsigned Word
+
+            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
+            0x40: addlv({{
+                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
+                // signed overflow occurs when operands have same sign
+                // and sign of result does not match.
+                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+                    fault = Integer_Overflow_Fault;
+                Rc.sl = tmp;
+            }});
+            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
+            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
+
+            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
+            0x60: addqv({{
+                uint64_t tmp = Ra + Rb_or_imm;
+                // signed overflow occurs when operands have same sign
+                // and sign of result does not match.
+                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
+                    fault = Integer_Overflow_Fault;
+                Rc = tmp;
+            }});
+            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
+            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
+
+            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
+            0x49: sublv({{
+                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
+                // signed overflow detection is same as for add,
+                // except we need to look at the *complemented*
+                // sign bit of the subtrahend (Rb), i.e., if the initial
+                // signs are the *same* then no overflow can occur
+                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+                    fault = Integer_Overflow_Fault;
+                Rc.sl = tmp;
+            }});
+            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
+            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
+
+            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
+            0x69: subqv({{
+                uint64_t tmp  = Ra - Rb_or_imm;
+                // signed overflow detection is same as for add,
+                // except we need to look at the *complemented*
+                // sign bit of the subtrahend (Rb), i.e., if the initial
+                // signs are the *same* then no overflow can occur
+                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
+                    fault = Integer_Overflow_Fault;
+                Rc = tmp;
+            }});
+            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
+            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
+
+            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
+            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
+            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
+            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
+            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
+
+            0x0f: cmpbge({{
+                int hi = 7;
+                int lo = 0;
+                uint64_t tmp = 0;
+                for (int i = 0; i < 8; ++i) {
+                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
+                    hi += 8;
+                    lo += 8;
+                }
+                Rc = tmp;
+            }});
+        }
+
+        0x11: decode INTFUNC { // integer logical operations
+
+            0x00: and({{ Rc = Ra & Rb_or_imm; }});
+            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
+            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
+            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
+            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
+            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
+
+            // conditional moves
+            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
+            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
+            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
+            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
+            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
+            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
+            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
+            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
+
+            // For AMASK, RA must be R31.
+            0x61: decode RA {
+                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
+            }
+
+            // For IMPLVER, RA must be R31 and the B operand
+            // must be the immediate value 1.
+            0x6c: decode RA {
+                31: decode IMM {
+                    1: decode INTIMM {
+                        // return EV5 for FULL_SYSTEM and EV6 otherwise
+                        1: implver({{
+#if FULL_SYSTEM
+                             Rc = 1;
+#else
+                             Rc = 2;
+#endif
+                        }});
+                    }
+                }
+            }
+
+#if FULL_SYSTEM
+            // The mysterious 11.25...
+            0x25: WarnUnimpl::eleven25();
+#endif
+        }
+
+        0x12: decode INTFUNC {
+            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
+            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
+            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
+
+            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
+            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
+            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
+            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
+
+            0x52: mskwh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
+            }});
+            0x62: msklh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
+            }});
+            0x72: mskqh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
+            }});
+
+            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
+            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
+            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
+            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
+
+            0x5a: extwh({{
+                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
+            0x6a: extlh({{
+                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
+            0x7a: extqh({{
+                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
+
+            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
+            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
+            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
+            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
+
+            0x57: inswh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
+            }});
+            0x67: inslh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
+            }});
+            0x77: insqh({{
+                int bv = Rb_or_imm<2:0>;
+                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
+            }});
+
+            0x30: zap({{
+                uint64_t zapmask = 0;
+                for (int i = 0; i < 8; ++i) {
+                    if (Rb_or_imm<i:>)
+                        zapmask |= (mask(8) << (i * 8));
+                }
+                Rc = Ra & ~zapmask;
+            }});
+            0x31: zapnot({{
+                uint64_t zapmask = 0;
+                for (int i = 0; i < 8; ++i) {
+                    if (!Rb_or_imm<i:>)
+                        zapmask |= (mask(8) << (i * 8));
+                }
+                Rc = Ra & ~zapmask;
+            }});
+        }
+
+        0x13: decode INTFUNC { // integer multiplies
+            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
+            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
+            0x30: umulh({{
+                uint64_t hi, lo;
+                mul128(Ra, Rb_or_imm, hi, lo);
+                Rc = hi;
+            }}, IntMultOp);
+            0x40: mullv({{
+                // 32-bit multiply with trap on overflow
+                int64_t Rax = Ra.sl;   // sign extended version of Ra.sl
+                int64_t Rbx = Rb_or_imm.sl;
+                int64_t tmp = Rax * Rbx;
+                // To avoid overflow, all the upper 32 bits must match
+                // the sign bit of the lower 32.  We code this as
+                // checking the upper 33 bits for all 0s or all 1s.
+                uint64_t sign_bits = tmp<63:31>;
+                if (sign_bits != 0 && sign_bits != mask(33))
+                    fault = Integer_Overflow_Fault;
+                Rc.sl = tmp<31:0>;
+            }}, IntMultOp);
+            0x60: mulqv({{
+                // 64-bit multiply with trap on overflow
+                uint64_t hi, lo;
+                mul128(Ra, Rb_or_imm, hi, lo);
+                // all the upper 64 bits must match the sign bit of
+                // the lower 64
+                if (!((hi == 0 && lo<63:> == 0) ||
+                      (hi == mask(64) && lo<63:> == 1)))
+                    fault = Integer_Overflow_Fault;
+                Rc = lo;
+            }}, IntMultOp);
+        }
+
+        0x1c: decode INTFUNC {
+            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
+            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+            0x32: ctlz({{
+                             uint64_t count = 0;
+                             uint64_t temp = Rb;
+                             if (temp<63:32>) temp >>= 32; else count += 32;
+                             if (temp<31:16>) temp >>= 16; else count += 16;
+                             if (temp<15:8>) temp >>= 8; else count += 8;
+                             if (temp<7:4>) temp >>= 4; else count += 4;
+                             if (temp<3:2>) temp >>= 2; else count += 2;
+                             if (temp<1:1>) temp >>= 1; else count += 1;
+                             if ((temp<0:0>) != 0x1) count += 1;
+                             Rc = count;
+                           }}, IntAluOp);
+
+            0x33: cttz({{
+                             uint64_t count = 0;
+                             uint64_t temp = Rb;
+                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
+                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
+                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
+                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
+                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+                             if (!(temp<0:0> & ULL(0x1))) count += 1;
+                             Rc = count;
+                           }}, IntAluOp);
+
+            format FailUnimpl {
+                0x30: ctpop();
+                0x31: perr();
+                0x34: unpkbw();
+                0x35: unpkbl();
+                0x36: pkwb();
+                0x37: pklb();
+                0x38: minsb8();
+                0x39: minsw4();
+                0x3a: minub8();
+                0x3b: minuw4();
+                0x3c: maxub8();
+                0x3d: maxuw4();
+                0x3e: maxsb8();
+                0x3f: maxsw4();
+            }
+
+            format BasicOperateWithNopCheck {
+                0x70: decode RB {
+                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
+                }
+                0x78: decode RB {
+                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
+                              FloatCvtOp);
+                }
+            }
+        }
+    }
+
+    //Table 3-2 CPU Branch and Jump Instructions ( )
+    //Table 3-10 Obsolete CPU Branch Instructions ( )
+
+    //Table 3-3 CPU Instruction Control Instructions ( )
+
+    //Table 3-4 CPU Load, Store, and Memory Control Instructions ( )
+
+    //Table 3-5 CPU Logical Instructions ( )
+
+    //Table 3-6 CPU Insert/Extract Instructions ( )
+
+    //Table 3-7 CPU Move Instructions ( )
+
+    //Table 3-9 CPU Trap Instructions ( )
+
+    //Table 3-11 FPU Arithmetic Instructions ( )
+
+    //Table 3-12 FPU Branch Instructions ( )
+    //Table 3-17 Obsolete  FPU Branch Instructions ()
+
+    //Table 3-13 FPU Compare Instructions ( )
+
+    //Table 3-14 FPU Convert Instructions ( )
+
+    //Table 3-15 FPU Load, Store, and Memory Control Instructions ( )
+
+    //Table 3-16 FPU Move Instructions ( )
+
+    //Tables 3-18 thru 3-22 are Co-Processor Instructions ( )
+
+    //Table 3-23 Privileged Instructions ( )
+
+    //Table 3-24 EJTAG Instructions ( )
+
+
+
+
+    format LoadAddress {
+        0x08: lda({{ Ra = Rb + disp; }});
+        0x09: ldah({{ Ra = Rb + (disp << 16); }});
+    }
+
+    format LoadOrNop {
+        0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
+        0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
+        0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
+        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
+        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
+        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
+        0x20: copy_load({{EA = Ra;}},
+                        {{fault = xc->copySrcTranslate(EA);}},
+                        IsMemRef, IsLoad, IsCopy);
+    }
+
+    format LoadOrPrefetch {
+        0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
+        0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
+        // IsFloating flag on lds gets the prefetch to disassemble
+        // using f31 instead of r31... funcitonally it's unnecessary
+        0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
+                  PF_EXCLUSIVE, IsFloating);
+    }
+
+    format Store {
+        0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
+        0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
+        0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
+        0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
+        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
+        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
+        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
+        0x24: copy_store({{EA = Rb;}},
+                         {{fault = xc->copy(EA);}},
+                         IsMemRef, IsStore, IsCopy);
+    }
+
+    format StoreCond {
+        0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
+                    {{
+                        uint64_t tmp = Mem_write_result;
+                        // see stq_c
+                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
+                    }}, LOCKED);
+        0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
+                    {{
+                        uint64_t tmp = Mem_write_result;
+                        // If the write operation returns 0 or 1, then
+                        // this was a conventional store conditional,
+                        // and the value indicates the success/failure
+                        // of the operation.  If another value is
+                        // returned, then this was a Turbolaser
+                        // mailbox access, and we don't update the
+                        // result register at all.
+                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
+                    }}, LOCKED);
+    }
+
+
+
+    // Conditional branches.
+    format CondBranch {
+        0x39: beq({{ cond = (Ra == 0); }});
+        0x3d: bne({{ cond = (Ra != 0); }});
+        0x3e: bge({{ cond = (Ra.sq >= 0); }});
+        0x3f: bgt({{ cond = (Ra.sq >  0); }});
+        0x3b: ble({{ cond = (Ra.sq <= 0); }});
+        0x3a: blt({{ cond = (Ra.sq < 0); }});
+        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
+        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
+
+        0x31: fbeq({{ cond = (Fa == 0); }});
+        0x35: fbne({{ cond = (Fa != 0); }});
+        0x36: fbge({{ cond = (Fa >= 0); }});
+        0x37: fbgt({{ cond = (Fa >  0); }});
+        0x33: fble({{ cond = (Fa <= 0); }});
+        0x32: fblt({{ cond = (Fa < 0); }});
+    }
+
+    // unconditional branches
+    format UncondBranch {
+        0x30: br();
+        0x34: bsr(IsCall);
+    }
+
+    // indirect branches
+    0x1a: decode JMPFUNC {
+        format Jump {
+            0: jmp();
+            1: jsr(IsCall);
+            2: ret(IsReturn);
+            3: jsr_coroutine(IsCall, IsReturn);
+        }
+    }
+
+    // Square root and integer-to-FP moves
+    0x14: decode FP_SHORTFUNC {
+        // Integer to FP register moves must have RB == 31
+        0x4: decode RB {
+            31: decode FP_FULLFUNC {
+                format BasicOperateWithNopCheck {
+                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
+                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
+                    0x014: FailUnimpl::itoff();        // VAX-format conversion
+                }
+            }
+        }
+
+        // Square root instructions must have FA == 31
+        0xb: decode FA {
+            31: decode FP_TYPEFUNC {
+                format FloatingPointOperate {
+#if SS_COMPATIBLE_FP
+                    0x0b: sqrts({{
+                        if (Fb < 0.0)
+                            fault = Arithmetic_Fault;
+                        Fc = sqrt(Fb);
+                    }}, FloatSqrtOp);
+#else
+                    0x0b: sqrts({{
+                        if (Fb.sf < 0.0)
+                            fault = Arithmetic_Fault;
+                        Fc.sf = sqrt(Fb.sf);
+                    }}, FloatSqrtOp);
+#endif
+                    0x2b: sqrtt({{
+                        if (Fb < 0.0)
+                            fault = Arithmetic_Fault;
+                        Fc = sqrt(Fb);
+                    }}, FloatSqrtOp);
+                }
+            }
+        }
+
+        // VAX-format sqrtf and sqrtg are not implemented
+        0xa: FailUnimpl::sqrtfg();
+    }
+
+    // IEEE floating point
+    0x16: decode FP_SHORTFUNC_TOP2 {
+        // The top two bits of the short function code break this
+        // space into four groups: binary ops, compares, reserved, and
+        // conversions.  See Table 4-12 of AHB.  There are different
+        // special cases in these different groups, so we decode on
+        // these top two bits first just to select a decode strategy.
+        // Most of these instructions may have various trapping and
+        // rounding mode flags set; these are decoded in the
+        // FloatingPointDecode template used by the
+        // FloatingPointOperate format.
+
+        // add/sub/mul/div: just decode on the short function code
+        // and source type.  All valid trapping and rounding modes apply.
+        0: decode FP_TRAPMODE {
+            // check for valid trapping modes here
+            0,1,5,7: decode FP_TYPEFUNC {
+                   format FloatingPointOperate {
+#if SS_COMPATIBLE_FP
+                       0x00: adds({{ Fc = Fa + Fb; }});
+                       0x01: subs({{ Fc = Fa - Fb; }});
+                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
+                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
+#else
+                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
+                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
+                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
+                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
+#endif
+
+                       0x20: addt({{ Fc = Fa + Fb; }});
+                       0x21: subt({{ Fc = Fa - Fb; }});
+                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
+                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
+                   }
+             }
+        }
+
+        // Floating-point compare instructions must have the default
+        // rounding mode, and may use the default trapping mode or
+        // /SU.  Both trapping modes are treated the same by M5; the
+        // only difference on the real hardware (as far a I can tell)
+        // is that without /SU you'd get an imprecise trap if you
+        // tried to compare a NaN with something else (instead of an
+        // "unordered" result).
+        1: decode FP_FULLFUNC {
+            format BasicOperateWithNopCheck {
+                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
+                                     FloatCmpOp);
+                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
+                                     FloatCmpOp);
+                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
+                                     FloatCmpOp);
+                0x0a4, 0x5a4: cmptun({{ // unordered
+                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
+                }}, FloatCmpOp);
+            }
+        }
+
+        // The FP-to-integer and integer-to-FP conversion insts
+        // require that FA be 31.
+        3: decode FA {
+            31: decode FP_TYPEFUNC {
+                format FloatingPointOperate {
+                    0x2f: decode FP_ROUNDMODE {
+                        format FPFixedRounding {
+                            // "chopped" i.e. round toward zero
+                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
+                                     Chopped);
+                            // round to minus infinity
+                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
+                                     MinusInfinity);
+                        }
+                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
+                    }
+
+                    // The cvtts opcode is overloaded to be cvtst if the trap
+                    // mode is 2 or 6 (which are not valid otherwise)
+                    0x2c: decode FP_FULLFUNC {
+                        format BasicOperateWithNopCheck {
+                            // trap on denorm version "cvtst/s" is
+                            // simulated same as cvtst
+                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
+                        }
+                      default: cvtts({{ Fc.sf = Fb; }});
+                    }
+
+                    // The trapping mode for integer-to-FP conversions
+                    // must be /SUI or nothing; /U and /SU are not
+                    // allowed.  The full set of rounding modes are
+                    // supported though.
+                    0x3c: decode FP_TRAPMODE {
+                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
+                    }
+                    0x3e: decode FP_TRAPMODE {
+                        0,7: cvtqt({{ Fc    = Fb.sq; }});
+                    }
+                }
+            }
+        }
+    }
+
+    // misc FP operate
+    0x17: decode FP_FULLFUNC {
+        format BasicOperateWithNopCheck {
+            0x010: cvtlq({{
+                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
+            }});
+            0x030: cvtql({{
+                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+            }});
+
+            // We treat the precise & imprecise trapping versions of
+            // cvtql identically.
+            0x130, 0x530: cvtqlv({{
+                // To avoid overflow, all the upper 32 bits must match
+                // the sign bit of the lower 32.  We code this as
+                // checking the upper 33 bits for all 0s or all 1s.
+                uint64_t sign_bits = Fb.uq<63:31>;
+                if (sign_bits != 0 && sign_bits != mask(33))
+                    fault = Integer_Overflow_Fault;
+                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+            }});
+
+            0x020: cpys({{  // copy sign
+                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
+            }});
+            0x021: cpysn({{ // copy sign negated
+                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
+            }});
+            0x022: cpyse({{ // copy sign and exponent
+                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
+            }});
+
+            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
+            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
+            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
+            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
+            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
+            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
+
+            0x024: mt_fpcr({{ FPCR = Fa.uq; }});
+            0x025: mf_fpcr({{ Fa.uq = FPCR; }});
+        }
+    }
+
+    // miscellaneous mem-format ops
+    0x18: decode MEMFUNC {
+        format WarnUnimpl {
+            0x8000: fetch();
+            0xa000: fetch_m();
+            0xe800: ecb();
+        }
+
+        format MiscPrefetch {
+            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
+                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
+                         IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
+                         NO_FAULT);
+        }
+
+        format BasicOperate {
+            0xc000: rpcc({{
+#if FULL_SYSTEM
+        /* Rb is a fake dependency so here is a fun way to get
+         * the parser to understand that.
+         */
+                Ra = xc->readIpr(MipsISA::IPR_CC, fault) + (Rb & 0);
+
+#else
+                Ra = curTick;
+#endif
+            }});
+
+            // All of the barrier instructions below do nothing in
+            // their execute() methods (hence the empty code blocks).
+            // All of their functionality is hard-coded in the
+            // pipeline based on the flags IsSerializing,
+            // IsMemBarrier, and IsWriteBarrier.  In the current
+            // detailed CPU model, the execute() function only gets
+            // called at fetch, so there's no way to generate pipeline
+            // behavior at any other stage.  Once we go to an
+            // exec-in-exec CPU model we should be able to get rid of
+            // these flags and implement this behavior via the
+            // execute() methods.
+
+            // trapb is just a barrier on integer traps, where excb is
+            // a barrier on integer and FP traps.  "EXCB is thus a
+            // superset of TRAPB." (Mips ARM, Sec 4.11.4) We treat
+            // them the same though.
+            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
+            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
+        }
+
+#if FULL_SYSTEM
+        format BasicOperate {
+            0xe000: rc({{
+                Ra = xc->readIntrFlag();
+                xc->setIntrFlag(0);
+            }}, IsNonSpeculative);
+            0xf000: rs({{
+                Ra = xc->readIntrFlag();
+                xc->setIntrFlag(1);
+            }}, IsNonSpeculative);
+        }
+#else
+        format FailUnimpl {
+            0xe000: rc();
+            0xf000: rs();
+        }
+#endif
+    }
+
+#if FULL_SYSTEM
+    0x00: CallPal::call_pal({{
+        if (!palValid ||
+            (palPriv
+             && xc->readIpr(MipsISA::IPR_ICM, fault) != MipsISA::mode_kernel)) {
+            // invalid pal function code, or attempt to do privileged
+            // PAL call in non-kernel mode
+            fault = Unimplemented_Opcode_Fault;
+        }
+        else {
+            // check to see if simulator wants to do something special
+            // on this PAL call (including maybe suppress it)
+            bool dopal = xc->simPalCheck(palFunc);
+
+            if (dopal) {
+                MipsISA::swap_palshadow(&xc->xcBase()->regs, true);
+                xc->setIpr(MipsISA::IPR_EXC_ADDR, NPC);
+                NPC = xc->readIpr(MipsISA::IPR_PAL_BASE, fault) + palOffset;
+            }
+        }
+    }}, IsNonSpeculative);
+#else
+    0x00: decode PALFUNC {
+        format EmulatedCallPal {
+            0x00: halt ({{
+                SimExit(curTick, "halt instruction encountered");
+            }}, IsNonSpeculative);
+            0x83: callsys({{
+                xc->syscall();
+            }}, IsNonSpeculative, IsSerializeAfter);
+            // Read uniq reg into ABI return value register (r0)
+            0x9e: rduniq({{ R0 = Runiq; }});
+            // Write uniq reg with value from ABI arg register (r16)
+            0x9f: wruniq({{ Runiq = R16; }});
+        }
+    }
+#endif
+
+#if FULL_SYSTEM
+    format HwLoadStore {
+        0x1b: decode HW_LDST_QUAD {
+            0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
+            1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+        }
+
+        0x1f: decode HW_LDST_COND {
+            0: decode HW_LDST_QUAD {
+                0: hw_st({{ EA = (Rb + disp) & ~3; }},
+                         {{ Mem.ul = Ra<31:0>; }}, L);
+                1: hw_st({{ EA = (Rb + disp) & ~7; }},
+                         {{ Mem.uq = Ra.uq; }}, Q);
+            }
+
+            1: FailUnimpl::hw_st_cond();
+        }
+    }
+
+    format HwMoveIPR {
+        0x19: hw_mfpr({{
+            // this instruction is only valid in PAL mode
+            if (!xc->inPalMode()) {
+                fault = Unimplemented_Opcode_Fault;
+            }
+            else {
+                Ra = xc->readIpr(ipr_index, fault);
+            }
+        }});
+        0x1d: hw_mtpr({{
+            // this instruction is only valid in PAL mode
+            if (!xc->inPalMode()) {
+                fault = Unimplemented_Opcode_Fault;
+            }
+            else {
+                xc->setIpr(ipr_index, Ra);
+                if (traceData) { traceData->setData(Ra); }
+            }
+        }});
+    }
+
+    format BasicOperate {
+        0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
+
+        // M5 special opcodes use the reserved 0x01 opcode space
+        0x01: decode M5FUNC {
+            0x00: arm({{
+                MipsPseudo::arm(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x01: quiesce({{
+                MipsPseudo::quiesce(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x10: ivlb({{
+                MipsPseudo::ivlb(xc->xcBase());
+            }}, No_OpClass, IsNonSpeculative);
+            0x11: ivle({{
+                MipsPseudo::ivle(xc->xcBase());
+            }}, No_OpClass, IsNonSpeculative);
+            0x20: m5exit_old({{
+                MipsPseudo::m5exit_old(xc->xcBase());
+            }}, No_OpClass, IsNonSpeculative);
+            0x21: m5exit({{
+                MipsPseudo::m5exit(xc->xcBase());
+            }}, No_OpClass, IsNonSpeculative);
+            0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
+            0x40: resetstats({{
+                MipsPseudo::resetstats(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x41: dumpstats({{
+                MipsPseudo::dumpstats(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x42: dumpresetstats({{
+                MipsPseudo::dumpresetstats(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x43: m5checkpoint({{
+                MipsPseudo::m5checkpoint(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x50: m5readfile({{
+                MipsPseudo::readfile(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x51: m5break({{
+                MipsPseudo::debugbreak(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x52: m5switchcpu({{
+                MipsPseudo::switchcpu(xc->xcBase());
+            }}, IsNonSpeculative);
+            0x53: m5addsymbol({{
+                MipsPseudo::addsymbol(xc->xcBase());
+            }}, IsNonSpeculative);
+
+        }
+    }
+#endif
+}
+
diff --git a/arch/mips/isa_desc/formats.h b/arch/mips/isa_desc/formats.h
new file mode 100644 (file)
index 0000000..733a093
--- /dev/null
@@ -0,0 +1,19 @@
+//Include the basic format
+//Templates from this format are used later
+##include "m5/arch/sparc/isa_desc/formats/basic.format"
+
+//Include the integerOp and integerOpCc format
+##include "m5/arch/sparc/isa_desc/formats/integerop.format"
+
+//Include the mem format
+##include "m5/arch/sparc/isa_desc/formats/mem.format"
+
+//Include the trap format
+##include "m5/arch/sparc/isa_desc/formats/trap.format"
+
+//Include the branch format
+##include "m5/arch/sparc/isa_desc/formats/branch.format"
+
+//Include the noop format
+##include "m5/arch/sparc/isa_desc/formats/noop.format"
+
diff --git a/arch/mips/isa_desc/formats/basic.format b/arch/mips/isa_desc/formats/basic.format
new file mode 100644 (file)
index 0000000..1994df4
--- /dev/null
@@ -0,0 +1,65 @@
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+        /**
+         * Static instruction class for "%(mnemonic)s".
+         */
+        class %(class_name)s : public %(base_class)s
+        {
+        public:
+                /// Constructor.
+                %(class_name)s(MachInst machInst);
+                %(BasicExecDeclare)s
+    };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+        inline %(class_name)s::%(class_name)s(MachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+        {
+                %(constructor)s;
+        }
+}};
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = No_Fault;
+
+                %(fp_enable_check)s;
+                %(op_decl)s;
+                %(op_rd)s;
+                %(code)s;
+
+                if(fault == No_Fault)
+                {
+                        %(op_wb)s;
+                }
+                return fault;
+        }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+        return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+        return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format... used only for a few misc. insts
+def format BasicOperate(code, *flags) {{
+        iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa_desc/formats/branch.format b/arch/mips/isa_desc/formats/branch.format
new file mode 100644 (file)
index 0000000..c4c0a90
--- /dev/null
@@ -0,0 +1,66 @@
+////////////////////////////////////////////////////////////////////
+//
+// Branch instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Branch : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template BranchExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Attempt to execute the instruction
+                try
+                {
+                        checkPriv;
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Branch(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = BranchExecute.subst(iop)
+}};
diff --git a/arch/mips/isa_desc/formats/integerop.format b/arch/mips/isa_desc/formats/integerop.format
new file mode 100644 (file)
index 0000000..275a346
--- /dev/null
@@ -0,0 +1,110 @@
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class IntegerOp : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template IntegerExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //These are set to constants when the execute method
+                //is generated
+                bool useCc = ;
+                bool checkPriv = ;
+
+                //Attempt to execute the instruction
+                try
+                {
+                        checkPriv;
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+                if(useCc)
+                {
+                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
+                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
+                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
+                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
+                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
+                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
+                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
+                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+                }
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOp(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        checkPriv = (code.find('checkPriv') != -1)
+        code.replace('checkPriv', '')
+        if checkPriv:
+                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+        else:
+                code.replace('checkPriv;', '')
+        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+                       ('xvValue', '0'), ('xcValue', '0')):
+                code.replace(marker, value)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = IntegerExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        checkPriv = (code.find('checkPriv') != -1)
+        code.replace('checkPriv', '')
+        if checkPriv:
+                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+        else:
+                code.replace('checkPriv;', '')
+        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
+                       ('xvValue', xvValue), ('xcValue', xcValue)):
+                code.replace(marker, value)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = IntegerExecute.subst(iop)
+}};
diff --git a/arch/mips/isa_desc/formats/mem.format b/arch/mips/isa_desc/formats/mem.format
new file mode 100644 (file)
index 0000000..abc00b6
--- /dev/null
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////
+//
+// Mem instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Mem : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template MemExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Attempt to execute the instruction
+                try
+                {
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        ea_code
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Mem(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+}};
+
+def format Cas(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = R1;');
+}};
diff --git a/arch/mips/isa_desc/formats/noop.format b/arch/mips/isa_desc/formats/noop.format
new file mode 100644 (file)
index 0000000..bc83e32
--- /dev/null
@@ -0,0 +1,47 @@
+////////////////////////////////////////////////////////////////////
+//
+// Noop instruction
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Noop : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template NoopExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Nothing to see here, move along
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Noop(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = NoopExecute.subst(iop)
+}};
diff --git a/arch/mips/isa_desc/formats/trap.format b/arch/mips/isa_desc/formats/trap.format
new file mode 100644 (file)
index 0000000..bee77fe
--- /dev/null
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////
+//
+// Trap instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Trap : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template TrapExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Call into the trap handler with the appropriate fault
+                return No_Fault;
+        }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Trap(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = TrapExecute.subst(iop)
+}};
diff --git a/arch/mips/isa_desc/includes.h b/arch/mips/isa_desc/includes.h
new file mode 100644 (file)
index 0000000..ff7cb7d
--- /dev/null
@@ -0,0 +1,40 @@
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <sstream>
+#include <iostream>
+#include <iomanip>
+
+#include "cpu/static_inst.hh"
+#include "traps.hh"
+#include "mem/mem_req.hh"  // some constructors use MemReq flags
+}};
+
+output decoder {{
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+}};
+
+output exec {{
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#ifdef FULL_SYSTEM
+//#include "arch/alpha/pseudo_inst.hh"
+#endif
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "sim/sim_exit.hh"
+}};
+
diff --git a/arch/mips/isa_desc/operands.h b/arch/mips/isa_desc/operands.h
new file mode 100644 (file)
index 0000000..77de6c9
--- /dev/null
@@ -0,0 +1,33 @@
+def operand_types {{
+    'sb' : ('signed int', 8),
+    'ub' : ('unsigned int', 8),
+    'shw' : ('signed int', 16),
+    'uhw' : ('unsigned int', 16),
+    'sw' : ('signed int', 32),
+    'uw' : ('unsigned int', 32),
+    'sdw' : ('signed int', 64),
+    'udw' : ('unsigned int', 64),
+    'sf' : ('float', 32),
+    'df' : ('float', 64),
+    'qf' : ('float', 128)
+}};
+
+def operands {{
+    # Int regs default to unsigned, but code should not count on this.
+    # For clarity, descriptions that depend on unsigned behavior should
+    # explicitly specify '.uq'.
+    'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
+    'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
+    'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
+    #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
+    #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
+    #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
+    'Mem': MemOperandTraits('udw', None,
+                            ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+    #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
+    #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
+    #'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+    # The next two are hacks for non-full-system call-pal emulation
+    #'R0':  IntRegOperandTraits('uq', '0', None, 1),
+    #'R16': IntRegOperandTraits('uq', '16', None, 1)
+}};
diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
new file mode 100644 (file)
index 0000000..c7a25f8
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/sparc/isa_traits.hh"
+#include "cpu/static_inst.hh"
+#include "sim/serialize.hh"
+
+// Alpha UNOP (ldq_u r31,0(r0))
+const MachInst SPARCISA::NoopMachInst = 0x2ffe0000;
+
+void
+SPARCISA::RegFile::serialize(std::ostream &os)
+{
+    intRegFile.serialize(os);
+    floatRegFile.serialize(os);
+    miscRegs.serialize(os);
+    SERIALIZE_SCALAR(pc);
+    SERIALIZE_SCALAR(npc);
+}
+
+
+void
+AlphaISA::RegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+    intRegFile.unserialize(cp, section);
+    floatRegFile.unserialize(cp, section);
+    miscRegs.unserialize(cp, section);
+    UNSERIALIZE_SCALAR(pc);
+    UNSERIALIZE_SCALAR(npc);
+}
+
+#endif //FULL_SYSTEM
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
new file mode 100644 (file)
index 0000000..9513b99
--- /dev/null
@@ -0,0 +1,528 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
+#define __ARCH_SPARC_ISA_TRAITS_HH__
+
+#include "arch/sparc/faults.hh"
+#include "base/misc.hh"
+#include "sim/host.hh"
+
+class FastCPU;
+//class FullCPU;
+//class Checkpoint;
+
+#define TARGET_SPARC
+
+template <class ISA> class StaticInst;
+template <class ISA> class StaticInstPtr;
+
+//namespace EV5
+//{
+//     int DTB_ASN_ASN(uint64_t reg);
+//     int ITB_ASN_ASN(uint64_t reg);
+//}
+
+class SPARCISA
+{
+        public:
+
+        typedef uint32_t MachInst;
+        typedef uint64_t Addr;
+        typedef uint8_t  RegIndex;
+
+        enum
+        {
+                MemoryEnd = 0xffffffffffffffffULL,
+
+                NumFloatRegs = 32,
+                NumMiscRegs = 32,
+
+                MaxRegsOfAnyType = 32,
+                // Static instruction parameters
+                MaxInstSrcRegs = 3,
+                MaxInstDestRegs = 2,
+
+                // Maximum trap level
+                MaxTL = 4
+
+                // semantically meaningful register indices
+                ZeroReg = 0,   // architecturally meaningful
+                // the rest of these depend on the ABI
+        }
+        typedef uint64_t IntReg;
+
+        class IntRegFile
+        {
+        private:
+                //For right now, let's pretend the register file is static
+                IntReg regs[32];
+        public:
+                IntReg & operator [] (RegIndex index)
+                {
+                        //Don't allow indexes outside of the 32 registers
+                        index &= 0x1F
+                        return regs[index];
+                }
+        };
+
+        void inline serialize(std::ostream & os)
+        {
+                SERIALIZE_ARRAY(regs, 32);
+        }
+
+        void inline unserialize(Checkpoint &*cp, const std::string &section)
+        {
+                UNSERIALIZE_ARRAY(regs, 32);
+        }
+
+        class FloatRegFile
+        {
+        private:
+                //By using the largest data type, we ensure everything
+                //is aligned correctly in memory
+                union
+                {
+                        double double rawRegs[16];
+                        uint64_t regDump[32];
+                };
+                class QuadRegs
+                {
+                        private:
+                                FloatRegFile * parent;
+                        public:
+                                QuadRegs(FloatRegFile * p) : parent(p) {;}
+                                double double & operator [] (RegIndex index)
+                                {
+                                        //Quad floats are index by the single
+                                        //precision register the start on,
+                                        //and only 16 should be accessed
+                                        index = (index >> 2) & 0xF;
+                                        return parent->rawRegs[index];
+                                }
+                };
+                class DoubleRegs
+                {
+                        private:
+                                FloatRegFile * parent;
+                        public:
+                                DoubleRegs(FloatRegFile * p) : parent(p) {;}
+                                double & operator [] (RegIndex index)
+                                {
+                                        //Double floats are index by the single
+                                        //precision register the start on,
+                                        //and only 32 should be accessed
+                                        index = (index >> 1) & 0x1F
+                                        return ((double [])parent->rawRegs)[index];
+                                }
+                }
+                class SingleRegs
+                {
+                        private:
+                                FloatRegFile * parent;
+                                public:
+                                SingleRegs(FloatRegFile * p) : parent(p) {;}
+                                double & operator [] (RegFile index)
+                                {
+                                        //Only 32 single floats should be accessed
+                                        index &= 0x1F
+                                        return ((float [])parent->rawRegs)[index];
+                                }
+                }
+        public:
+                void inline serialize(std::ostream & os)
+                {
+                        SERIALIZE_ARRAY(regDump, 32);
+                }
+
+                void inline unserialize(Checkpoint &* cp, std::string & section)
+                {
+                        UNSERIALIZE_ARRAY(regDump, 32);
+                }
+
+                QuadRegs quadRegs;
+                DoubleRegs doubleRegs;
+                SingleRegs singleRegs;
+                FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
+                {;}
+        };
+
+        // control register file contents
+        typedef uint64_t MiscReg;
+        // The control registers, broken out into fields
+        class MiscRegFile
+        {
+        public:
+                union
+                {
+                        uint16_t pstate;               // Process State Register
+                        struct
+                        {
+                                uint16_t ag:1;         // Alternate Globals
+                                uint16_t ie:1;         // Interrupt enable
+                                uint16_t priv:1;       // Privelege mode
+                                uint16_t am:1;         // Address mask
+                                uint16_t pef:1;                // PSTATE enable floating-point
+                                uint16_t red:1;                // RED (reset, error, debug) state
+                                uint16_t mm:2;         // Memory Model
+                                uint16_t tle:1;                // Trap little-endian
+                                uint16_t cle:1;                // Current little-endian
+                        } pstateFields;
+                }
+                uint64_t tba;          // Trap Base Address
+                union
+                {
+                        uint64_t y;            // Y (used in obsolete multiplication)
+                        struct
+                        {
+                                uint64_t value:32;     // The actual value stored in y
+                                const uint64_t :32;    // reserved bits
+                        } yFields;
+                }
+                uint8_t pil;           // Process Interrupt Register
+                uint8_t cwp;           // Current Window Pointer
+                uint16_t tt[MaxTL];    // Trap Type (Type of trap which occured on the previous level)
+                union
+                {
+                        uint8_t        ccr;            // Condition Code Register
+                        struct
+                        {
+                                union
+                                {
+                                        uint8_t icc:4; // 32-bit condition codes
+                                        struct
+                                        {
+                                                uint8_t c:1;   // Carry
+                                                uint8_t v:1;   // Overflow
+                                                uint8_t z:1;   // Zero
+                                                uint8_t n:1;   // Negative
+                                        } iccFields:4;
+                                } :4;
+                                union
+                                {
+                                        uint8_t xcc:4; // 64-bit condition codes
+                                        struct
+                                        {
+                                                uint8_t c:1;   // Carry
+                                                uint8_t v:1;   // Overflow
+                                                uint8_t z:1;   // Zero
+                                                uint8_t n:1;   // Negative
+                                        } xccFields:4;
+                                } :4;
+                        } ccrFields;
+                }
+                uint8_t asi;           // Address Space Identifier
+                uint8_t tl;            // Trap Level
+                uint64_t tpc[MaxTL];   // Trap Program Counter (value from previous trap level)
+                uint64_t tnpc[MaxTL];  // Trap Next Program Counter (value from previous trap level)
+                union
+                {
+                        uint64_t tstate[MaxTL];        // Trap State
+                        struct
+                        {
+                                //Values are from previous trap level
+                                uint64_t cwp:5;                // Current Window Pointer
+                                const uint64_t :2;     // Reserved bits
+                                uint64_t pstate:10;    // Process State
+                                const uint64_t :6;     // Reserved bits
+                                uint64_t asi:8;                // Address Space Identifier
+                                uint64_t ccr:8;                // Condition Code Register
+                        } tstateFields[MaxTL];
+                }
+                union
+                {
+                        uint64_t       tick;           // Hardware clock-tick counter
+                        struct
+                        {
+                                uint64_t counter:63;   // Clock-tick count
+                                uint64_t npt:1;                // Non-priveleged trap
+                        } tickFields;
+                }
+                uint8_t cansave;       // Savable windows
+                uint8_t canrestore;    // Restorable windows
+                uint8_t otherwin;      // Other windows
+                uint8_t cleanwin;      // Clean windows
+                union
+                {
+                        uint8_t wstate;                // Window State
+                        struct
+                        {
+                                uint8_t normal:3;      // Bits TT<4:2> are set to on a normal
+                                                        // register window trap
+                                uint8_t other:3;       // Bits TT<4:2> are set to on an "otherwin"
+                                                        // register window trap
+                        } wstateFields;
+                }
+                union
+                {
+                        uint64_t ver;          // Version
+                        struct
+                        {
+                                uint64_t maxwin:5;     // Max CWP value
+                                const uint64_t :2;     // Reserved bits
+                                uint64_t maxtl:8;      // Maximum trap level
+                                const uint64_t :8;     // Reserved bits
+                                uint64_t mask:8;       // Processor mask set revision number
+                                uint64_t impl:16;      // Implementation identification number
+                                uint64_t manuf:16;     // Manufacturer code
+                        } verFields;
+                }
+                union
+                {
+                        uint64_t       fsr;    // Floating-Point State Register
+                        struct
+                        {
+                                union
+                                {
+                                        uint64_t cexc:5;       // Current excpetion
+                                        struct
+                                        {
+                                                uint64_t nxc:1;                // Inexact
+                                                uint64_t dzc:1;                // Divide by zero
+                                                uint64_t ufc:1;                // Underflow
+                                                uint64_t ofc:1;                // Overflow
+                                                uint64_t nvc:1;                // Invalid operand
+                                        } cexecFields:5;
+                                } :5;
+                                union
+                                {
+                                        uint64_t aexc:5;               // Accrued exception
+                                        struct
+                                        {
+                                                uint64_t nxc:1;                // Inexact
+                                                uint64_t dzc:1;                // Divide by zero
+                                                uint64_t ufc:1;                // Underflow
+                                                uint64_t ofc:1;                // Overflow
+                                                uint64_t nvc:1;                // Invalid operand
+                                        } aexecFields:5;
+                                } :5;
+                                uint64_t fcc0:2;               // Floating-Point condtion codes
+                                const uint64_t :1;             // Reserved bits
+                                uint64_t qne:1;                        // Deferred trap queue not empty
+                                                                // with no queue, it should read 0
+                                uint64_t ftt:3;                        // Floating-Point trap type
+                                uint64_t ver:3;                        // Version (of the FPU)
+                                const uint64_t :2;             // Reserved bits
+                                uint64_t ns:1;                 // Nonstandard floating point
+                                union
+                                {
+                                        uint64_t tem:5;                        // Trap Enable Mask
+                                        struct
+                                        {
+                                                uint64_t nxm:1;                // Inexact
+                                                uint64_t dzm:1;                // Divide by zero
+                                                uint64_t ufm:1;                // Underflow
+                                                uint64_t ofm:1;                // Overflow
+                                                uint64_t nvm:1;                // Invalid operand
+                                        } temFields:5;
+                                } :5;
+                                const uint64_t :2;             // Reserved bits
+                                uint64_t rd:2;                 // Rounding direction
+                                uint64_t fcc1:2;               // Floating-Point condition codes
+                                uint64_t fcc2:2;               // Floating-Point condition codes
+                                uint64_t fcc3:2;               // Floating-Point condition codes
+                                const uint64_t :26;            // Reserved bits
+                        } fsrFields;
+                }
+                union
+                {
+                        uint8_t                fprs;   // Floating-Point Register State
+                        struct
+                        {
+                                dl:1;          // Dirty lower
+                                du:1;          // Dirty upper
+                                fef:1;         // FPRS enable floating-Point
+                        } fprsFields;
+                };
+
+                void serialize(std::ostream & os)
+                {
+                        SERIALIZE_SCALAR(pstate);
+                        SERIAlIZE_SCALAR(tba);
+                        SERIALIZE_SCALAR(y);
+                        SERIALIZE_SCALAR(pil);
+                        SERIALIZE_SCALAR(cwp);
+                        SERIALIZE_ARRAY(tt, MaxTL);
+                        SERIALIZE_SCALAR(ccr);
+                        SERIALIZE_SCALAR(asi);
+                        SERIALIZE_SCALAR(tl);
+                        SERIALIZE_SCALAR(tpc);
+                        SERIALIZE_SCALAR(tnpc);
+                        SERIALIZE_ARRAY(tstate, MaxTL);
+                        SERIALIZE_SCALAR(tick);
+                        SERIALIZE_SCALAR(cansave);
+                        SERIALIZE_SCALAR(canrestore);
+                        SERIALIZE_SCALAR(otherwin);
+                        SERIALIZE_SCALAR(cleanwin);
+                        SERIALIZE_SCALAR(wstate);
+                        SERIALIZE_SCALAR(ver);
+                        SERIALIZE_SCALAR(fsr);
+                        SERIALIZE_SCALAR(fprs);
+                }
+
+                void unserialize(Checkpoint &* cp, std::string & section)
+                {
+                        UNSERIALIZE_SCALAR(pstate);
+                        UNSERIAlIZE_SCALAR(tba);
+                        UNSERIALIZE_SCALAR(y);
+                        UNSERIALIZE_SCALAR(pil);
+                        UNSERIALIZE_SCALAR(cwp);
+                        UNSERIALIZE_ARRAY(tt, MaxTL);
+                        UNSERIALIZE_SCALAR(ccr);
+                        UNSERIALIZE_SCALAR(asi);
+                        UNSERIALIZE_SCALAR(tl);
+                        UNSERIALIZE_SCALAR(tpc);
+                        UNSERIALIZE_SCALAR(tnpc);
+                        UNSERIALIZE_ARRAY(tstate, MaxTL);
+                        UNSERIALIZE_SCALAR(tick);
+                        UNSERIALIZE_SCALAR(cansave);
+                        UNSERIALIZE_SCALAR(canrestore);
+                        UNSERIALIZE_SCALAR(otherwin);
+                        UNSERIALIZE_SCALAR(cleanwin);
+                        UNSERIALIZE_SCALAR(wstate);
+                        UNSERIALIZE_SCALAR(ver);
+                        UNSERIALIZE_SCALAR(fsr);
+                        UNSERIALIZE_SCALAR(fprs);
+                }
+        };
+
+        typedef union
+        {
+                IntReg  intreg;
+                FloatReg   fpreg;
+                MiscReg ctrlreg;
+        } AnyReg;
+
+        struct RegFile
+        {
+                IntRegFile intRegFile;         // (signed) integer register file
+                FloatRegFile floatRegFile;     // floating point register file
+                MiscRegFile miscRegFile;       // control register file
+
+                Addr pc;               // Program Counter
+                Addr npc;              // Next Program Counter
+
+                void serialize(std::ostream &os);
+                void unserialize(Checkpoint *cp, const std::string &section);
+        };
+
+        static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+
+        // return a no-op instruction... used for instruction fetch faults
+        static const MachInst NoopMachInst;
+
+        // Instruction address compression hooks
+        static inline Addr realPCToFetchPC(const Addr &addr)
+        {
+                return addr;
+        }
+
+        static inline Addr fetchPCToRealPC(const Addr &addr)
+        {
+                return addr;
+        }
+
+        // the size of "fetched" instructions (not necessarily the size
+        // of real instructions for PISA)
+        static inline size_t fetchInstSize()
+        {
+                return sizeof(MachInst);
+        }
+
+        /**
+         * Function to insure ISA semantics about 0 registers.
+         * @param xc The execution context.
+         */
+        template <class XC>
+        static void zeroRegisters(XC *xc);
+};
+
+
+typedef SPARCISA TheISA;
+
+typedef TheISA::MachInst MachInst;
+typedef TheISA::Addr Addr;
+typedef TheISA::RegIndex RegIndex;
+typedef TheISA::IntReg IntReg;
+typedef TheISA::IntRegFile IntRegFile;
+typedef TheISA::FloatReg FloatReg;
+typedef TheISA::FloatRegFile FloatRegFile;
+typedef TheISA::MiscReg MiscReg;
+typedef TheISA::MiscRegFile MiscRegFile;
+typedef TheISA::AnyReg AnyReg;
+typedef TheISA::RegFile RegFile;
+
+const int VMPageSize   = TheISA::VMPageSize;
+const int LogVMPageSize   = TheISA::LogVMPageSize;
+const int ZeroReg = TheISA::ZeroReg;
+const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
+
+#ifndef FULL_SYSTEM
+class SyscallReturn {
+        public:
+           template <class T>
+           SyscallReturn(T v, bool s)
+           {
+               retval = (uint64_t)v;
+               success = s;
+           }
+
+           template <class T>
+           SyscallReturn(T v)
+           {
+               success = (v >= 0);
+               retval = (uint64_t)v;
+           }
+
+           ~SyscallReturn() {}
+
+           SyscallReturn& operator=(const SyscallReturn& s) {
+               retval = s.retval;
+               success = s.success;
+               return *this;
+           }
+
+           bool successful() { return success; }
+           uint64_t value() { return retval; }
+
+
+       private:
+           uint64_t retval;
+           bool success;
+};
+
+#endif
+
+
+#ifdef FULL_SYSTEM
+
+#include "arch/alpha/ev5.hh"
+#endif
+
+#endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff --git a/arch/sparc/isa_desc/bitfields.h b/arch/sparc/isa_desc/bitfields.h
deleted file mode 100644 (file)
index b0ac575..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Bitfield definitions.
-//
-
-// Bitfields are shared liberally between instruction formats, so they are
-// simply defined alphabetically
-
-def bitfield A         <29>;
-def bitfield CC02      <20>;
-def bitfield CC03      <25>;
-def bitfield CC04      <11>;
-def bitfield CC12      <21>;
-def bitfield CC13      <26>;
-def bitfield CC14      <12>;
-def bitfield CC2       <18>;
-def bitfield CMASK     <6:4>;
-def bitfield COND2     <28:25>;
-def bitfield COND4     <17:14>;
-def bitfield D16HI     <21:20>;
-def bitfield D16LO     <13:0>;
-def bitfield DISP19    <18:0>;
-def bitfield DISP22    <21:0>;
-def bitfield DISP30    <29:0>;
-def bitfield FCN       <29:26>;
-def bitfield I         <13>;
-def bitfield IMM_ASI   <12:5>;
-def bitfield IMM22     <21:0>;
-def bitfield MMASK     <3:0>;
-def bitfield OP                <31:30>;
-def bitfield OP2       <24:22>;
-def bitfield OP3       <24:19>;
-def bitfield OPF       <13:5>;
-def bitfield OPF_CC    <13:11>;
-def bitfield OPF_LOW5  <9:5>;
-def bitfield OPF_LOW6  <10:5>;
-def bitfield P         <19>;
-def bitfield RCOND2    <27:25>;
-def bitfield RCOND3    <12:10>;
-def bitfield RCOND4    <12:10>;
-def bitfield RD                <29:25>;
-def bitfield RS1       <18:14>;
-def bitfield RS2       <4:0>;
-def bitfield SHCNT32   <4:0>;
-def bitfield SHCNT64   <5:0>;
-def bitfield SIMM10    <9:0>;
-def bitfield SIMM11    <10:0>;
-def bitfield SIMM13    <12:0>;
-def bitfield SW_TRAP   <6:0>;
-def bitfield X         <12>;
diff --git a/arch/sparc/isa_desc/decoder.h b/arch/sparc/isa_desc/decoder.h
deleted file mode 100644 (file)
index 06834ec..0000000
+++ /dev/null
@@ -1,638 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// The actual decoder specification
-//
-
-decode OP default Trap::unknown({{illegal_instruction}}) {
-
-        0x0: decode OP2 {
-                0x0: Trap::illtrap({{illegal_instruction}});  //ILLTRAP
-                0x1: Branch::bpcc({{
-                        switch((CC12 << 1) | CC02)
-                        {
-                                case 1: case 3:
-                                        throw illegal_instruction;
-                                case 0:
-                                        if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
-                                                ;//branchHere
-                                break;
-                                case 2:
-                                        if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
-                                                ;//branchHere
-                                break;
-                        }
-                }});//BPcc
-                0x2: Branch::bicc({{
-                        if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
-                                ;//branchHere
-                }});//Bicc
-                0x3: Branch::bpr({{
-                        switch(RCOND)
-                        {
-                                case 0: case 4:
-                                        throw illegal_instruction;
-                                case 1:
-                                        if(Rs1 == 0) ;//branchHere
-                                break;
-                                case 2:
-                                        if(Rs1 <= 0) ;//branchHere
-                                break;
-                                case 3:
-                                        if(Rs1 < 0) ;//branchHere
-                                break;
-                                case 5:
-                                        if(Rs1 != 0) ;//branchHere
-                                break;
-                                case 6:
-                                        if(Rs1 > 0) ;//branchHere
-                                break;
-                                case 7:
-                                        if(Rs1 >= 0) ;//branchHere
-                                break;
-                        }
-                }});    //BPr
-                0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});   //SETHI (or NOP if rd == 0 and imm == 0)
-                0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
-                0x6: Trap::fbfcc({{throw fp_disabled;}});  //FBfcc
-        }
-        0x1: Branch::call({{
-                //branch here
-                Rd = xc->pc;
-        }});
-        0x2: decode OP3 {
-                format IntegerOp {
-                        0x00: add({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                Rd = Rs1.sdw + val2;
-                        }});//ADD
-                        0x01: and({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = Rs1.udw & val2;
-                        }});//AND
-                        0x02: or({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = Rs1.udw | val2;
-                        }});//OR
-                        0x03: xor({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = Rs1.udw ^ val2;
-                        }});//XOR
-                        0x04: sub({{
-                                INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1;
-                                Rd = Rs1.sdw + val2;
-                        }});//SUB
-                        0x05: andn({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = Rs1.udw & ~val2;
-                        }});//ANDN
-                        0x06: orn({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = Rs1.udw | ~val2;
-                        }});//ORN
-                        0x07: xnor({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = ~(Rs1.udw ^ val2);
-                        }});//XNOR
-                        0x08: addc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd = Rs1.sdw + val2 + carryin;
-                        }});//ADDC
-                        0x09: mulx({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 * val2;
-                        }});//MULX
-                        0x0A: umul({{
-                                UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                        }});//UMUL
-                        0x0B: smul({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                        }});//SMUL
-                        0x0C: subc({{
-                                INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1;
-                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd.sdw = Rs1.sdw + val2 + carryin;
-                        }});//SUBC
-                        0x0D: udivx({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.udw = Rs1.udw / val2;
-                        }});//UDIVX
-                        0x0E: udiv({{
-                                UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
-                                INT32 overflow = (resTemp<63:32> != 0);
-                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
-                                else rd.udw = resTemp;
-                        }});   //UDIV
-                        0x0F: sdiv({{
-                                INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
-                                INT32 overflow = (resTemp<63:31> != 0);
-                                INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
-                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
-                                else rd.udw = resTemp;
-                        }});//SDIV
-                }
-                format IntegerOpCc {
-                        0x10: addcc({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//ADDcc
-                        0x11: andcc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 & val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//ANDcc
-                        0x12: orcc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 | val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//ORcc
-                        0x13: xorcc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 ^ val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//XORcc
-                        0x14: subcc({{
-                                INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 - val2;}},
-                                {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
-                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}},
-                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                        );//SUBcc
-                        0x15: andncc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 & ~val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//ANDNcc
-                        0x16: orncc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = Rs1 | ~val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//ORNcc
-                        0x17: xnorcc({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = ~(Rs1 ^ val2);}}
-                        ,{{0}},{{0}},{{0}},{{0}});//XNORcc
-                        0x18: addccc({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd = resTemp = Rs1 + val2 + carryin;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}},
-                                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//ADDCcc
-                        0x1A: umulcc({{
-                                UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//UMULcc
-                        0x1B: smulcc({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//SMULcc
-                        0x1C: subccc({{
-                                INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
-                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
-                                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
-                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
-                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                        );//SUBCcc
-                        0x1D: udivxcc({{
-                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.udw = Rs1.udw / val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
-                        0x1E: udivcc({{
-                                UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
-                                INT32 overflow = (resTemp<63:32> != 0);
-                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow}},
-                                {{0}},
-                                {{0}}
-                        );//UDIVcc
-                        0x1F: sdivcc({{
-                                INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
-                                INT32 overflow = (resTemp<63:31> != 0);
-                                INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
-                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow || underflow}},
-                                {{0}},
-                                {{0}}
-                        );//SDIVcc
-                        0x20: taddcc({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDcc
-                        0x21: tsubcc({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBcc
-                        0x22: taddcctv({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDccTV
-                        0x23: tsubcctv({{
-                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBccTV
-                        0x24: mulscc({{
-                                INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
-                                INT32 multiplier = Rs1<31:0>;
-                                INT32 savedLSB = Rs1<0:>;
-                                multiplier = multipler<31:1> |
-                                        ((xc->regs.MiscRegs.ccrFields.iccFields.n
-                                        ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
-                                if(!xc->regs.MiscRegs.yFields.value<0:>)
-                                        multiplicand = 0;
-                                Rd = resTemp = multiplicand + multiplier;
-                                xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
-                                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
-                                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
-                                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
-                                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
-                        );//MULScc
-                }
-                format IntegerOp
-                {
-                        0x25: decode X {
-                                0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
-                                0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
-                        }
-                        0x26: decode X {
-                                0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
-                                0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
-                        }
-                        0x27: decode X {
-                                0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
-                                0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
-                        }
-                        0x28: decode RS1 {
-                                0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
-                                0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
-                                0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
-                                0x4: rdtick({{
-                                        if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
-                                                xc->regs.MiscRegs.tickFields.npt == 1)
-                                                throw privileged_action;
-                                        Rd = xc->regs.MiscRegs.tick;
-                                }});//RDTICK
-                                0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
-                                0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
-                                0xF: decode I {
-                                        0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
-                                        0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
-                                }
-                        }
-
-                        0x2A: decode RS1 {
-                                0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
-                                0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
-                                0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
-                                0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
-                                0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
-                                0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
-                                0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
-                                0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
-                                0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
-                                0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
-                                0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
-                                0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
-                                0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
-                                0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
-                                0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
-                                0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
-                        }
-                        0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
-                        0x2C: movcc({{
-                                ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
-                                switch(ccBank)
-                                {
-                                        case 0: case 1: case 2: case 3:
-                                                throw fp_disabled;
-                                        break;
-                                        case 5: case 7:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 4:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                        case 6:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                }
-                        }});//MOVcc
-                        0x2D: sdivx({{
-                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = Rs1.sdw / val2;
-                        }});//SDIVX
-                        0x2E: decode RS1 {
-                                0x0: IntegerOp::popc({{
-                                INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
-                                for(unsigned int x = 0; x < 16; x++)
-                                {
-                                        count += oneBits[val2 & 0xF];
-                                        val2 >> 4;
-                                }
-                                }});//POPC
-                        }
-                        0x2F: movr({{
-                                UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw);
-                                switch(RCOND)
-                                {
-                                        case 0: case 4:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 1:
-                                                if(Rs1 == 0) Rd = val2;
-                                        break;
-                                        case 2:
-                                                if(Rs1 <= 0) Rd = val2;
-                                        break;
-                                        case 3:
-                                                if(Rs1 = 0) Rd = val2;
-                                        break;
-                                        case 5:
-                                                if(Rs1 != 0) Rd = val2;
-                                        break;
-                                        case 6:
-                                                if(Rs1 > 0) Rd = val2;
-                                        break;
-                                        case 7:
-                                                if(Rs1 >= 0) Rd = val2;
-                                        break;
-                                }
-                        }});//MOVR
-                        0x30: decode RD {
-                                0x0: wry({{
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.y = Rs1 ^ val2;
-                                }});//WRY
-                                0x2: wrccr({{
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.ccr = Rs1 ^ val2;
-                                }});//WRCCR
-                                0x3: wrasi({{
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRASI
-                                0x6: wrfprs({{
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRFPRS
-                                0xF: Trap::sir({{software_initiated_reset}}); //SIR
-                        }
-                        0x31: decode FCN {
-                                0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
-                                0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
-                        }
-                        0x32: decode RD {
-                                0x0: wrprtpc({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x1: wrprtnpc({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x2: wrprtstate({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x3: wrprtt({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x4: wrprtick({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tick = Rs1 ^ val2;
-                                }});
-                                0x5: wrprtba({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tba = Rs1 ^ val2;
-                                }});
-                                0x6: wrprpstate({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pstate = Rs1 ^ val2;
-                                }});
-                                0x7: wrprtl({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tl = Rs1 ^ val2;
-                                }});
-                                0x8: wrprpil({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pil = Rs1 ^ val2;
-                                }});
-                                0x9: wrprcwp({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cwp = Rs1 ^ val2;
-                                }});
-                                0xA: wrprcansave({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cansave = Rs1 ^ val2;
-                                }});
-                                0xB: wrprcanrestore({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
-                                }});
-                                0xC: wrprcleanwin({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
-                                }});
-                                0xD: wrprotherwin({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
-                                }});
-                                0xE: wrprwstate({{checkPriv
-                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.wstate = Rs1 ^ val2;
-                                }});
-                        }
-
-                        0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
-                        0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
-
-
-                        0x38: Branch::jmpl({{//Stuff}}); //JMPL
-                        0x39: Branch::return({{//Other Stuff}}); //RETURN
-                        0x3A: Trap::tcc({{
-                                switch((CC14 << 1) | (CC04 << 0))
-                                {
-                                        case 1: case 3:
-                                                throw illegal_instruction;
-                                        case 0:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
-                                                        throw trap_instruction;
-                                        break;
-                                        case 2:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
-                                                        throw trap_instruction;
-                                        break;
-                                }
-                        }}); //Tcc
-                        0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
-                        0x3C: BasicOperate::save({{//leprechauns); //SAVE
-                        0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
-                        0x3E: decode FCN {
-                                0x1: BasicOperate::done({{//Done thing}}); //DONE
-                                0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
-                        }
-                }
-        }
-        0x3: decode OP3 {
-                format Mem {
-                        0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
-                        0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
-                        0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
-                        0x03: ldd({{
-                                UINT64 val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }});//LDD
-                        0x04: stw({{Mem.sw = Rd.sw;}}); //STW
-                        0x05: stb({{Mem.sb = Rd.sb;}}); //STB
-                        0x06: sth({{Mem.shw = Rd.shw;}}); //STH
-                        0x07: std({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }});//STD
-                        0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
-                        0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
-                        0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
-                        0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
-
-                        0x0D: ldstub({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUB
-                        0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
-                        0x0F: swap({{
-                                UINT32 temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAP
-                        0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
-                        0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
-                        0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
-                        0x13: ldda({{
-                                UINT64 val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }}); //LDDA
-                        0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
-                        0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
-                        0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
-                        0x17: stda({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }}); //STDA
-                        0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
-                        0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
-                        0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
-                        0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
-
-                        0x1D: ldstuba({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUBA
-                        0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
-                        0x1F: swapa({{
-                                UINT32 temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAPA
-                        0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
-                        0x21: decode X {
-                                0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
-                                0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
-                        }
-                        0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
-                        0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
-                        0x24: Trap::stf({{throw fp_disabled;}}); //STF
-                        0x25: decode X {
-                                0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
-                                0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
-                        }
-                        0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
-                        0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
-
-
-
-
-
-                        0x2D: Noop::prefetch({{ }}); //PREFETCH
-
-
-                        0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
-
-                        0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
-                        0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
-                        0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
-                        0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
-                        0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
-
-
-
-
-
-                        0x3C: Cas::casa(
-                                {{UINT64 val = Mem.uw;
-                                if(Rs2.uw == val)
-                                        Mem.uw = Rd.uw;
-                                Rd.uw = val;
-                        }}); //CASA
-                        0x3D: Noop::prefetcha({{ }}); //PREFETCHA
-                        0x3E: Cas::casxa(
-                                {{UINT64 val = Mem.udw;
-                                if(Rs2 == val)
-                                        Mem.udw = Rd;
-                                Rd = val;
-                        }}); //CASXA
-                }
-        }
-}
diff --git a/arch/sparc/isa_desc/formats.h b/arch/sparc/isa_desc/formats.h
deleted file mode 100644 (file)
index 733a093..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-//Include the basic format
-//Templates from this format are used later
-##include "m5/arch/sparc/isa_desc/formats/basic.format"
-
-//Include the integerOp and integerOpCc format
-##include "m5/arch/sparc/isa_desc/formats/integerop.format"
-
-//Include the mem format
-##include "m5/arch/sparc/isa_desc/formats/mem.format"
-
-//Include the trap format
-##include "m5/arch/sparc/isa_desc/formats/trap.format"
-
-//Include the branch format
-##include "m5/arch/sparc/isa_desc/formats/branch.format"
-
-//Include the noop format
-##include "m5/arch/sparc/isa_desc/formats/noop.format"
-
diff --git a/arch/sparc/isa_desc/formats/basic.format b/arch/sparc/isa_desc/formats/basic.format
deleted file mode 100644 (file)
index 1994df4..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-
-// Declarations for execute() methods.
-def template BasicExecDeclare {{
-        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
-}};
-
-// Basic instruction class declaration template.
-def template BasicDeclare {{
-        /**
-         * Static instruction class for "%(mnemonic)s".
-         */
-        class %(class_name)s : public %(base_class)s
-        {
-        public:
-                /// Constructor.
-                %(class_name)s(MachInst machInst);
-                %(BasicExecDeclare)s
-    };
-}};
-
-// Basic instruction class constructor template.
-def template BasicConstructor {{
-        inline %(class_name)s::%(class_name)s(MachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-        {
-                %(constructor)s;
-        }
-}};
-
-// Basic instruction class execute method template.
-def template BasicExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                Fault fault = No_Fault;
-
-                %(fp_enable_check)s;
-                %(op_decl)s;
-                %(op_rd)s;
-                %(code)s;
-
-                if(fault == No_Fault)
-                {
-                        %(op_wb)s;
-                }
-                return fault;
-        }
-}};
-
-// Basic decode template.
-def template BasicDecode {{
-        return new %(class_name)s(machInst);
-}};
-
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
-        return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
-// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
-        iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa_desc/formats/branch.format b/arch/sparc/isa_desc/formats/branch.format
deleted file mode 100644 (file)
index c4c0a90..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Branch instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Branch : public SparcStaticInst
-        {
-                protected:
-
-                /// Constructor
-                Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template BranchExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Branch(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa_desc/formats/integerop.format b/arch/sparc/isa_desc/formats/integerop.format
deleted file mode 100644 (file)
index 275a346..0000000
+++ /dev/null
@@ -1,110 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Integer operate instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class IntegerOp : public SparcStaticInst
-        {
-                protected:
-
-                /// Constructor
-                IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template IntegerExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
-
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-                if(useCc)
-                {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
-                }
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format IntegerOp(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
-}};
-
-// Primary format for integer operate instructions:
-def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
-                       ('xvValue', xvValue), ('xcValue', xcValue)):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa_desc/formats/mem.format b/arch/sparc/isa_desc/formats/mem.format
deleted file mode 100644 (file)
index abc00b6..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Mem instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Mem : public SparcStaticInst
-        {
-                protected:
-
-                /// Constructor
-                Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template MemExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //Attempt to execute the instruction
-                try
-                {
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        ea_code
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Mem(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
-}};
-
-def format Cas(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = R1;');
-}};
diff --git a/arch/sparc/isa_desc/formats/noop.format b/arch/sparc/isa_desc/formats/noop.format
deleted file mode 100644 (file)
index bc83e32..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Noop instruction
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Noop : public SparcStaticInst
-        {
-                protected:
-
-                /// Constructor
-                Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template NoopExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //Nothing to see here, move along
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = NoopExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa_desc/formats/trap.format b/arch/sparc/isa_desc/formats/trap.format
deleted file mode 100644 (file)
index bee77fe..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Trap instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Trap : public SparcStaticInst
-        {
-                protected:
-
-                /// Constructor
-                Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template TrapExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //Call into the trap handler with the appropriate fault
-                return No_Fault;
-        }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Trap(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = TrapExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa_desc/includes.h b/arch/sparc/isa_desc/includes.h
deleted file mode 100644 (file)
index ff7cb7d..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Output include file directives.
-//
-
-output header {{
-#include <sstream>
-#include <iostream>
-#include <iomanip>
-
-#include "cpu/static_inst.hh"
-#include "traps.hh"
-#include "mem/mem_req.hh"  // some constructors use MemReq flags
-}};
-
-output decoder {{
-#include "base/cprintf.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
-
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-}};
-
-output exec {{
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-
-#ifdef FULL_SYSTEM
-//#include "arch/alpha/pseudo_inst.hh"
-#endif
-#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
-#include "sim/sim_exit.hh"
-}};
-
diff --git a/arch/sparc/isa_desc/operands.h b/arch/sparc/isa_desc/operands.h
deleted file mode 100644 (file)
index 77de6c9..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-def operand_types {{
-    'sb' : ('signed int', 8),
-    'ub' : ('unsigned int', 8),
-    'shw' : ('signed int', 16),
-    'uhw' : ('unsigned int', 16),
-    'sw' : ('signed int', 32),
-    'uw' : ('unsigned int', 32),
-    'sdw' : ('signed int', 64),
-    'udw' : ('unsigned int', 64),
-    'sf' : ('float', 32),
-    'df' : ('float', 64),
-    'qf' : ('float', 128)
-}};
-
-def operands {{
-    # Int regs default to unsigned, but code should not count on this.
-    # For clarity, descriptions that depend on unsigned behavior should
-    # explicitly specify '.uq'.
-    'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
-    'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
-    'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
-    #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
-    #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
-    #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
-    'Mem': MemOperandTraits('udw', None,
-                            ('IsMemRef', 'IsLoad', 'IsStore'), 4)
-    #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
-    #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
-    #'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
-    # The next two are hacks for non-full-system call-pal emulation
-    #'R0':  IntRegOperandTraits('uq', '0', None, 1),
-    #'R16': IntRegOperandTraits('uq', '16', None, 1)
-}};
diff --git a/arch/sparc/isa_traits.cc b/arch/sparc/isa_traits.cc
deleted file mode 100644 (file)
index c7a25f8..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/isa_traits.hh"
-#include "cpu/static_inst.hh"
-#include "sim/serialize.hh"
-
-// Alpha UNOP (ldq_u r31,0(r0))
-const MachInst SPARCISA::NoopMachInst = 0x2ffe0000;
-
-void
-SPARCISA::RegFile::serialize(std::ostream &os)
-{
-    intRegFile.serialize(os);
-    floatRegFile.serialize(os);
-    miscRegs.serialize(os);
-    SERIALIZE_SCALAR(pc);
-    SERIALIZE_SCALAR(npc);
-}
-
-
-void
-AlphaISA::RegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
-    intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
-    miscRegs.unserialize(cp, section);
-    UNSERIALIZE_SCALAR(pc);
-    UNSERIALIZE_SCALAR(npc);
-}
-
-#endif //FULL_SYSTEM
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
deleted file mode 100644 (file)
index 9513b99..0000000
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
-#define __ARCH_SPARC_ISA_TRAITS_HH__
-
-#include "arch/sparc/faults.hh"
-#include "base/misc.hh"
-#include "sim/host.hh"
-
-class FastCPU;
-//class FullCPU;
-//class Checkpoint;
-
-#define TARGET_SPARC
-
-template <class ISA> class StaticInst;
-template <class ISA> class StaticInstPtr;
-
-//namespace EV5
-//{
-//     int DTB_ASN_ASN(uint64_t reg);
-//     int ITB_ASN_ASN(uint64_t reg);
-//}
-
-class SPARCISA
-{
-        public:
-
-        typedef uint32_t MachInst;
-        typedef uint64_t Addr;
-        typedef uint8_t  RegIndex;
-
-        enum
-        {
-                MemoryEnd = 0xffffffffffffffffULL,
-
-                NumFloatRegs = 32,
-                NumMiscRegs = 32,
-
-                MaxRegsOfAnyType = 32,
-                // Static instruction parameters
-                MaxInstSrcRegs = 3,
-                MaxInstDestRegs = 2,
-
-                // Maximum trap level
-                MaxTL = 4
-
-                // semantically meaningful register indices
-                ZeroReg = 0,   // architecturally meaningful
-                // the rest of these depend on the ABI
-        }
-        typedef uint64_t IntReg;
-
-        class IntRegFile
-        {
-        private:
-                //For right now, let's pretend the register file is static
-                IntReg regs[32];
-        public:
-                IntReg & operator [] (RegIndex index)
-                {
-                        //Don't allow indexes outside of the 32 registers
-                        index &= 0x1F
-                        return regs[index];
-                }
-        };
-
-        void inline serialize(std::ostream & os)
-        {
-                SERIALIZE_ARRAY(regs, 32);
-        }
-
-        void inline unserialize(Checkpoint &*cp, const std::string &section)
-        {
-                UNSERIALIZE_ARRAY(regs, 32);
-        }
-
-        class FloatRegFile
-        {
-        private:
-                //By using the largest data type, we ensure everything
-                //is aligned correctly in memory
-                union
-                {
-                        double double rawRegs[16];
-                        uint64_t regDump[32];
-                };
-                class QuadRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                        public:
-                                QuadRegs(FloatRegFile * p) : parent(p) {;}
-                                double double & operator [] (RegIndex index)
-                                {
-                                        //Quad floats are index by the single
-                                        //precision register the start on,
-                                        //and only 16 should be accessed
-                                        index = (index >> 2) & 0xF;
-                                        return parent->rawRegs[index];
-                                }
-                };
-                class DoubleRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                        public:
-                                DoubleRegs(FloatRegFile * p) : parent(p) {;}
-                                double & operator [] (RegIndex index)
-                                {
-                                        //Double floats are index by the single
-                                        //precision register the start on,
-                                        //and only 32 should be accessed
-                                        index = (index >> 1) & 0x1F
-                                        return ((double [])parent->rawRegs)[index];
-                                }
-                }
-                class SingleRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                                public:
-                                SingleRegs(FloatRegFile * p) : parent(p) {;}
-                                double & operator [] (RegFile index)
-                                {
-                                        //Only 32 single floats should be accessed
-                                        index &= 0x1F
-                                        return ((float [])parent->rawRegs)[index];
-                                }
-                }
-        public:
-                void inline serialize(std::ostream & os)
-                {
-                        SERIALIZE_ARRAY(regDump, 32);
-                }
-
-                void inline unserialize(Checkpoint &* cp, std::string & section)
-                {
-                        UNSERIALIZE_ARRAY(regDump, 32);
-                }
-
-                QuadRegs quadRegs;
-                DoubleRegs doubleRegs;
-                SingleRegs singleRegs;
-                FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
-                {;}
-        };
-
-        // control register file contents
-        typedef uint64_t MiscReg;
-        // The control registers, broken out into fields
-        class MiscRegFile
-        {
-        public:
-                union
-                {
-                        uint16_t pstate;               // Process State Register
-                        struct
-                        {
-                                uint16_t ag:1;         // Alternate Globals
-                                uint16_t ie:1;         // Interrupt enable
-                                uint16_t priv:1;       // Privelege mode
-                                uint16_t am:1;         // Address mask
-                                uint16_t pef:1;                // PSTATE enable floating-point
-                                uint16_t red:1;                // RED (reset, error, debug) state
-                                uint16_t mm:2;         // Memory Model
-                                uint16_t tle:1;                // Trap little-endian
-                                uint16_t cle:1;                // Current little-endian
-                        } pstateFields;
-                }
-                uint64_t tba;          // Trap Base Address
-                union
-                {
-                        uint64_t y;            // Y (used in obsolete multiplication)
-                        struct
-                        {
-                                uint64_t value:32;     // The actual value stored in y
-                                const uint64_t :32;    // reserved bits
-                        } yFields;
-                }
-                uint8_t pil;           // Process Interrupt Register
-                uint8_t cwp;           // Current Window Pointer
-                uint16_t tt[MaxTL];    // Trap Type (Type of trap which occured on the previous level)
-                union
-                {
-                        uint8_t        ccr;            // Condition Code Register
-                        struct
-                        {
-                                union
-                                {
-                                        uint8_t icc:4; // 32-bit condition codes
-                                        struct
-                                        {
-                                                uint8_t c:1;   // Carry
-                                                uint8_t v:1;   // Overflow
-                                                uint8_t z:1;   // Zero
-                                                uint8_t n:1;   // Negative
-                                        } iccFields:4;
-                                } :4;
-                                union
-                                {
-                                        uint8_t xcc:4; // 64-bit condition codes
-                                        struct
-                                        {
-                                                uint8_t c:1;   // Carry
-                                                uint8_t v:1;   // Overflow
-                                                uint8_t z:1;   // Zero
-                                                uint8_t n:1;   // Negative
-                                        } xccFields:4;
-                                } :4;
-                        } ccrFields;
-                }
-                uint8_t asi;           // Address Space Identifier
-                uint8_t tl;            // Trap Level
-                uint64_t tpc[MaxTL];   // Trap Program Counter (value from previous trap level)
-                uint64_t tnpc[MaxTL];  // Trap Next Program Counter (value from previous trap level)
-                union
-                {
-                        uint64_t tstate[MaxTL];        // Trap State
-                        struct
-                        {
-                                //Values are from previous trap level
-                                uint64_t cwp:5;                // Current Window Pointer
-                                const uint64_t :2;     // Reserved bits
-                                uint64_t pstate:10;    // Process State
-                                const uint64_t :6;     // Reserved bits
-                                uint64_t asi:8;                // Address Space Identifier
-                                uint64_t ccr:8;                // Condition Code Register
-                        } tstateFields[MaxTL];
-                }
-                union
-                {
-                        uint64_t       tick;           // Hardware clock-tick counter
-                        struct
-                        {
-                                uint64_t counter:63;   // Clock-tick count
-                                uint64_t npt:1;                // Non-priveleged trap
-                        } tickFields;
-                }
-                uint8_t cansave;       // Savable windows
-                uint8_t canrestore;    // Restorable windows
-                uint8_t otherwin;      // Other windows
-                uint8_t cleanwin;      // Clean windows
-                union
-                {
-                        uint8_t wstate;                // Window State
-                        struct
-                        {
-                                uint8_t normal:3;      // Bits TT<4:2> are set to on a normal
-                                                        // register window trap
-                                uint8_t other:3;       // Bits TT<4:2> are set to on an "otherwin"
-                                                        // register window trap
-                        } wstateFields;
-                }
-                union
-                {
-                        uint64_t ver;          // Version
-                        struct
-                        {
-                                uint64_t maxwin:5;     // Max CWP value
-                                const uint64_t :2;     // Reserved bits
-                                uint64_t maxtl:8;      // Maximum trap level
-                                const uint64_t :8;     // Reserved bits
-                                uint64_t mask:8;       // Processor mask set revision number
-                                uint64_t impl:16;      // Implementation identification number
-                                uint64_t manuf:16;     // Manufacturer code
-                        } verFields;
-                }
-                union
-                {
-                        uint64_t       fsr;    // Floating-Point State Register
-                        struct
-                        {
-                                union
-                                {
-                                        uint64_t cexc:5;       // Current excpetion
-                                        struct
-                                        {
-                                                uint64_t nxc:1;                // Inexact
-                                                uint64_t dzc:1;                // Divide by zero
-                                                uint64_t ufc:1;                // Underflow
-                                                uint64_t ofc:1;                // Overflow
-                                                uint64_t nvc:1;                // Invalid operand
-                                        } cexecFields:5;
-                                } :5;
-                                union
-                                {
-                                        uint64_t aexc:5;               // Accrued exception
-                                        struct
-                                        {
-                                                uint64_t nxc:1;                // Inexact
-                                                uint64_t dzc:1;                // Divide by zero
-                                                uint64_t ufc:1;                // Underflow
-                                                uint64_t ofc:1;                // Overflow
-                                                uint64_t nvc:1;                // Invalid operand
-                                        } aexecFields:5;
-                                } :5;
-                                uint64_t fcc0:2;               // Floating-Point condtion codes
-                                const uint64_t :1;             // Reserved bits
-                                uint64_t qne:1;                        // Deferred trap queue not empty
-                                                                // with no queue, it should read 0
-                                uint64_t ftt:3;                        // Floating-Point trap type
-                                uint64_t ver:3;                        // Version (of the FPU)
-                                const uint64_t :2;             // Reserved bits
-                                uint64_t ns:1;                 // Nonstandard floating point
-                                union
-                                {
-                                        uint64_t tem:5;                        // Trap Enable Mask
-                                        struct
-                                        {
-                                                uint64_t nxm:1;                // Inexact
-                                                uint64_t dzm:1;                // Divide by zero
-                                                uint64_t ufm:1;                // Underflow
-                                                uint64_t ofm:1;                // Overflow
-                                                uint64_t nvm:1;                // Invalid operand
-                                        } temFields:5;
-                                } :5;
-                                const uint64_t :2;             // Reserved bits
-                                uint64_t rd:2;                 // Rounding direction
-                                uint64_t fcc1:2;               // Floating-Point condition codes
-                                uint64_t fcc2:2;               // Floating-Point condition codes
-                                uint64_t fcc3:2;               // Floating-Point condition codes
-                                const uint64_t :26;            // Reserved bits
-                        } fsrFields;
-                }
-                union
-                {
-                        uint8_t                fprs;   // Floating-Point Register State
-                        struct
-                        {
-                                dl:1;          // Dirty lower
-                                du:1;          // Dirty upper
-                                fef:1;         // FPRS enable floating-Point
-                        } fprsFields;
-                };
-
-                void serialize(std::ostream & os)
-                {
-                        SERIALIZE_SCALAR(pstate);
-                        SERIAlIZE_SCALAR(tba);
-                        SERIALIZE_SCALAR(y);
-                        SERIALIZE_SCALAR(pil);
-                        SERIALIZE_SCALAR(cwp);
-                        SERIALIZE_ARRAY(tt, MaxTL);
-                        SERIALIZE_SCALAR(ccr);
-                        SERIALIZE_SCALAR(asi);
-                        SERIALIZE_SCALAR(tl);
-                        SERIALIZE_SCALAR(tpc);
-                        SERIALIZE_SCALAR(tnpc);
-                        SERIALIZE_ARRAY(tstate, MaxTL);
-                        SERIALIZE_SCALAR(tick);
-                        SERIALIZE_SCALAR(cansave);
-                        SERIALIZE_SCALAR(canrestore);
-                        SERIALIZE_SCALAR(otherwin);
-                        SERIALIZE_SCALAR(cleanwin);
-                        SERIALIZE_SCALAR(wstate);
-                        SERIALIZE_SCALAR(ver);
-                        SERIALIZE_SCALAR(fsr);
-                        SERIALIZE_SCALAR(fprs);
-                }
-
-                void unserialize(Checkpoint &* cp, std::string & section)
-                {
-                        UNSERIALIZE_SCALAR(pstate);
-                        UNSERIAlIZE_SCALAR(tba);
-                        UNSERIALIZE_SCALAR(y);
-                        UNSERIALIZE_SCALAR(pil);
-                        UNSERIALIZE_SCALAR(cwp);
-                        UNSERIALIZE_ARRAY(tt, MaxTL);
-                        UNSERIALIZE_SCALAR(ccr);
-                        UNSERIALIZE_SCALAR(asi);
-                        UNSERIALIZE_SCALAR(tl);
-                        UNSERIALIZE_SCALAR(tpc);
-                        UNSERIALIZE_SCALAR(tnpc);
-                        UNSERIALIZE_ARRAY(tstate, MaxTL);
-                        UNSERIALIZE_SCALAR(tick);
-                        UNSERIALIZE_SCALAR(cansave);
-                        UNSERIALIZE_SCALAR(canrestore);
-                        UNSERIALIZE_SCALAR(otherwin);
-                        UNSERIALIZE_SCALAR(cleanwin);
-                        UNSERIALIZE_SCALAR(wstate);
-                        UNSERIALIZE_SCALAR(ver);
-                        UNSERIALIZE_SCALAR(fsr);
-                        UNSERIALIZE_SCALAR(fprs);
-                }
-        };
-
-        typedef union
-        {
-                IntReg  intreg;
-                FloatReg   fpreg;
-                MiscReg ctrlreg;
-        } AnyReg;
-
-        struct RegFile
-        {
-                IntRegFile intRegFile;         // (signed) integer register file
-                FloatRegFile floatRegFile;     // floating point register file
-                MiscRegFile miscRegFile;       // control register file
-
-                Addr pc;               // Program Counter
-                Addr npc;              // Next Program Counter
-
-                void serialize(std::ostream &os);
-                void unserialize(Checkpoint *cp, const std::string &section);
-        };
-
-        static StaticInstPtr<AlphaISA> decodeInst(MachInst);
-
-        // return a no-op instruction... used for instruction fetch faults
-        static const MachInst NoopMachInst;
-
-        // Instruction address compression hooks
-        static inline Addr realPCToFetchPC(const Addr &addr)
-        {
-                return addr;
-        }
-
-        static inline Addr fetchPCToRealPC(const Addr &addr)
-        {
-                return addr;
-        }
-
-        // the size of "fetched" instructions (not necessarily the size
-        // of real instructions for PISA)
-        static inline size_t fetchInstSize()
-        {
-                return sizeof(MachInst);
-        }
-
-        /**
-         * Function to insure ISA semantics about 0 registers.
-         * @param xc The execution context.
-         */
-        template <class XC>
-        static void zeroRegisters(XC *xc);
-};
-
-
-typedef SPARCISA TheISA;
-
-typedef TheISA::MachInst MachInst;
-typedef TheISA::Addr Addr;
-typedef TheISA::RegIndex RegIndex;
-typedef TheISA::IntReg IntReg;
-typedef TheISA::IntRegFile IntRegFile;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegFile FloatRegFile;
-typedef TheISA::MiscReg MiscReg;
-typedef TheISA::MiscRegFile MiscRegFile;
-typedef TheISA::AnyReg AnyReg;
-typedef TheISA::RegFile RegFile;
-
-const int VMPageSize   = TheISA::VMPageSize;
-const int LogVMPageSize   = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
-#ifndef FULL_SYSTEM
-class SyscallReturn {
-        public:
-           template <class T>
-           SyscallReturn(T v, bool s)
-           {
-               retval = (uint64_t)v;
-               success = s;
-           }
-
-           template <class T>
-           SyscallReturn(T v)
-           {
-               success = (v >= 0);
-               retval = (uint64_t)v;
-           }
-
-           ~SyscallReturn() {}
-
-           SyscallReturn& operator=(const SyscallReturn& s) {
-               retval = s.retval;
-               success = s.success;
-               return *this;
-           }
-
-           bool successful() { return success; }
-           uint64_t value() { return retval; }
-
-
-       private:
-           uint64_t retval;
-           bool success;
-};
-
-#endif
-
-
-#ifdef FULL_SYSTEM
-
-#include "arch/alpha/ev5.hh"
-#endif
-
-#endif // __ARCH_SPARC_ISA_TRAITS_HH__