Moved simple xilinx counter sim example to subdir

diff --git a/techlibs/xilinx/counter.v b/techlibs/xilinx/counter.v
deleted file mode 100644 (file)
index 72208bd..0000000
--- a/techlibs/xilinx/counter.v
+++ /dev/null
@@ -1,12 +0,0 @@
-module counter (clk, rst, en, count);
-
-   input clk, rst, en;
-   output reg [3:0] count;
-   
-   always @(posedge clk)
-      if (rst)
-         count <= 4'd0;
-      else if (en)
-         count <= count + 4'd1;
-
-endmodule

diff --git a/techlibs/xilinx/counter_tb.v b/techlibs/xilinx/counter_tb.v
deleted file mode 100644 (file)
index b6b6426..0000000
--- a/techlibs/xilinx/counter_tb.v
+++ /dev/null
@@ -1,61 +0,0 @@
-`timescale  1 ns / 1 ps
-
-module testbench;
-
-reg clk, en, rst;
-wire [3:0] count;
-
-counter uut_counter(
-       .clk(clk),
-       .count(count),
-       .en(en),
-       .rst(rst)
-);
-
-initial begin
-       clk <= 0;
-       forever begin
-               #50;
-               clk <= ~clk;
-       end
-end
-
-initial begin
-       @(posedge clk);
-       forever begin
-               @(posedge clk);
-               $display("%d", count);
-       end
-end
-
-initial begin
-       rst <= 1; en <= 0; @(posedge clk);
-       rst <= 1; en <= 0; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 1; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 1; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       rst <= 0; en <= 1; @(posedge clk);
-       rst <= 0; en <= 0; @(posedge clk);
-       $finish;
-end
-
-endmodule

diff --git a/techlibs/xilinx/example_sim_counter/counter.v b/techlibs/xilinx/example_sim_counter/counter.v
new file mode 100644 (file)
index 0000000..72208bd
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/counter.v
@@ -0,0 +1,12 @@
+module counter (clk, rst, en, count);
+
+   input clk, rst, en;
+   output reg [3:0] count;
+   
+   always @(posedge clk)
+      if (rst)
+         count <= 4'd0;
+      else if (en)
+         count <= count + 4'd1;
+
+endmodule

diff --git a/techlibs/xilinx/example_sim_counter/counter_tb.v b/techlibs/xilinx/example_sim_counter/counter_tb.v
new file mode 100644 (file)
index 0000000..b6b6426
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/counter_tb.v
@@ -0,0 +1,61 @@
+`timescale  1 ns / 1 ps
+
+module testbench;
+
+reg clk, en, rst;
+wire [3:0] count;
+
+counter uut_counter(
+       .clk(clk),
+       .count(count),
+       .en(en),
+       .rst(rst)
+);
+
+initial begin
+       clk <= 0;
+       forever begin
+               #50;
+               clk <= ~clk;
+       end
+end
+
+initial begin
+       @(posedge clk);
+       forever begin
+               @(posedge clk);
+               $display("%d", count);
+       end
+end
+
+initial begin
+       rst <= 1; en <= 0; @(posedge clk);
+       rst <= 1; en <= 0; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 1; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 1; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       rst <= 0; en <= 1; @(posedge clk);
+       rst <= 0; en <= 0; @(posedge clk);
+       $finish;
+end
+
+endmodule

diff --git a/techlibs/xilinx/example_sim_counter/run_testbench.sh b/techlibs/xilinx/example_sim_counter/run_testbench.sh
new file mode 100644 (file)
index 0000000..b4251f4
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/run_testbench.sh
@@ -0,0 +1,86 @@
+#!/bin/bash
+
+set -ex
+
+XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
+
+../../yosys - <<- EOT
+       # read design
+       read_verilog counter.v
+
+       # high-level synthesis
+       hierarchy -check -top counter
+       proc; opt; fsm; opt; techmap; opt
+
+       # mapping logic to LUTs using Berkeley ABC
+       abc -lut 6; opt
+
+       # map internal cells to FPGA cells
+       techmap -map cells.v; opt
+
+       # write netlist
+       write_verilog -noattr testbench_synth.v
+       write_edif testbench_synth.edif
+EOT
+
+iverilog -o testbench_gold counter_tb.v counter.v
+iverilog -o testbench_gate counter_tb.v testbench_synth.v \
+       $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+
+./testbench_gold > testbench_gold.txt
+./testbench_gate > testbench_gate.txt
+
+if diff -u testbench_gold.txt testbench_gate.txt; then
+       set +x; echo; echo; banner "  PASS  "
+else
+       exit 1
+fi
+
+if [ "$*" = "-map" ]; then
+       set -x
+
+       cat > testbench_synth.ut <<- EOT
+               -w
+               -g DebugBitstream:No
+               -g Binary:no
+               -g CRC:Enable
+               -g Reset_on_err:No
+               -g ConfigRate:2
+               -g ProgPin:PullUp
+               -g TckPin:PullUp
+               -g TdiPin:PullUp
+               -g TdoPin:PullUp
+               -g TmsPin:PullUp
+               -g UnusedPin:PullDown
+               -g UserID:0xFFFFFFFF
+               -g ExtMasterCclk_en:No
+               -g SPI_buswidth:1
+               -g TIMER_CFG:0xFFFF
+               -g multipin_wakeup:No
+               -g StartUpClk:CClk
+               -g DONE_cycle:4
+               -g GTS_cycle:5
+               -g GWE_cycle:6
+               -g LCK_cycle:NoWait
+               -g Security:None
+               -g DonePipe:No
+               -g DriveDone:No
+               -g en_sw_gsr:No
+               -g drive_awake:No
+               -g sw_clk:Startupclk
+               -g sw_gwe_cycle:5
+               -g sw_gts_cycle:4
+       EOT
+
+       $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
+       $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
+       $XILINX_DIR/bin/lin64/map -p xc7k70t-fbg676-1 -w -o testbench_mapped.ncd testbench_synth prffile.pcf
+       $XILINX_DIR/bin/lin64/par -w testbench_mapped.ncd testbench_synth.ncd prffile.pcf
+       $XILINX_DIR/bin/lin64/bitgen -f testbench_synth.ut testbench_synth.ncd
+fi
+
+if [ "$*" = "-clean" ]; then
+       rm -rf netlist.lst _xmsgs/ prffile.pcf
+       rm -f testbench_{synth,gold,gate,mapped}*
+fi
+

diff --git a/techlibs/xilinx/run_testbench.sh b/techlibs/xilinx/run_testbench.sh
deleted file mode 100644 (file)
index b4251f4..0000000
--- a/techlibs/xilinx/run_testbench.sh
+++ /dev/null
@@ -1,86 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
-
-../../yosys - <<- EOT
-       # read design
-       read_verilog counter.v
-
-       # high-level synthesis
-       hierarchy -check -top counter
-       proc; opt; fsm; opt; techmap; opt
-
-       # mapping logic to LUTs using Berkeley ABC
-       abc -lut 6; opt
-
-       # map internal cells to FPGA cells
-       techmap -map cells.v; opt
-
-       # write netlist
-       write_verilog -noattr testbench_synth.v
-       write_edif testbench_synth.edif
-EOT
-
-iverilog -o testbench_gold counter_tb.v counter.v
-iverilog -o testbench_gate counter_tb.v testbench_synth.v \
-       $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
-
-./testbench_gold > testbench_gold.txt
-./testbench_gate > testbench_gate.txt
-
-if diff -u testbench_gold.txt testbench_gate.txt; then
-       set +x; echo; echo; banner "  PASS  "
-else
-       exit 1
-fi
-
-if [ "$*" = "-map" ]; then
-       set -x
-
-       cat > testbench_synth.ut <<- EOT
-               -w
-               -g DebugBitstream:No
-               -g Binary:no
-               -g CRC:Enable
-               -g Reset_on_err:No
-               -g ConfigRate:2
-               -g ProgPin:PullUp
-               -g TckPin:PullUp
-               -g TdiPin:PullUp
-               -g TdoPin:PullUp
-               -g TmsPin:PullUp
-               -g UnusedPin:PullDown
-               -g UserID:0xFFFFFFFF
-               -g ExtMasterCclk_en:No
-               -g SPI_buswidth:1
-               -g TIMER_CFG:0xFFFF
-               -g multipin_wakeup:No
-               -g StartUpClk:CClk
-               -g DONE_cycle:4
-               -g GTS_cycle:5
-               -g GWE_cycle:6
-               -g LCK_cycle:NoWait
-               -g Security:None
-               -g DonePipe:No
-               -g DriveDone:No
-               -g en_sw_gsr:No
-               -g drive_awake:No
-               -g sw_clk:Startupclk
-               -g sw_gwe_cycle:5
-               -g sw_gts_cycle:4
-       EOT
-
-       $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
-       $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
-       $XILINX_DIR/bin/lin64/map -p xc7k70t-fbg676-1 -w -o testbench_mapped.ncd testbench_synth prffile.pcf
-       $XILINX_DIR/bin/lin64/par -w testbench_mapped.ncd testbench_synth.ncd prffile.pcf
-       $XILINX_DIR/bin/lin64/bitgen -f testbench_synth.ut testbench_synth.ncd
-fi
-
-if [ "$*" = "-clean" ]; then
-       rm -rf netlist.lst _xmsgs/ prffile.pcf
-       rm -f testbench_{synth,gold,gate,mapped}*
-fi
-