remove sv.setvl but *not* sv.svstep

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 620a9bdc5fc74440a15c2502f31de6b1cbb7549c..dfe3ce184ba207d5dc950c3789276fa93ae9a104 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1105,22 +1105,7 @@ class SVP64Asm:
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("svstep", bin(insn))
             yield ".long 0x%x" % insn
-
-        elif v30b_op in ["setvl", "setvl."]:
-            insn = 22 << (31-5)          # opcode 22, bits 0-5
-            fields = list(map(int, fields))
-            insn |= fields[0] << (31-10)  # RT       , bits 6-10
-            insn |= fields[1] << (31-15)  # RA       , bits 11-15
-            insn |= (fields[2]-1) << (31-22)  # SVi      , bits 16-22
-            insn |= fields[3] << (31-25)  # ms       , bit  25
-            insn |= fields[4] << (31-24)  # vs       , bit  24
-            insn |= fields[5] << (31-23)  # vf       , bit  23
-            insn |= 0b00000 << (31-30)  # XO       , bits 26..30
-            if opcode == 'setvl.':
-                insn |= 1 << (31-31)     # Rc=1     , bit 31
-            log("setvl", bin(insn))
-            yield ".long 0x%x" % insn
-
+        # argh, sv.fcoss etc. need to be done manually
         elif v30b_op in ["fcoss", "fcoss."]:
             insn = 59 << (31-5)  # opcode 59, bits 0-5
             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
@@ -1304,6 +1289,7 @@ if __name__ == '__main__':
         'sv.bc/all 3,12,192',
         'sv.bclr/vsbi 3,81.v,192',
         'sv.ld 5.v, 4(1.v)',
+        'sv.svstep. 2.v, 4, 0',
     ]
     isa = SVP64Asm(lst, macros=macros)
     print("list", list(isa))