clk2fflogic: nice names for autogenerated signals

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index dcaf364e929a23b10770d70bed03a65d101be287..1caf80c1128667db94cec18fdb14d8f8a752dcae 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -616,6 +616,23 @@ RTLIL::IdString new_id(std::string file, int line, std::string func)
        return stringf("$auto$%s:%d:%s$%d", file.c_str(), line, func.c_str(), autoidx++);
 }
 
+RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix)
+{
+#ifdef _WIN32
+       size_t pos = file.find_last_of("/\\");
+#else
+       size_t pos = file.find_last_of('/');
+#endif
+       if (pos != std::string::npos)
+               file = file.substr(pos+1);
+
+       pos = func.find_last_of(':');
+       if (pos != std::string::npos)
+               func = func.substr(pos+1);
+
+       return stringf("$auto$%s:%d:%s$%s$%d", file.c_str(), line, func.c_str(), suffix.c_str(), autoidx++);
+}
+
 RTLIL::Design *yosys_get_design()
 {
        return yosys_design;

diff --git a/kernel/yosys.h b/kernel/yosys.h
index 43aecdbc8e508529f50eb85404ca7f85cfb0e63d..5df7e2df047920620d3268ca295e810d150db4da 100644 (file)
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -321,9 +321,12 @@ Tcl_Interp *yosys_get_tcl_interp();
 extern RTLIL::Design *yosys_design;
 
 RTLIL::IdString new_id(std::string file, int line, std::string func);
+RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);
 
 #define NEW_ID \
        YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)
+#define NEW_ID_SUFFIX(suffix) \
+       YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
 
 // Create a statically allocated IdString object, using for example ID::A or ID($add).
 //

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index cbf7c5435e9e5d1c23d66c32a53e875428533e63..b9ba5ee3c5cfd10db33cf0936f3731f23af3f034 100644 (file)
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -40,7 +40,10 @@ struct Clk2fflogicPass : public Pass {
                log("\n");
        }
        SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity) {
-               Wire *past_sig = module->addWire(NEW_ID, GetSize(sig));
+               return wrap_async_control(module, sig, polarity, NEW_ID);
+       }
+       SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
+               Wire *past_sig = module->addWire(past_sig_id, GetSize(sig));
                module->addFf(NEW_ID, sig, past_sig);
                if (polarity)
                        sig = module->Or(NEW_ID, sig, past_sig);
@@ -105,7 +108,7 @@ struct Clk2fflogicPass : public Pass {
                                                        i, log_id(module), log_id(mem.memid), log_signal(port.clk),
                                                        log_signal(port.addr), log_signal(port.data));
 
-                                       Wire *past_clk = module->addWire(NEW_ID);
+                                       Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
                                        past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
                                        module->addFf(NEW_ID, port.clk, past_clk);
 
@@ -121,13 +124,13 @@ struct Clk2fflogicPass : public Pass {
 
                                        SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
 
-                                       SigSpec en_q = module->addWire(NEW_ID, GetSize(port.en));
+                                       SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
                                        module->addFf(NEW_ID, port.en, en_q);
 
-                                       SigSpec addr_q = module->addWire(NEW_ID, GetSize(port.addr));
+                                       SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
                                        module->addFf(NEW_ID, port.addr, addr_q);
 
-                                       SigSpec data_q = module->addWire(NEW_ID, GetSize(port.data));
+                                       SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
                                        module->addFf(NEW_ID, port.data, data_q);
 
                                        port.clk = State::S0;
@@ -153,7 +156,13 @@ struct Clk2fflogicPass : public Pass {
                                                continue;
                                        }
 
-                                       Wire *past_q = module->addWire(NEW_ID, ff.width);
+                                       // Strip spaces from signal name, since Yosys IDs can't contain spaces
+                                       // Spaces only occur when have a signal that's a slice of a larger bus,
+                                       // e.g. "\myreg [5:0]", so removing spaces shouldn't result in loss of uniqueness
+                                       std::string sig_q_str = log_signal(ff.sig_q);
+                                       sig_q_str.erase(std::remove(sig_q_str.begin(), sig_q_str.end(), ' '), sig_q_str.end());
+
+                                       Wire *past_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_q_wire", sig_q_str.c_str())), ff.width);
                                        if (!ff.is_fine) {
                                                module->addFf(NEW_ID, ff.sig_q, past_q);
                                        } else {
@@ -165,7 +174,7 @@ struct Clk2fflogicPass : public Pass {
                                        if (ff.has_clk) {
                                                ff.unmap_ce_srst(module);
 
-                                               Wire *past_clk = module->addWire(NEW_ID);
+                                               Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_clk#%s", sig_q_str.c_str(), log_signal(ff.sig_clk))));
                                                initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
 
                                                if (!ff.is_fine)
@@ -189,7 +198,7 @@ struct Clk2fflogicPass : public Pass {
 
                                                SigSpec clock_edge = module->Eqx(NEW_ID, {ff.sig_clk, SigSpec(past_clk)}, clock_edge_pattern);
 
-                                               Wire *past_d = module->addWire(NEW_ID, ff.width);
+                                               Wire *past_d = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_d_wire", sig_q_str.c_str())), ff.width);
                                                if (!ff.is_fine)
                                                        module->addFf(NEW_ID, ff.sig_d, past_d);
                                                else
@@ -236,7 +245,8 @@ struct Clk2fflogicPass : public Pass {
                                                        module->addAndGate(NEW_ID, qval, clrval, ff.sig_q);
                                                }
                                        } else if (ff.has_arst) {
-                                               SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst);
+                                               IdString id = NEW_ID_SUFFIX(stringf("%s#past_arst#%s", sig_q_str.c_str(), log_signal(ff.sig_arst)));
+                                               SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst, id);
                                                if (!ff.is_fine)
                                                        module->addMux(NEW_ID, qval, ff.val_arst, arst, ff.sig_q);
                                                else