Fix verific.cc PRIM_DLATCH handling

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6b303e4b66b6d5c06e51f3d15edc7f223be1c4a7..18fba9b76acf716a148ff952afeeee27b23c96c9 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -443,7 +443,13 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 
        if (inst->Type() == PRIM_DLATCH)
        {
-               module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               if (inst->GetAsyncCond()->IsGnd()) {
+                       module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               } else {
+                       RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
+                       RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
+                       module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               }
                return true;
        }