i965: Update workaround flush comments for Gen6 3DSTATE_VS.

Unfortunately, the workaround text never made it into the Sandybridge
PRM, so we still have to refer to the BSpec.

It also wasn't obvious why we needed this workaround at all, since we
don't currently do VS passthrough - but BLORP can turn off the VS.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 05b4ced42e6efdf8bac33f9b1aabbe3cd3590d01..fc26eb561ce3dbe32be8bc46cb253d417c0d6a1e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -554,7 +554,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
                            const brw_blorp_params *params)
 {
    if (brw->gen == 6) {
-      /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+      /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
        * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
        *
        *   [DevSNB] A pipeline flush must be programmed prior to a

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 7c459b4071911d46cc6d623c8b819e3607cee7c6..da20713e93febdcf2a551539a093ed4d9a4f1031 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -101,12 +101,16 @@ upload_vs_state(struct brw_context *brw)
    struct gl_context *ctx = &brw->ctx;
    uint32_t floating_point_mode = 0;
 
-   /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
+    *
     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
     *   command that causes the VS Function Enable to toggle. Pipeline
     *   flush can be executed by sending a PIPE_CONTROL command with CS
     *   stall bit set and a post sync operation.
+    *
+    * Although we don't disable the VS during normal drawing, BLORP sometimes
+    * disables it.  To be safe, do the flush here just in case.
     */
    intel_emit_post_sync_nonzero_flush(brw);