Generalize the mul_32bit and mul_signed fields of decode_rom_t

This changes the names of the mul_32bit and mul_signed fields of
decode_rom_t to is_32bit and is_signed, so they can be used with
other types of operations besides multiplies.

This plumbs the is_32bit and is_signed flags down into execute1,
though they are not used at this point.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

diff --git a/common.vhdl b/common.vhdl
index 67872c8a3e4369887b3e91da16014e5e41c5e159..284d52f311482d30d76c94ae40251e0608390ee4 100644 (file)
--- a/common.vhdl
+++ b/common.vhdl
@@ -61,9 +61,14 @@ package common is
                output_carry: std_ulogic;
                input_cr: std_ulogic;
                output_cr: std_ulogic;
+               is_32bit: std_ulogic;
+               is_signed: std_ulogic;
                 insn: std_ulogic_vector(31 downto 0);
        end record;
-       constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', invert_a => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0'));
+       constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
+               (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', invert_a => '0',
+                input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
+                is_32bit => '0', is_signed => '0', others => (others => '0'));
 
        type Decode2ToMultiplyType is record
                valid: std_ulogic;

diff --git a/decode1.vhdl b/decode1.vhdl
index 0173084450ebb12a469c41bc74c6cac1393ff63e..275c45e46ec0a4f727beaf77440f7b07fe1a7e3b 100644 (file)
--- a/decode1.vhdl
+++ b/decode1.vhdl
@@ -34,8 +34,8 @@ architecture behaviour of decode1 is
                             (ALU,    OP_ILLEGAL,   NONE,       NONE,        NONE, NONE, '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1');
 
         constant major_decode_rom_array : major_rom_array_t := (
-               --          unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                        op                                            in   out   A   in    out  len        ext             32  sgn             pipe
+               --          unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                        op                                            in   out   A   in    out  len        ext                                 pipe
                12 =>       (ALU,    OP_ADD,       RA,         CONST_SI,    NONE, RT,   '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- addic
                13 =>       (ALU,    OP_ADD,       RA,         CONST_SI,    NONE, RT,   '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', ONE,  '0', '1'), -- addic.
                 14 =>       (ALU,    OP_ADD,       RA_OR_ZERO, CONST_SI,    NONE, RT,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- addi
@@ -99,8 +99,8 @@ architecture behaviour of decode1 is
 
         -- indexed by bits 5, 3, 2 of instruction word
        constant decode_op_19_array : op_19_subop_array_t := (
-               --                 unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                               op                                            in   out   A   in    out  len        ext             32  sgn             pipe
+               --                 unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                               op                                            in   out   A   in    out  len        ext                                 pipe
                 -- mcrf; cr logical ops not implemented yet
                2#000#    =>       (ALU,    OP_MCRF,      NONE,       NONE,        NONE, NONE, '1', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'),
                -- addpcis not implemented yet
@@ -113,8 +113,8 @@ architecture behaviour of decode1 is
         );
 
        constant decode_op_30_array : op_30_subop_array_t := (
-               --                 unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                               op                                           in   out   A   in    out  len        ext             32  sgn             pipe
+               --                 unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                               op                                           in   out   A   in    out  len        ext                                pipe
                2#010#   =>       (ALU,    OP_RLDIC,     NONE,       NONE,        RS,   RA,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'),
                2#000#   =>       (ALU,    OP_RLDICL,    NONE,       NONE,        RS,   RA,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'),
                2#001#   =>       (ALU,    OP_RLDICR,    NONE,       NONE,        RS,   RA,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'),
@@ -126,8 +126,8 @@ architecture behaviour of decode1 is
 
        -- Note: reformat with column -t -o ' '
        constant decode_op_31_array : op_31_subop_array_t := (
-               --                       unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                                    op                                            in   out   A   in    out  len        ext             32  sgn             pipe
+               --                       unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                                    op                                            in   out   A   in    out  len        ext                                 pipe
                2#0100001010#  =>       (ALU,    OP_ADD,       RA,         RB,          NONE, RT,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'), -- add
                2#0000001010#  =>       (ALU,    OP_ADD,       RA,         RB,          NONE, RT,   '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'), -- addc
                2#0010001010#  =>       (ALU,    OP_ADD,       RA,         RB,          NONE, RT,   '0', '0', '0', CA,   '1', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'), -- adde
@@ -286,8 +286,8 @@ architecture behaviour of decode1 is
        );
 
         constant decode_op_58_array : minor_rom_array_2_t := (
-               --              unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                           op                                            in   out   A   in    out  len        ext             32  sgn             pipe
+               --              unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                           op                                            in   out   A   in    out  len        ext                                 pipe
                0     =>       (LDST,   OP_LOAD,      RA_OR_ZERO, CONST_DS,    NONE, RT,   '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- ld
                 1     =>       (LDST,   OP_LOAD,      RA_OR_ZERO, CONST_DS,    NONE, RT,   '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '1'), -- ldu
                 2     =>       (LDST,   OP_LOAD,      RA_OR_ZERO, CONST_DS,    NONE, RT,   '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '1'), -- lwa
@@ -295,15 +295,15 @@ architecture behaviour of decode1 is
         );
 
         constant decode_op_62_array : minor_rom_array_2_t := (
-               --              unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-               --                            op                                           in   out   A   in    out  len        ext             32  sgn             pipe
+               --              unit    internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+               --                            op                                           in   out   A   in    out  len        ext                                 pipe
                0     =>       (LDST,   OP_STORE,     RA_OR_ZERO, CONST_DS,    RS,   NONE, '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- std
                1     =>       (LDST,   OP_STORE,     RA_OR_ZERO, CONST_DS,    RS,   NONE, '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '1'), -- stdu
                others   => decode_rom_init
         );
 
-        --                                       unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv mul  mul  rc    lk   sgl
-        --                                                      op                                           in   out   A   in    out  len        ext             32  sgn             pipe
+        --                                       unit     internal      in1         in2          in3   out   CR   CR   inv  cry   cry  ldst  BR   sgn  upd  rsrv 32b  sgn  rc    lk   sgl
+        --                                                      op                                           in   out   A   in    out  len        ext                                 pipe
         constant attn_instr    : decode_rom_t := (ALU,    OP_ILLEGAL,   NONE,       NONE,        NONE, NONE, '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1');
        constant nop_instr     : decode_rom_t := (ALU,    OP_NOP,       NONE,       NONE,        NONE, NONE, '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1');
         constant sim_cfg_instr : decode_rom_t := (ALU,    OP_SIM_CONFIG,NONE,       NONE,        NONE, RT,   '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1');

diff --git a/decode2.vhdl b/decode2.vhdl
index e22b065d8fadac605c6ea6cfdae91fcbacc1ba91..7c6c0cacb29883f7ec4c8270ea9ad821f6622459 100644 (file)
--- a/decode2.vhdl
+++ b/decode2.vhdl
@@ -199,6 +199,8 @@ begin
                 v.e.invert_a := d_in.decode.invert_a;
                v.e.input_carry := d_in.decode.input_carry;
                v.e.output_carry := d_in.decode.output_carry;
+               v.e.is_32bit := d_in.decode.is_32bit;
+               v.e.is_signed := d_in.decode.is_signed;
                if d_in.decode.lr = '1' then
                        v.e.lr := insn_lk(d_in.insn);
                end if;
@@ -211,8 +213,8 @@ begin
                v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
                v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 
-               if d_in.decode.mul_32bit = '1' then
-                       if d_in.decode.mul_signed = '1' then
+               if d_in.decode.is_32bit = '1' then
+                       if d_in.decode.is_signed = '1' then
                                v.m.data1 := (others => mul_a(31));
                                v.m.data1(31 downto 0) := mul_a(31 downto 0);
                                v.m.data2 := (others => mul_b(31));
@@ -222,7 +224,7 @@ begin
                                v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
                        end if;
                else
-                       if d_in.decode.mul_signed = '1' then
+                       if d_in.decode.is_signed = '1' then
                                v.m.data1 := mul_a(63) & mul_a;
                                v.m.data2 := mul_b(63) & mul_b;
                        else

diff --git a/decode_types.vhdl b/decode_types.vhdl
index cbdf449422856e99658fbc4ae7db43b7a52e8d62..6ac91a51849360903b6dacd714ca4ee8721066ec 100644 (file)
--- a/decode_types.vhdl
+++ b/decode_types.vhdl
@@ -71,9 +71,9 @@ package decode_types is
                update       : std_ulogic;
                reserve      : std_ulogic;
 
-               -- multiplier signals
-               mul_32bit     : std_ulogic;
-               mul_signed    : std_ulogic;
+               -- multiplier and ALU signals
+               is_32bit     : std_ulogic;
+               is_signed    : std_ulogic;
 
                rc           : rc_t;
                lr           : std_ulogic;
@@ -86,8 +86,8 @@ package decode_types is
                output_reg_a => NONE, input_cr => '0', output_cr => '0',
                invert_a => '0', input_carry => ZERO, output_carry => '0',
                length => NONE, byte_reverse => '0', sign_extend => '0',
-               update => '0', reserve => '0', mul_32bit => '0',
-               mul_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0');
+               update => '0', reserve => '0', is_32bit => '0',
+               is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0');
 
 end decode_types;