tests: Always specify memory mode in every test system.

Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index baeab677ac50860a773c3e56d71f69af22030f24..a92c61ba19cd1af9f0ca190c23abca45f61965ca 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -40,7 +40,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller

diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index a4dddb08fa95a901391a0026e70e7186ab214552..a33a2ac06251a6e7e91e2086e251fd9ee4cf35c2 100644 (file)
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -53,7 +53,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 cpu.connectAllPorts(system.membus)

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 9bdef5eef2e30be054e54a4736bdedc4e852750e..126e71ed570c8df11d31de8996a8b5c5d3227854 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -38,7 +38,8 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
+                mem_mode = "timing")
 
 for cpu in cpus:
     # create the interrupt controller

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 6f3bddc6f09ffe848291c3164c47f4a716a2f169..c3a4929bb4afb0a752a3e49ec861655acfc88528 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -35,7 +35,10 @@ nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
+system = System(cpu = cpus,
+                physmem = SimpleDRAM(),
+                membus = CoherentBus(),
+                mem_mode = "timing")
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')

diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index a45939f36e19911beb4df15a0def837c01e1bdeb..26dbb000b3eecd0d933c030a6cce95fbc400a952 100644 (file)
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -40,7 +40,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = ruby_memory,
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.physmem.port = system.membus.master
 # create the interrupt controller
 cpu.createInterruptController()

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 30c2f413eca988aaad5b41b531fd1fc212f38f30..474d139023414a45ffe9f87141d300a2f44d2f67 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -42,7 +42,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 5a851ba2584e8d5d2aeb8244fb00019b428b3be4..b366f01e5b384ea5d6fe3dbe04f1e3b771c6c24f 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
                               L2Cache(size = '2MB'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller