add testcase for #1614

diff --git a/tests/various/bug1614.ys b/tests/various/bug1614.ys
new file mode 100644 (file)
index 0000000..6fbe84a
--- /dev/null
+++ b/tests/various/bug1614.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module testcase;
+    wire [3:0] #1 a = 4'b0000;
+endmodule
+EOT