aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array

SME2 adds various new fields that are similar to
AARCH64_OPND_SME_ZA_array, but are distinguished by the size of
their offset fields.  This patch adds _off4 to the name of the
field that we already have.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6ebfcda7dff54d31f4af1653fa9d7793bac24409..b4e0b937605f5a57eaca860deb253b72bfe0f1b8 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7647,7 +7647,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          info->imm.value = val;
          break;
 
-       case AARCH64_OPND_SME_ZA_array:
+       case AARCH64_OPND_SME_ZA_array_off4:
          if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
                                       &info->indexed_za, &qualifier, 0))
            goto failure;

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 5c9b5e5dac10da2b4511204ea23ec576b3d01ab4..945846685178ccb9909b0ee27d17f343525b5de0 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -487,11 +487,11 @@ enum aarch64_opnd
   AARCH64_OPND_SME_ZA_HV_idx_dest,     /* SME destination ZA tile vector.  */
   AARCH64_OPND_SME_Pm,         /* SME scalable predicate register, bits [15:13].  */
   AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles.  */
-  AARCH64_OPND_SME_ZA_HV_idx_ldstr,    /* SME destination ZA tile vector.  */
-  AARCH64_OPND_SME_ZA_array,        /* SME ZA[<Wv>{, #<imm>}].  */
+  AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector.  */
+  AARCH64_OPND_SME_ZA_array_off4,   /* SME ZA[<Wv>{, #<imm>}].  */
   AARCH64_OPND_SME_ADDR_RI_U4xVL,   /* SME [<Xn|SP>{, #<imm>, MUL VL}].  */
   AARCH64_OPND_SME_SM_ZA,           /* SME {SM | ZA}.  */
-  AARCH64_OPND_SME_PnT_Wm_imm,           /* SME <Pn>.<T>[<Wm>, #<imm>].  */
+  AARCH64_OPND_SME_PnT_Wm_imm,      /* SME <Pn>.<T>[<Wm>, #<imm>].  */
   AARCH64_OPND_TME_UIMM16,     /* TME unsigned 16-bit immediate.  */
   AARCH64_OPND_SM3_IMM2,       /* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,   /* [Rd]!, in bits [0, 4].  */

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index fe67dbc9b62c54c0a7df190c2374be3a062869d1..65ce8d42b0a5beeb318e44e36bbccfd042c20ba6 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -241,7 +241,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
   {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
-  {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"},
+  {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"},
   {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 969362a56cd1fc537857c30f9de9a46b7075d878..e97201bb03a3160b7af9e74d55ccf1592ad1ea22 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1684,7 +1684,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
            return 0;
          break;
 
-       case AARCH64_OPND_SME_ZA_array:
+       case AARCH64_OPND_SME_ZA_array_off4:
          if (!check_za_access (opnd, mismatch_detail, idx, 12, 15))
            return 0;
          break;
@@ -2882,7 +2882,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
         */
         case sme_ldr:
         case sme_str:
-          assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
+          assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array_off4);
           assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
           if (inst->operands[0].indexed_za.index.imm
               != inst->operands[1].addr.offset.imm)
@@ -3686,7 +3686,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
       print_sme_za_list (buf, size, opnd->reg.regno, styler);
       break;
 
-    case AARCH64_OPND_SME_ZA_array:
+    case AARCH64_OPND_SME_ZA_array_off4:
       snprintf (buf, size, "%s[%s, %s]",
                style_reg (styler, "za"),
                style_reg (styler, "w%d", opnd->indexed_za.index.regno),

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index aa05ca0f4a9617def6e8f79403b23ae376e4cb76..75497ea6065fac3e31d9d85da597b9085997eeca 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5265,8 +5265,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DUU, 0, 0),
   SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QUU, 0, 0),
 
-  SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
-  SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
+  SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1),
+  SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1),
 
   SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
   SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
@@ -5921,7 +5921,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0,            \
       F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0),   \
       "an SME horizontal or vertical vector access register")          \
-    Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0,                      \
+    Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0,                 \
       F(FLD_SME_Rv,FLD_imm4_0), "ZA array")                            \
     Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
       F(FLD_Rn,FLD_imm4_0), "memory offset")                           \