abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
- val device = new SimpleDevice("spi", Seq("sifive,spi0"))
+ val device = new SimpleDevice("spi", Seq("sifive,spi0")) {
+ override def describe(resources: ResourceBindings): Description = {
+ val Description(name, mapping) = super.describe(resources)
+ val rangesSeq = resources("ranges").map(_.value)
+ val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq)
+ Description(name, mapping ++ ranges)
+ }
+ }
+
val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}
require(isPow2(c.fSize))
val fnode = TLManagerNode(1, TLManagerParameters(
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
+ resources = Seq(Resource(device, "ranges")),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, 1),