se.py Ruby: Connect TLB walker ports

In order to ensure correct functionality of switch CPUs, the TLB walker ports
must be connected to the Ruby system in x86 simulation.

This fixes x86 assertion failures that the TLB walker ports are not connected
during the CPU switch process.

diff --git a/configs/example/se.py b/configs/example/se.py
index 887e414ca3dfe9e8c54676b0d48cf1d32f79fea1..b60baf0419f20fbb8e34172e425c65a9c0bcf5c2 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -198,6 +198,9 @@ if options.ruby:
         # Connect the cpu's cache ports to Ruby
         system.cpu[i].icache_port = ruby_port.slave
         system.cpu[i].dcache_port = ruby_port.slave
+        if buildEnv['TARGET_ISA'] == 'x86':
+            system.cpu[i].itb.walker.port = ruby_port.slave
+            system.cpu[i].dtb.walker.port = ruby_port.slave
 else:
     system.system_port = system.membus.slave
     system.physmem.port = system.membus.master