sim: bfin: handle large shift values with accumulator shift insns

When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter).  So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index c7029816466f55512e5c8ddb76091e5c274f4189..31efa11cbce05849b2cf6b6f59ba211157451534 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,9 @@
+2011-06-18  Robin Getz  <robin.getz@analog.com>
+
+       * bfin-sim.c (decode_dsp32shiftimm_0): When shift is greater than
+       32, perform a left shift.  Update the corresponding AV bit.  Set
+       AZ when the low 32bits are also zero.
+
 2011-06-18  Robin Getz  <robin.getz@analog.com>
 
        * bfin-sim.c (decode_dsp32shiftimm_0): With left shift vector insns,

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 11eea3a234b485021474637793944c11b4649050..b982aaf70a084be1a2ce3de090ec38c0ae0013e5 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5775,11 +5775,17 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       if (sop == 0)
        acc <<= shiftup;
       else
-       acc >>= shiftdn;
+       {
+         if (shiftdn <= 32)
+           acc >>= shiftdn;
+         else
+           acc <<= 32 - (shiftdn & 0x1f);
+       }
 
       SET_AREG (HLs, acc);
+      SET_ASTATREG (av[HLs], 0);
       SET_ASTATREG (an, !!(acc & 0x8000000000ull));
-      SET_ASTATREG (az, acc == 0);
+      SET_ASTATREG (az, (acc & 0xFFFFFFFFFF) == 0);
     }
   else if (sop == 1 && sopcde == 1 && bit8 == 0)
     {