arch-arm: Disambuiguate NumFloatV7ArchRegs usage

Sometimes NumFloatV7ArchRegs is used to specify the maximum number of
AArch32 floating point registers. Sometimes it is just used for indexing
a free register storage to be used by microcode.  In that scenario,
VecSpecialElem should be used, which is a index to the first available
non architectural register for floating point.

Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index e6de8321d1400877c33fad810b8257d03241ad14..bff0d3e7230e105b2559aaa985d7656a26dd2ada 100644 (file)
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -472,7 +472,7 @@ VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
     if (deinterleave) numMicroops += (regs / elems);
     microOps = new StaticInstPtr[numMicroops];
 
-    RegIndex rMid = deinterleave ? NumFloatV7ArchRegs : vd * 2;
+    RegIndex rMid = deinterleave ? VecSpecialElem : vd * 2;
 
     uint32_t noAlign = TLB::MustBeOne;
 
@@ -575,7 +575,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst,
     numMicroops += (regs / elems);
     microOps = new StaticInstPtr[numMicroops];
 
-    RegIndex ufp0 = NumFloatV7ArchRegs;
+    RegIndex ufp0 = VecSpecialElem;
 
     unsigned uopIdx = 0;
     switch (loadSize) {
@@ -837,7 +837,7 @@ VstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 
     uint32_t noAlign = TLB::MustBeOne;
 
-    RegIndex rMid = interleave ? NumFloatV7ArchRegs : vd * 2;
+    RegIndex rMid = interleave ? VecSpecialElem : vd * 2;
 
     unsigned uopIdx = 0;
     if (interleave) {
@@ -939,7 +939,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst,
     numMicroops += (regs / elems);
     microOps = new StaticInstPtr[numMicroops];
 
-    RegIndex ufp0 = NumFloatV7ArchRegs;
+    RegIndex ufp0 = VecSpecialElem;
 
     unsigned uopIdx = 0;
     switch (elems) {

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index f2dfce4253c529a97d5a7de2cf66bce8a0b721ae..1c746ff380bc6954544a53f79c02a1364eac640d 100644 (file)
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -87,7 +87,11 @@ const int NumCCRegs = NUM_CCREGS;
 const int NumMiscRegs = NUM_MISCREGS;
 
 // Vec, PredVec
-const int NumFloatV7ArchRegs  = 64;
+// NumFloatV7ArchRegs: This in theory should be 32.
+// However in A32 gem5 is splitting double register accesses in two
+// subsequent single register ones. This means we would use a index
+// bigger than 31 when accessing D16-D31.
+const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
 const int NumVecV7ArchRegs  = 16; // Q0-Q15
 const int NumVecV8ArchRegs  = 32; // V0-V31
 const int NumVecSpecialRegs = 8;
@@ -116,6 +120,7 @@ const int PCReg = INTREG_PC;
 const int ZeroReg = INTREG_ZERO;
 
 // Vec, PredVec indices
+const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
 const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
 const int INTRLVREG1 = INTRLVREG0 + 1;
 const int INTRLVREG2 = INTRLVREG0 + 2;