Added $meminit cell type

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 60e6606f8bfc43dc0e588c4b2126f22bdeb91e46..57bcde47104ffb7770b57a94dd8f9244a9fd8dba 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -135,6 +135,7 @@ struct CellTypes
 
                setup_type("$memrd", {CLK, ADDR}, {DATA});
                setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
+               setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
                setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
 
                setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 776625b9cf5bf9e021e48b9e325ad7cb37f650d0..9fd3d29593dbf6d3fd018d3f9e110e0e4df1cc08 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -904,6 +904,15 @@ namespace {
                                return;
                        }
 
+                       if (cell->type == "$meminit") {
+                               param("\\MEMID");
+                               param("\\PRIORITY");
+                               port("\\ADDR", param("\\ABITS"));
+                               port("\\DATA", param("\\WIDTH"));
+                               check_expected();
+                               return;
+                       }
+
                        if (cell->type == "$mem") {
                                param("\\MEMID");
                                param("\\SIZE");

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 6a7e6051d3feeff2871761003921628002066a69..aea341759c27429b647f75de7803447d623d680b 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose)
                                        if (bit.wire != nullptr)
                                                wire2driver[bit].insert(cell);
                }
-               if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
+               if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr())
                        queue.insert(cell);
                else
                        unused.insert(cell);

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a73c6ee09183d0f843611df0cab6e124e642e7f5..6707e190bdd98d1b93133b055e26f0520c2491d7 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1514,6 +1514,28 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$meminit (ADDR, DATA);
+
+parameter MEMID = "";
+parameter ABITS = 8;
+parameter WIDTH = 8;
+
+parameter PRIORITY = 0;
+
+input [ABITS-1:0] ADDR;
+input [WIDTH-1:0] DATA;
+
+initial begin
+       if (MEMID != "") begin
+               $display("ERROR: Found non-simulatable instance of $meminit!");
+               $finish;
+       end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";