Verific updates

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/Makefile b/Makefile
index 053796e9d72c500a20d510b08b59cfef0b561d88..8da6315fb90342f16d2461667c69324188914bb2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -357,7 +357,7 @@ endif
 
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
-VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree
+VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
 LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 971f0b24a8514688a0b778c8f0ae1e59308bd9f5..bc035c31a0ed781922d002b4c18110c9415f6181 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2094,42 +2094,6 @@ struct VerificPass : public Pass {
 
                        if (mode_all)
                        {
-#if 0
-                               log("Running veri_file::ElaborateAll().\n");
-                               if (!veri_file::ElaborateAll())
-                                       log_cmd_error("Elaboration of Verilog modules failed.\n");
-
-                               log("Running vhdl_file::ElaborateAll().\n");
-                               if (!vhdl_file::ElaborateAll())
-                                       log_cmd_error("Elaboration of VHDL modules failed.\n");
-
-                               Library *lib = Netlist::PresentDesign()->Owner()->Owner();
-
-                               if (argidx == GetSize(args))
-                               {
-                                       MapIter iter;
-                                       char *iter_name;
-                                       Verific::Cell *iter_cell;
-
-                                       FOREACH_MAP_ITEM(lib->GetCells(), iter, &iter_name, &iter_cell) {
-                                               if (*iter_name != '$')
-                                                       nl_todo.insert(iter_cell->GetFirstNetlist());
-                                       }
-                               }
-                               else
-                               {
-                                       for (; argidx < GetSize(args); argidx++)
-                                       {
-                                               Verific::Cell *cell = lib->GetCell(args[argidx].c_str());
-
-                                               if (cell == nullptr)
-                                                       log_cmd_error("Module not found: %s\n", args[argidx].c_str());
-
-                                               nl_todo.insert(cell->GetFirstNetlist());
-                                               cell->GetFirstNetlist()->SetPresentDesign();
-                                       }
-                               }
-#else
                                log("Running hier_tree::ElaborateAll().\n");
 
                                VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
@@ -2146,28 +2110,12 @@ struct VerificPass : public Pass {
                                FOREACH_ARRAY_ITEM(netlists, i, nl)
                                        nl_todo.insert(nl);
                                delete netlists;
-#endif
                        }
                        else
                        {
                                if (argidx == GetSize(args))
                                        log_cmd_error("No top module specified.\n");
 
-#if 0
-                               for (; argidx < GetSize(args); argidx++) {
-                                       if (veri_file::GetModule(args[argidx].c_str())) {
-                                               log("Running veri_file::Elaborate(\"%s\").\n", args[argidx].c_str());
-                                               if (!veri_file::Elaborate(args[argidx].c_str()))
-                                                       log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
-                                               nl_todo.insert(Netlist::PresentDesign());
-                                       } else {
-                                               log("Running vhdl_file::Elaborate(\"%s\").\n", args[argidx].c_str());
-                                               if (!vhdl_file::Elaborate(args[argidx].c_str()))
-                                                       log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
-                                               nl_todo.insert(Netlist::PresentDesign());
-                                       }
-                               }
-#else
                                Array veri_modules, vhdl_units;
                                for (; argidx < GetSize(args); argidx++)
                                {
@@ -2199,7 +2147,6 @@ struct VerificPass : public Pass {
                                FOREACH_ARRAY_ITEM(netlists, i, nl)
                                        nl_todo.insert(nl);
                                delete netlists;
-#endif
                        }
 
                        if (!verific_error_msg.empty())