Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
authorClifford Wolf <clifford@clifford.at>
Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)
committerGitHub <noreply@github.com>
Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)
write_verilog: write RTLIL::Sa aka - as Verilog ?

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backends/verilog/verilog_backend.cc

Simple merge