arm: Use little endian packet accessors.

We know data is little endian, so we can use those accessors
explicitly.

Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45
Reviewed-on: https://gem5-review.googlesource.com/c/13457
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/dev/arm/a9scu.cc b/src/dev/arm/a9scu.cc
index 86a50ae8e78f02e81cfc1e6d549b67b8f5f26412..677101b36a40b6f18898bc18c210cf65e669ddaf 100644 (file)
--- a/src/dev/arm/a9scu.cc
+++ b/src/dev/arm/a9scu.cc
@@ -59,7 +59,7 @@ A9SCU::read(PacketPtr pkt)
 
     switch(daddr) {
       case Control:
-        pkt->set(1); // SCU already enabled
+        pkt->setLE(1); // SCU already enabled
         break;
       case Config:
         /* Without making a completely new SCU, we can use the core count field
@@ -75,7 +75,7 @@ A9SCU::read(PacketPtr pkt)
         int smp_bits, core_cnt;
         smp_bits = power(2,sys->numContexts()) - 1;
         core_cnt = sys->numContexts() - 1;
-        pkt->set(smp_bits << 4 | core_cnt);
+        pkt->setLE(smp_bits << 4 | core_cnt);
         break;
       default:
         // Only configuration register is implemented

diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc
index d9acc9a007484c5492a9f08b69f326c9f4661783..a8404a42cbe282c932d0d7e06cd764a3431eaeaa 100644 (file)
--- a/src/dev/arm/amba_device.cc
+++ b/src/dev/arm/amba_device.cc
@@ -83,6 +83,6 @@ AmbaDevice::readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
             (amba_id >> byte) & 0xFF,
             pkt->getAddr() - pio_addr, byte);
     assert(pkt->getSize() == 4);
-    pkt->set<uint32_t>((amba_id >> byte) & 0xFF);
+    pkt->setLE<uint32_t>((amba_id >> byte) & 0xFF);
     return true;
 }

diff --git a/src/dev/arm/amba_fake.cc b/src/dev/arm/amba_fake.cc
index 475ff768a3ea2770785139e5bcaff66a0e8bca0a..9c14140fb234c31efabfa32fbf1d2dac3ed8e763 100644 (file)
--- a/src/dev/arm/amba_fake.cc
+++ b/src/dev/arm/amba_fake.cc
@@ -61,7 +61,7 @@ AmbaFake::read(PacketPtr pkt)
 
     DPRINTF(AMBA, " read register %#x\n", daddr);
 
-    pkt->set<uint32_t>(0);
+    pkt->setLE<uint32_t>(0);
     if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
         panic("Tried to read AmbaFake at offset %#x that doesn't exist\n", daddr);
 

diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc
index 9cfce3a48777fbbc3a63d9c41d4c5c70fe47cad3..ba2d3e942297fe6d05e807913f90507a903f7038 100644 (file)
--- a/src/dev/arm/energy_ctrl.cc
+++ b/src/dev/arm/energy_ctrl.cc
@@ -72,7 +72,7 @@ EnergyCtrl::read(PacketPtr pkt)
 
     if (!dvfsHandler->isEnabled()) {
         // NB: Zero is a good response if the handler is disabled
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
         warn_once("EnergyCtrl: Disabled handler, ignoring read from reg %i\n",
                   reg);
         DPRINTF(EnergyCtrl, "dvfs handler disabled, return 0 for read from "\
@@ -141,7 +141,7 @@ EnergyCtrl::read(PacketPtr pkt)
         panic("Tried to read EnergyCtrl at offset %#x / reg %i\n", daddr,
               reg);
     }
-    pkt->set<uint32_t>(result);
+    pkt->setLE<uint32_t>(result);
     pkt->makeAtomicResponse();
     return pioDelay;
 }
@@ -153,7 +153,7 @@ EnergyCtrl::write(PacketPtr pkt)
     assert(pkt->getSize() == 4);
 
     uint32_t data;
-    data = pkt->get<uint32_t>();
+    data = pkt->getLE<uint32_t>();
 
     Addr daddr = pkt->getAddr() - pioAddr;
     assert((daddr & 3) == 0);

diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 92c39c2aeb70366289c3d497506b6677df2cf8e2..0994f6dd4854b1bb1f2c5d2392736c469e79b06c 100644 (file)
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -583,9 +583,9 @@ GenericTimerMem::read(PacketPtr pkt)
     DPRINTF(Timer, "Read 0x%x <- 0x%x(%i)\n", value, addr, size);
 
     if (size == 8) {
-        pkt->set<uint64_t>(value);
+        pkt->setLE<uint64_t>(value);
     } else if (size == 4) {
-        pkt->set<uint32_t>(value);
+        pkt->setLE<uint32_t>(value);
     } else {
         panic("Unexpected access size: %i\n", size);
     }
@@ -602,7 +602,7 @@ GenericTimerMem::write(PacketPtr pkt)
 
     const Addr addr(pkt->getAddr());
     const uint64_t value(size == 8 ?
-                         pkt->get<uint64_t>() : pkt->get<uint32_t>());
+                         pkt->getLE<uint64_t>() : pkt->getLE<uint32_t>());
 
     DPRINTF(Timer, "Write 0x%x -> 0x%x(%i)\n", value, addr, size);
     if (ctrlRange.contains(addr)) {

diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 99124b08c5af82c213d8bbab7942551353f5ad85..a24e5639106f783f2defcf64ab7a96aa3b35a6ae 100644 (file)
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -145,13 +145,13 @@ GicV2::readDistributor(PacketPtr pkt)
 
     switch (pkt->getSize()) {
       case 1:
-        pkt->set<uint8_t>(resp);
+        pkt->setLE<uint8_t>(resp);
         break;
       case 2:
-        pkt->set<uint16_t>(resp);
+        pkt->setLE<uint16_t>(resp);
         break;
       case 4:
-        pkt->set<uint32_t>(resp);
+        pkt->setLE<uint32_t>(resp);
         break;
       default:
         panic("Invalid size while reading Distributor regs in GIC: %d\n",
@@ -296,7 +296,7 @@ GicV2::readCpu(PacketPtr pkt)
     DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
             ctx);
 
-    pkt->set<uint32_t>(readCpu(ctx, daddr));
+    pkt->setLE<uint32_t>(readCpu(ctx, daddr));
 
     pkt->makeAtomicResponse();
     return cpuPioDelay;
@@ -395,13 +395,13 @@ GicV2::writeDistributor(PacketPtr pkt)
     switch (data_sz)
     {
       case 1:
-        pkt_data = pkt->get<uint8_t>();
+        pkt_data = pkt->getLE<uint8_t>();
         break;
       case 2:
-        pkt_data = pkt->get<uint16_t>();
+        pkt_data = pkt->getLE<uint16_t>();
         break;
       case 4:
-        pkt_data = pkt->get<uint32_t>();
+        pkt_data = pkt->getLE<uint32_t>();
         break;
       default:
         panic("Invalid size when writing to priority regs in Gic: %d\n",
@@ -558,7 +558,7 @@ GicV2::writeCpu(PacketPtr pkt)
 
     assert(pkt->req->hasContextId());
     const ContextID ctx = pkt->req->contextId();
-    const uint32_t data = pkt->get<uint32_t>();
+    const uint32_t data = pkt->getLE<uint32_t>();
 
     DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
             ctx, daddr, data);

diff --git a/src/dev/arm/gic_v2m.cc b/src/dev/arm/gic_v2m.cc
index d90cb986e9d9ef41f61a7bde4fecbda98a9a6a26..9ae0f68ee0ffe125eda4b5286052aa858732cf8c 100644 (file)
--- a/src/dev/arm/gic_v2m.cc
+++ b/src/dev/arm/gic_v2m.cc
@@ -114,18 +114,18 @@ Gicv2m::read(PacketPtr pkt)
 
     switch (offset) {
       case MSI_TYPER:
-        pkt->set<uint32_t>((frames[frame]->spi_base << 16) |
+        pkt->setLE<uint32_t>((frames[frame]->spi_base << 16) |
                            frames[frame]->spi_len);
         break;
 
       case PER_ID4:
-        pkt->set<uint32_t>(0x4 | ((4+log2framenum) << 4));
+        pkt->setLE<uint32_t>(0x4 | ((4+log2framenum) << 4));
         // Nr of 4KB blocks used by component.  This is messy as frames are 64K
         // (16, ie 2^4) and we should assert we're given a Po2 number of frames.
         break;
       default:
         DPRINTF(GICV2M, "GICv2m: Read of unk reg %#x\n", offset);
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
     };
 
     pkt->makeAtomicResponse();
@@ -144,7 +144,7 @@ Gicv2m::write(PacketPtr pkt)
 
     if (offset == MSI_SETSPI_NSR) {
         /* Is payload SPI number within range? */
-        uint32_t m = pkt->get<uint32_t>();
+        uint32_t m = pkt->getLE<uint32_t>();
         if (m >= frames[frame]->spi_base &&
             m < (frames[frame]->spi_base + frames[frame]->spi_len)) {
             DPRINTF(GICV2M, "GICv2m: Frame %d raising MSI %d\n", frame, m);

diff --git a/src/dev/arm/gpu_nomali.cc b/src/dev/arm/gpu_nomali.cc
index a6c3e29e58743fdfe93ae08a8ec112e1f8d8e262..c8630c7075c3b41875fe8a2273af795dfc5be82d 100644 (file)
--- a/src/dev/arm/gpu_nomali.cc
+++ b/src/dev/arm/gpu_nomali.cc
@@ -160,7 +160,7 @@ NoMaliGpu::read(PacketPtr pkt)
     else if (addr & 0x3)
         panic("Unaligned GPU read: %i\n", size);
 
-    pkt->set<uint32_t>(readReg(addr));
+    pkt->setLE<uint32_t>(readReg(addr));
     pkt->makeResponse();
 
     return 0;
@@ -181,7 +181,7 @@ NoMaliGpu::write(PacketPtr pkt)
     else if (addr & 0x3)
         panic("Unaligned GPU write: %i\n", size);
 
-    writeReg(addr, pkt->get<uint32_t>());
+    writeReg(addr, pkt->getLE<uint32_t>());
     pkt->makeAtomicResponse();
 
     return 0;

diff --git a/src/dev/arm/hdlcd.cc b/src/dev/arm/hdlcd.cc
index 20dc7d44ef4a75a80bba2b50bf09efeb0ad19565..113c1c358836db4ad8c9813549d86887a3bde20a 100644 (file)
--- a/src/dev/arm/hdlcd.cc
+++ b/src/dev/arm/hdlcd.cc
@@ -248,7 +248,7 @@ HDLcd::read(PacketPtr pkt)
     const uint32_t data(readReg(daddr));
     DPRINTF(HDLcd, "read register 0x%04x: 0x%x\n", daddr, data);
 
-    pkt->set<uint32_t>(data);
+    pkt->setLE<uint32_t>(data);
     pkt->makeAtomicResponse();
     return pioDelay;
 }
@@ -264,7 +264,7 @@ HDLcd::write(PacketPtr pkt)
     panic_if(pkt->getSize() != 4,
              "Unhandled read size (address: 0x.4x, size: %u)",
              daddr, pkt->getSize());
-    const uint32_t data(pkt->get<uint32_t>());
+    const uint32_t data(pkt->getLE<uint32_t>());
     DPRINTF(HDLcd, "write register 0x%04x: 0x%x\n", daddr, data);
 
     writeReg(daddr, data);

diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 8055afe2e21232b42b8b56b6ebccf20af34f1c7c..3cb598d68918129ed0c80ebac5b4db7ad10be2b0 100644 (file)
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -98,7 +98,7 @@ Pl050::read(PacketPtr pkt)
       default:
         if (readId(pkt, ambaId, pioAddr)) {
             // Hack for variable size accesses
-            data = pkt->get<uint32_t>();
+            data = pkt->getLE<uint32_t>();
             break;
         }
 

diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index 5ca9f608739d0e0be05f7563ba965535ade31adf..fe73d9674926297436c1daedb68eb4be2932372c 100644 (file)
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -136,7 +136,7 @@ Pl011::read(PacketPtr pkt)
       default:
         if (readId(pkt, AMBA_ID, pioAddr)) {
             // Hack for variable size accesses
-            data = pkt->get<uint32_t>();
+            data = pkt->getLE<uint32_t>();
             break;
         }
 
@@ -146,13 +146,13 @@ Pl011::read(PacketPtr pkt)
 
     switch(pkt->getSize()) {
       case 1:
-        pkt->set<uint8_t>(data);
+        pkt->setLE<uint8_t>(data);
         break;
       case 2:
-        pkt->set<uint16_t>(data);
+        pkt->setLE<uint16_t>(data);
         break;
       case 4:
-        pkt->set<uint32_t>(data);
+        pkt->setLE<uint32_t>(data);
         break;
       default:
         panic("Uart read size too big?\n");
@@ -173,7 +173,7 @@ Pl011::write(PacketPtr pkt)
     Addr daddr = pkt->getAddr() - pioAddr;
 
     DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
-            pkt->get<uint8_t>(), pkt->getSize());
+            pkt->getLE<uint8_t>(), pkt->getSize());
 
     // use a temporary data since the uart registers are read/written with
     // different size operations
@@ -182,13 +182,13 @@ Pl011::write(PacketPtr pkt)
 
     switch(pkt->getSize()) {
       case 1:
-        data = pkt->get<uint8_t>();
+        data = pkt->getLE<uint8_t>();
         break;
       case 2:
-        data = pkt->get<uint16_t>();
+        data = pkt->getLE<uint16_t>();
         break;
       case 4:
-        data = pkt->get<uint32_t>();
+        data = pkt->getLE<uint32_t>();
         break;
       default:
         panic("Uart write size too big?\n");

diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 344eb0864b0a43ec0e582e9a9da5e6e602740fa9..7560ec4b95727aab9f4bcdf1032fd469406b8133 100644 (file)
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -185,7 +185,7 @@ Pl111::read(PacketPtr pkt)
       default:
         if (readId(pkt, AMBA_ID, pioAddr)) {
             // Hack for variable size accesses
-            data = pkt->get<uint32_t>();
+            data = pkt->getLE<uint32_t>();
             break;
         } else if (daddr >= CrsrImage && daddr <= 0xBFC) {
             // CURSOR IMAGE
@@ -208,13 +208,13 @@ Pl111::read(PacketPtr pkt)
 
     switch(pkt->getSize()) {
       case 1:
-        pkt->set<uint8_t>(data);
+        pkt->setLE<uint8_t>(data);
         break;
       case 2:
-        pkt->set<uint16_t>(data);
+        pkt->setLE<uint16_t>(data);
         break;
       case 4:
-        pkt->set<uint32_t>(data);
+        pkt->setLE<uint32_t>(data);
         break;
       default:
         panic("CLCD controller read size too big?\n");
@@ -236,13 +236,13 @@ Pl111::write(PacketPtr pkt)
 
     switch(pkt->getSize()) {
       case 1:
-        data = pkt->get<uint8_t>();
+        data = pkt->getLE<uint8_t>();
         break;
       case 2:
-        data = pkt->get<uint16_t>();
+        data = pkt->getLE<uint16_t>();
         break;
       case 4:
-        data = pkt->get<uint32_t>();
+        data = pkt->getLE<uint32_t>();
         break;
       default:
         panic("PL111 CLCD controller write size too big?\n");
@@ -255,7 +255,7 @@ Pl111::write(PacketPtr pkt)
     Addr daddr = pkt->getAddr() - pioAddr;
 
     DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr,
-            pkt->get<uint8_t>(), pkt->getSize());
+            pkt->getLE<uint8_t>(), pkt->getSize());
 
     switch (daddr) {
       case LcdTiming0:

diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index 5b6ce52888029c43c104f03743b92609d7e97cb4..9abb77629f13494417f48766731e6c5a04e9379a 100644 (file)
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -92,7 +92,7 @@ PL031::read(PacketPtr pkt)
       default:
         if (readId(pkt, ambaId, pioAddr)) {
             // Hack for variable sized access
-            data = pkt->get<uint32_t>();
+            data = pkt->getLE<uint32_t>();
             break;
         }
         panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
@@ -101,13 +101,13 @@ PL031::read(PacketPtr pkt)
 
     switch(pkt->getSize()) {
       case 1:
-        pkt->set<uint8_t>(data);
+        pkt->setLE<uint8_t>(data);
         break;
       case 2:
-        pkt->set<uint16_t>(data);
+        pkt->setLE<uint16_t>(data);
         break;
       case 4:
-        pkt->set<uint32_t>(data);
+        pkt->setLE<uint32_t>(data);
         break;
       default:
         panic("Uart read size too big?\n");
@@ -131,22 +131,22 @@ PL031::write(PacketPtr pkt)
       case DataReg:
         break;
       case MatchReg:
-        matchVal = pkt->get<uint32_t>();
+        matchVal = pkt->getLE<uint32_t>();
         resyncMatch();
         break;
       case LoadReg:
         lastWrittenTick = curTick();
-        timeVal = pkt->get<uint32_t>();
+        timeVal = pkt->getLE<uint32_t>();
         loadVal = timeVal;
         resyncMatch();
         break;
       case ControlReg:
         break; // Can't stop when started
       case IntMask:
-        maskInt = pkt->get<uint32_t>();
+        maskInt = pkt->getLE<uint32_t>();
         break;
       case IntClear:
-        if (pkt->get<uint32_t>()) {
+        if (pkt->getLE<uint32_t>()) {
             rawInt = false;
             pendingInt = false;
         }

diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 954be6597e0d8091c237b745f28a4f926fd1095c..9f9e51f09f6787d17742172b2be341398e5ede1c 100644 (file)
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -61,66 +61,66 @@ RealViewCtrl::read(PacketPtr pkt)
 
     switch(daddr) {
       case ProcId0:
-        pkt->set(params()->proc_id0);
+        pkt->setLE(params()->proc_id0);
         break;
       case ProcId1:
-        pkt->set(params()->proc_id1);
+        pkt->setLE(params()->proc_id1);
         break;
       case Clock24:
         Tick clk;
         clk = SimClock::Float::MHz * curTick() * 24;
-        pkt->set((uint32_t)(clk));
+        pkt->setLE((uint32_t)(clk));
         break;
       case Clock100:
         Tick clk100;
         clk100 = SimClock::Float::MHz * curTick() * 100;
-        pkt->set((uint32_t)(clk100));
+        pkt->setLE((uint32_t)(clk100));
         break;
       case Flash:
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
         break;
       case Clcd:
-        pkt->set<uint32_t>(0x00001F00);
+        pkt->setLE<uint32_t>(0x00001F00);
         break;
       case Osc0:
-        pkt->set<uint32_t>(0x00012C5C);
+        pkt->setLE<uint32_t>(0x00012C5C);
         break;
       case Osc1:
-        pkt->set<uint32_t>(0x00002CC0);
+        pkt->setLE<uint32_t>(0x00002CC0);
         break;
       case Osc2:
-        pkt->set<uint32_t>(0x00002C75);
+        pkt->setLE<uint32_t>(0x00002C75);
         break;
       case Osc3:
-        pkt->set<uint32_t>(0x00020211);
+        pkt->setLE<uint32_t>(0x00020211);
         break;
       case Osc4:
-        pkt->set<uint32_t>(0x00002C75);
+        pkt->setLE<uint32_t>(0x00002C75);
         break;
       case Lock:
-        pkt->set<uint32_t>(sysLock);
+        pkt->setLE<uint32_t>(sysLock);
         break;
       case Flags:
-        pkt->set<uint32_t>(flags);
+        pkt->setLE<uint32_t>(flags);
         break;
       case IdReg:
-        pkt->set<uint32_t>(params()->idreg);
+        pkt->setLE<uint32_t>(params()->idreg);
         break;
       case CfgStat:
-        pkt->set<uint32_t>(1);
+        pkt->setLE<uint32_t>(1);
         break;
       case CfgData:
-        pkt->set<uint32_t>(scData);
+        pkt->setLE<uint32_t>(scData);
         DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
         break;
       case CfgCtrl:
-        pkt->set<uint32_t>(0); // not busy
+        pkt->setLE<uint32_t>(0); // not busy
         DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
         break;
       default:
         warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
              daddr);
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
         break;
     }
     pkt->makeAtomicResponse();
@@ -144,26 +144,26 @@ RealViewCtrl::write(PacketPtr pkt)
       case Osc4:
         break;
       case Lock:
-        sysLock.lockVal = pkt->get<uint16_t>();
+        sysLock.lockVal = pkt->getLE<uint16_t>();
         break;
       case ResetCtl:
         // Ignore writes to reset control
         warn_once("Ignoring write to reset control\n");
         break;
       case Flags:
-        flags = pkt->get<uint32_t>();
+        flags = pkt->getLE<uint32_t>();
         break;
       case FlagsClr:
         flags = 0;
         break;
       case CfgData:
-        scData = pkt->get<uint32_t>();
+        scData = pkt->getLE<uint32_t>();
         break;
       case CfgCtrl: {
           // A request is being submitted to read/write the system control
           // registers.  See
           // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
-          CfgCtrlReg req = pkt->get<uint32_t>();
+          CfgCtrlReg req = pkt->getLE<uint32_t>();
           if (!req.start) {
               DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
                       req);
@@ -195,7 +195,7 @@ RealViewCtrl::write(PacketPtr pkt)
       case CfgStat:     // Weird to write this
       default:
         warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
-             daddr, pkt->get<uint32_t>());
+             daddr, pkt->getLE<uint32_t>());
         break;
     }
     pkt->makeAtomicResponse();

diff --git a/src/dev/arm/timer_a9global.cc b/src/dev/arm/timer_a9global.cc
index 742ed76cd12b30626061bfe2de7d368b89c5ed0a..1d4089f7fe2b4be386a5da3f3071a9de20b22791 100644 (file)
--- a/src/dev/arm/timer_a9global.cc
+++ b/src/dev/arm/timer_a9global.cc
@@ -94,19 +94,19 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr)
       case CounterRegLow32:
         time = getTimeCounterFromTicks(curTick());
         DPRINTF(Timer, "-- returning lower 32-bits of counter: %u\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case CounterRegHigh32:
         time = getTimeCounterFromTicks(curTick());
         time >>= 32;
         DPRINTF(Timer, "-- returning upper 32-bits of counter: %u\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case ControlReg:
-        pkt->set<uint32_t>(control);
+        pkt->setLE<uint32_t>(control);
         break;
       case IntStatusReg:
-        pkt->set<uint32_t>(rawInt);
+        pkt->setLE<uint32_t>(rawInt);
         break;
       case CmpValRegLow32:
         DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
@@ -117,7 +117,7 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr)
           time = 0;
         }
         DPRINTF(Timer, "-- returning lower 32-bits of comparator: %u\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case CmpValRegHigh32:
         DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
@@ -129,17 +129,17 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr)
           time = 0;
         }
         DPRINTF(Timer, "-- returning upper 32-bits of comparator: %u\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case AutoIncrementReg:
-        pkt->set<uint32_t>(autoIncValue);
+        pkt->setLE<uint32_t>(autoIncValue);
         break;
       default:
         panic("Tried to read A9GlobalTimer at offset %#x\n", daddr);
         break;
     }
     DPRINTF(Timer, "Reading %#x from A9GlobalTimer at offset: %#x\n",
-             pkt->get<uint32_t>(), daddr);
+             pkt->getLE<uint32_t>(), daddr);
 }
 
 Tick
@@ -165,7 +165,7 @@ void
 A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr)
 {
     DPRINTF(Timer, "Writing %#x to A9GlobalTimer at offset: %#x\n",
-            pkt->get<uint32_t>(), daddr);
+            pkt->getLE<uint32_t>(), daddr);
     switch (daddr) {
      case CounterRegLow32:
      case CounterRegHigh32:
@@ -176,7 +176,7 @@ A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr)
         bool old_cmpEnable;
         old_enable = control.enable;
         old_cmpEnable = control.cmpEnable;
-        control = pkt->get<uint32_t>();
+        control = pkt->getLE<uint32_t>();
         if ((old_enable == 0) && control.enable)
             restartCounter();
         if ((old_cmpEnable == 0) && control.cmpEnable)
@@ -193,14 +193,14 @@ A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr)
         break;
       case CmpValRegLow32:
         cmpVal &= 0xFFFFFFFF00000000ULL;
-        cmpVal |= (uint64_t)pkt->get<uint32_t>();
+        cmpVal |= (uint64_t)pkt->getLE<uint32_t>();
         break;
       case CmpValRegHigh32:
         cmpVal &= 0x00000000FFFFFFFFULL;
-        cmpVal |= ((uint64_t)pkt->get<uint32_t>() << 32);
+        cmpVal |= ((uint64_t)pkt->getLE<uint32_t>() << 32);
         break;
       case AutoIncrementReg:
-        autoIncValue = pkt->get<uint32_t>();
+        autoIncValue = pkt->getLE<uint32_t>();
         break;
       default:
         panic("Tried to write A9GlobalTimer at offset %#x\n", daddr);

diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc
index 9e9946b1f4146d3a2594a8f5c9ec8ee8f2312a1f..a0825232f1b9be11bf8c7bfe40c50ab2abdfa0ad 100644 (file)
--- a/src/dev/arm/timer_cpulocal.cc
+++ b/src/dev/arm/timer_cpulocal.cc
@@ -116,7 +116,7 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
 
     switch(daddr) {
       case TimerLoadReg:
-        pkt->set<uint32_t>(timerLoadValue);
+        pkt->setLE<uint32_t>(timerLoadValue);
         break;
       case TimerCounterReg:
         DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n",
@@ -126,16 +126,16 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
         time = time / parent->clockPeriod() /
             power(16, timerControl.prescalar);
         DPRINTF(Timer, "-- returning counter at %d\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case TimerControlReg:
-        pkt->set<uint32_t>(timerControl);
+        pkt->setLE<uint32_t>(timerControl);
         break;
       case TimerIntStatusReg:
-        pkt->set<uint32_t>(rawIntTimer);
+        pkt->setLE<uint32_t>(rawIntTimer);
         break;
       case WatchdogLoadReg:
-        pkt->set<uint32_t>(watchdogLoadValue);
+        pkt->setLE<uint32_t>(watchdogLoadValue);
         break;
       case WatchdogCounterReg:
         DPRINTF(Timer,
@@ -146,16 +146,16 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
         time = time / parent->clockPeriod() /
             power(16, watchdogControl.prescalar);
         DPRINTF(Timer, "-- returning counter at %d\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case WatchdogControlReg:
-        pkt->set<uint32_t>(watchdogControl);
+        pkt->setLE<uint32_t>(watchdogControl);
         break;
       case WatchdogIntStatusReg:
-        pkt->set<uint32_t>(rawIntWatchdog);
+        pkt->setLE<uint32_t>(rawIntWatchdog);
         break;
       case WatchdogResetStatusReg:
-        pkt->set<uint32_t>(rawResetWatchdog);
+        pkt->setLE<uint32_t>(rawResetWatchdog);
         break;
       case WatchdogDisableReg:
         panic("Tried to read from WatchdogDisableRegister\n");
@@ -197,16 +197,16 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
       case TimerLoadReg:
         // Writing to this register also resets the counter register and
         // starts decrementing if the counter is enabled.
-        timerLoadValue = pkt->get<uint32_t>();
+        timerLoadValue = pkt->getLE<uint32_t>();
         restartTimerCounter(timerLoadValue);
         break;
       case TimerCounterReg:
         // Can be written, doesn't start counting unless the timer is enabled
-        restartTimerCounter(pkt->get<uint32_t>());
+        restartTimerCounter(pkt->getLE<uint32_t>());
         break;
       case TimerControlReg:
         old_enable = timerControl.enable;
-        timerControl = pkt->get<uint32_t>();
+        timerControl = pkt->getLE<uint32_t>();
         if ((old_enable == 0) && timerControl.enable)
             restartTimerCounter(timerLoadValue);
         break;
@@ -218,19 +218,19 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
         }
         break;
       case WatchdogLoadReg:
-        watchdogLoadValue = pkt->get<uint32_t>();
+        watchdogLoadValue = pkt->getLE<uint32_t>();
         restartWatchdogCounter(watchdogLoadValue);
         break;
       case WatchdogCounterReg:
         // Can't be written when in watchdog mode, but can in timer mode
         if (!watchdogControl.watchdogMode) {
-            restartWatchdogCounter(pkt->get<uint32_t>());
+            restartWatchdogCounter(pkt->getLE<uint32_t>());
         }
         break;
       case WatchdogControlReg:
         old_enable = watchdogControl.enable;
         old_wd_mode = watchdogControl.watchdogMode;
-        watchdogControl = pkt->get<uint32_t>();
+        watchdogControl = pkt->getLE<uint32_t>();
         if ((old_enable == 0) && watchdogControl.enable)
             restartWatchdogCounter(watchdogLoadValue);
         // cannot disable watchdog using control register
@@ -250,7 +250,7 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
         break;
       case WatchdogDisableReg:
         old_val = watchdogDisableReg;
-        watchdogDisableReg = pkt->get<uint32_t>();
+        watchdogDisableReg = pkt->getLE<uint32_t>();
         // if this sequence is observed, turn off watchdog mode
         if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321)
             watchdogControl.watchdogMode = 0;

diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc
index f28ba7bf036969d68cf235ec3da8afe086c01d62..0549c6318bb84ef77c1ce43c85091f5dc62bd1a7 100644 (file)
--- a/src/dev/arm/timer_sp804.cc
+++ b/src/dev/arm/timer_sp804.cc
@@ -86,7 +86,7 @@ Sp804::Timer::read(PacketPtr pkt, Addr daddr)
 {
     switch(daddr) {
       case LoadReg:
-        pkt->set<uint32_t>(loadValue);
+        pkt->setLE<uint32_t>(loadValue);
         break;
       case CurrentReg:
         DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
@@ -95,25 +95,26 @@ Sp804::Timer::read(PacketPtr pkt, Addr daddr)
         time = zeroEvent.when() - curTick();
         time = time / clock / power(16, control.timerPrescale);
         DPRINTF(Timer, "-- returning counter at %d\n", time);
-        pkt->set<uint32_t>(time);
+        pkt->setLE<uint32_t>(time);
         break;
       case ControlReg:
-        pkt->set<uint32_t>(control);
+        pkt->setLE<uint32_t>(control);
         break;
       case RawISR:
-        pkt->set<uint32_t>(rawInt);
+        pkt->setLE<uint32_t>(rawInt);
         break;
       case MaskedISR:
-        pkt->set<uint32_t>(pendingInt);
+        pkt->setLE<uint32_t>(pendingInt);
         break;
       case BGLoad:
-        pkt->set<uint32_t>(loadValue);
+        pkt->setLE<uint32_t>(loadValue);
         break;
       default:
         panic("Tried to read SP804 timer at offset %#x\n", daddr);
         break;
     }
-    DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
+    DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n",
+            pkt->getLE<uint32_t>(), daddr);
 }
 
 Tick
@@ -137,10 +138,11 @@ Sp804::write(PacketPtr pkt)
 void
 Sp804::Timer::write(PacketPtr pkt, Addr daddr)
 {
-    DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
+    DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n",
+            pkt->getLE<uint32_t>(), daddr);
     switch (daddr) {
       case LoadReg:
-        loadValue = pkt->get<uint32_t>();
+        loadValue = pkt->getLE<uint32_t>();
         restartCounter(loadValue);
         break;
       case CurrentReg:
@@ -149,7 +151,7 @@ Sp804::Timer::write(PacketPtr pkt, Addr daddr)
       case ControlReg:
         bool old_enable;
         old_enable = control.timerEnable;
-        control = pkt->get<uint32_t>();
+        control = pkt->getLE<uint32_t>();
         if ((old_enable == 0) && control.timerEnable)
             restartCounter(loadValue);
         break;
@@ -162,7 +164,7 @@ Sp804::Timer::write(PacketPtr pkt, Addr daddr)
         }
         break;
       case BGLoad:
-        loadValue = pkt->get<uint32_t>();
+        loadValue = pkt->getLE<uint32_t>();
         break;
       default:
         panic("Tried to write SP804 timer at offset %#x\n", daddr);

diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 137ad8c2750fa2cbfc60a9605a8f39212a164682..cc28000724cf40015079fcbf821ede2f3292993b 100644 (file)
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -1053,7 +1053,7 @@ UFSHostDevice::read(PacketPtr pkt)
         break;
     }
 
-    pkt->set<uint32_t>(data);
+    pkt->setLE<uint32_t>(data);
     pkt->makeResponse();
     return pioDelay;
 }
@@ -1071,15 +1071,15 @@ UFSHostDevice::write(PacketPtr pkt)
     switch (pkt->getSize()) {
 
       case 1:
-        data = pkt->get<uint8_t>();
+        data = pkt->getLE<uint8_t>();
         break;
 
       case 2:
-        data = pkt->get<uint16_t>();
+        data = pkt->getLE<uint16_t>();
         break;
 
       case 4:
-        data = pkt->get<uint32_t>();
+        data = pkt->getLE<uint32_t>();
         break;
 
       default:

diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 52952040392d4d8a17b3558d226e179377d7a511..3e295828ced6c7cd1b1018d34ab63d6194bbf060 100644 (file)
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -106,16 +106,16 @@ VGic::readVCpu(PacketPtr pkt)
 
     switch (daddr) {
       case GICV_CTLR:
-        pkt->set<uint32_t>(vid->vctrl);
+        pkt->setLE<uint32_t>(vid->vctrl);
         break;
       case GICV_IAR: {
           int i = findHighestPendingLR(vid);
           if (i < 0 || !vid->vctrl.En) {
-              pkt->set<uint32_t>(1023); // "No int" marker
+              pkt->setLE<uint32_t>(1023); // "No int" marker
           } else {
               ListReg *lr = &vid->LR[i];
 
-              pkt->set<uint32_t>(lr->VirtualID |
+              pkt->setLE<uint32_t>(lr->VirtualID |
                                  (((int)lr->CpuID) << 10));
               // We don't support auto-EOI of HW interrupts via real GIC!
               // Fortunately, KVM doesn't use this.  How about Xen...? Ulp!
@@ -160,15 +160,15 @@ VGic::readCtrl(PacketPtr pkt)
 
     switch (daddr) {
       case GICH_HCR:
-        pkt->set<uint32_t>(vid->hcr);
+        pkt->setLE<uint32_t>(vid->hcr);
         break;
 
       case GICH_VTR:
-        pkt->set<uint32_t>(0x44000000 | (NUM_LR - 1));
+        pkt->setLE<uint32_t>(0x44000000 | (NUM_LR - 1));
         break;
 
       case GICH_VMCR:
-        pkt->set<uint32_t>(
+        pkt->setLE<uint32_t>(
             ((uint32_t)vid->VMPriMask << 27) |
             ((uint32_t)vid->VMBP << 21) |
             ((uint32_t)vid->VMABP << 18) |
@@ -182,15 +182,15 @@ VGic::readCtrl(PacketPtr pkt)
         break;
 
       case GICH_MISR:
-        pkt->set<uint32_t>(getMISR(vid));
+        pkt->setLE<uint32_t>(getMISR(vid));
         break;
 
       case GICH_EISR0:
-        pkt->set<uint32_t>(vid->eisr & 0xffffffff);
+        pkt->setLE<uint32_t>(vid->eisr & 0xffffffff);
         break;
 
       case GICH_EISR1:
-        pkt->set<uint32_t>(vid->eisr >> 32);
+        pkt->setLE<uint32_t>(vid->eisr >> 32);
         break;
 
       case GICH_ELSR0: {
@@ -199,7 +199,7 @@ VGic::readCtrl(PacketPtr pkt)
               if (!vid->LR[i].State)
                   bm |= 1 << i;
           }
-          pkt->set<uint32_t>(bm);
+          pkt->setLE<uint32_t>(bm);
       } break;
 
       case GICH_ELSR1: {
@@ -208,19 +208,19 @@ VGic::readCtrl(PacketPtr pkt)
               if (!vid->LR[i].State)
                   bm |= 1 << (i-32);
           }
-          pkt->set<uint32_t>(bm);
+          pkt->setLE<uint32_t>(bm);
       } break;
 
       case GICH_APR0:
         warn_once("VGIC GICH_APR read!\n");
-        pkt->set<uint32_t>(0);
+        pkt->setLE<uint32_t>(0);
         break;
 
       case GICH_LR0:
       case GICH_LR1:
       case GICH_LR2:
       case GICH_LR3:
-        pkt->set<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]);
+        pkt->setLE<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]);
         break;
 
       default:
@@ -240,20 +240,21 @@ VGic::writeVCpu(PacketPtr pkt)
     assert(ctx_id < VGIC_CPU_MAX);
     struct vcpuIntData *vid = &vcpuData[ctx_id];
 
-    DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
+    DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n",
+            daddr, pkt->getLE<uint32_t>());
 
     switch (daddr) {
       case GICV_CTLR:
-        vid->vctrl = pkt->get<uint32_t>();
+        vid->vctrl = pkt->getLE<uint32_t>();
         break;
       case GICV_PMR:
-        vid->VMPriMask = pkt->get<uint32_t>();
+        vid->VMPriMask = pkt->getLE<uint32_t>();
         break;
       case GICV_EOIR: {
           // We don't handle the split EOI-then-DIR mode.  Linux (guest)
           // doesn't need it though.
           assert(!vid->vctrl.EOImode);
-          uint32_t w = pkt->get<uint32_t>();
+          uint32_t w = pkt->getLE<uint32_t>();
           unsigned int virq = w & 0x3ff;
           unsigned int vcpu = (w >> 10) & 7;
           int i = findLRForVIRQ(vid, virq, vcpu);
@@ -268,7 +269,8 @@ VGic::writeVCpu(PacketPtr pkt)
           }
       } break;
       default:
-        panic("VGIC VCPU write %#x to unk address %#x\n", pkt->get<uint32_t>(), daddr);
+        panic("VGIC VCPU write %#x to unk address %#x\n",
+                pkt->getLE<uint32_t>(), daddr);
     }
 
     // This updates the EISRs and flags IRQs:
@@ -285,7 +287,8 @@ VGic::writeCtrl(PacketPtr pkt)
 
     ContextID ctx_id = pkt->req->contextId();
 
-    DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
+    DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n",
+            daddr, pkt->getLE<uint32_t>());
 
     /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
      * Anything > that is 0x200-sized slices of 'per CPU' regs.
@@ -301,12 +304,12 @@ VGic::writeCtrl(PacketPtr pkt)
 
     switch (daddr) {
       case GICH_HCR:
-        vid->hcr = pkt->get<uint32_t>();
+        vid->hcr = pkt->getLE<uint32_t>();
         // update int state
         break;
 
       case GICH_VMCR: {
-          uint32_t d = pkt->get<uint32_t>();
+          uint32_t d = pkt->getLE<uint32_t>();
           vid->VMPriMask = d >> 27;
           vid->VMBP = (d >> 21) & 7;
           vid->VMABP = (d >> 18) & 7;
@@ -326,7 +329,7 @@ VGic::writeCtrl(PacketPtr pkt)
       case GICH_LR1:
       case GICH_LR2:
       case GICH_LR3:
-        vid->LR[(daddr - GICH_LR0) >> 2] = pkt->get<uint32_t>();
+        vid->LR[(daddr - GICH_LR0) >> 2] = pkt->getLE<uint32_t>();
         // update int state
         break;
 

diff --git a/src/dev/arm/vio_mmio.cc b/src/dev/arm/vio_mmio.cc
index 9f7bf1333eadfcfb62a93d1809f7b23bd00f43f5..b9ecce918da7f055ce1133d89ee2c13ff4c2345a 100644 (file)
--- a/src/dev/arm/vio_mmio.cc
+++ b/src/dev/arm/vio_mmio.cc
@@ -79,7 +79,7 @@ MmioVirtIO::read(PacketPtr pkt)
     const uint32_t value = read(offset);
     DPRINTF(VIOIface, "    value: 0x%x\n", value);
     pkt->makeResponse();
-    pkt->set<uint32_t>(value);
+    pkt->setLE<uint32_t>(value);
 
     return 0;
 }
@@ -173,9 +173,9 @@ MmioVirtIO::write(PacketPtr pkt)
     }
 
     panic_if(size != 4, "Unexpected write size @ 0x%x: %u\n", offset, size);
-    DPRINTF(VIOIface, "    value: 0x%x\n", pkt->get<uint32_t>());
+    DPRINTF(VIOIface, "    value: 0x%x\n", pkt->getLE<uint32_t>());
     pkt->makeResponse();
-    write(offset, pkt->get<uint32_t>());
+    write(offset, pkt->getLE<uint32_t>());
     return 0;
 }