sdram: remove nbits from modules and databits from GeomSettings

diff --git a/misoclib/mem/sdram/__init__.py b/misoclib/mem/sdram/__init__.py
index 4f7cf782e5cd1cf4e2628cc21408cbb89ef84641..c80205a605531e47e4fa69c553d9a5f3645129c6 100644 (file)
--- a/misoclib/mem/sdram/__init__.py
+++ b/misoclib/mem/sdram/__init__.py
@@ -4,8 +4,8 @@ PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase w
 def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
        return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
 
-GeomSettingsT = namedtuple("_GeomSettings", "databits bankbits rowbits colbits addressbits")
-def GeomSettings(databits, bankbits, rowbits, colbits):
-       return GeomSettingsT(databits, bankbits, rowbits, colbits, max(rowbits, colbits))
+GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
+def GeomSettings(bankbits, rowbits, colbits):
+       return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))
 
 TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index ccdc9fcb30c26f95cb1db5ac03a4f46710144b93..d946038774380f6f2191fb6f06fc6a366b5e9613 100644 (file)
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -25,7 +25,6 @@ class SDRAMModule:
                self.clk_freq = clk_freq
                self.memtype = memtype
                self.geom_settings = sdram.GeomSettings(
-                       databits=geom_settings["nbits"],
                        bankbits=log2_int(geom_settings["nbanks"]),
                        rowbits=log2_int(geom_settings["nrows"]),
                        colbits=log2_int(geom_settings["ncols"]),
@@ -48,7 +47,6 @@ class SDRAMModule:
 # SDR
 class IS42S16160(SDRAMModule):
        geom_settings = {
-               "nbits":        16,
                "nbanks":       4,
                "nrows":        8192,
                "ncols":        512
@@ -68,7 +66,6 @@ class IS42S16160(SDRAMModule):
 
 class MT48LC4M16(SDRAMModule):
        geom_settings = {
-               "nbits":        16,
                "nbanks":       4,
                "nrows":        4096,
                "ncols":        256
@@ -87,7 +84,6 @@ class MT48LC4M16(SDRAMModule):
 
 class AS4C16M16(SDRAMModule):
        geom_settings = {
-               "nbits":        16,
                "nbanks":       4,
                "nrows":        8192,
                "ncols":        512
@@ -108,7 +104,6 @@ class AS4C16M16(SDRAMModule):
 # DDR
 class MT46V32M16(SDRAMModule):
        geom_settings = {
-               "nbits":        16,
                "nbanks":       4,
                "nrows":        8192,
                "ncols":        1024
@@ -128,7 +123,6 @@ class MT46V32M16(SDRAMModule):
 # LPDDR
 class MT46H32M16(SDRAMModule):
        geom_settings = {
-               "nbits":        16,
                "nbanks":       4,
                "nrows":        8192,
                "ncols":        1024
@@ -148,7 +142,6 @@ class MT46H32M16(SDRAMModule):
 # DDR2
 class MT47H128M8(SDRAMModule):
        geom_settings = {
-               "nbits":        8,
                "nbanks":       8,
                "nrows":        16384,
                "ncols":        1024
@@ -168,7 +161,6 @@ class MT47H128M8(SDRAMModule):
 # DDR3
 class MT8JTF12864(SDRAMModule):
        geom_settings = {
-               "nbits":        8,
                "nbanks":       8,
                "nrows":        65536,
                "ncols":        1024

diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
index 31886b4c8e61781ef5e6663c721a01099d8620e2..52342c5c7c10f0b0cd0bfeaaf6db03e5260af5a7 100644 (file)
--- a/misoclib/mem/sdram/phy/simphy.py
+++ b/misoclib/mem/sdram/phy/simphy.py
@@ -87,9 +87,8 @@ class DFIPhase(Module):
                ]
 
 class SDRAMPHYSim(Module):
-       def __init__(self, module, nmodules=1):
+       def __init__(self, module, data_width):
                addressbits = module.geom_settings.addressbits
-               databits = module.geom_settings.databits
                bankbits = module.geom_settings.bankbits
                rowbits = module.geom_settings.rowbits
                colbits = module.geom_settings.colbits
@@ -97,7 +96,7 @@ class SDRAMPHYSim(Module):
                # XXX expose this to user
                self.settings = sdram.PhySettings(
                        memtype=module.memtype,
-                       dfi_databits=databits,
+                       dfi_databits=data_width,
                        nphases=1,
                        rdphase=0,
                        wrphase=0,
@@ -109,13 +108,12 @@ class SDRAMPHYSim(Module):
                )
                self.module = module
 
-               self.dfi = Interface(addressbits, bankbits, databits)
+               self.dfi = Interface(addressbits, bankbits, data_width)
 
                ###
                nbanks = 2**bankbits
                nrows = 2**rowbits
                ncols = 2**colbits
-               data_width = databits*nmodules
 
                # DFI phases
                phases = [DFIPhase(self.dfi, n) for n in range(self.settings.nphases)]