instruction['writes'].difference_update(writes_possible)
return stall
+ def is_idle(self):
+ return len(self.stages) == 0
+
class Fetch:
"""
self.stages[0] = insn_trace
return stall
+ def is_idle(self):
+ return self.stages[0] is None
+
class Decode:
"""
self.cpu.issue.add_instruction(insn, writeregs)
return stall
+ def is_idle(self):
+ return True
+
+
class Issue:
"""
Issue phase: if not stalled will place the instruction into execute.
self.cpu.exe.add_instruction(insn, writeregs)
return stall
+ def is_idle(self):
+ return True
+
class CPU:
"""
self.curr_clk += 1
#print("---------------")
+ def is_idle(self):
+ return (self.fetch.is_idle() and
+ self.decode.is_idle() and
+ self.issue.is_idle() and
+ self.exe.is_idle())
+
# TODO: Make formatting prettier, and conform to markdown table format
# TODO: Adjust based on actual number of pipeline stages.
def print_headings(self):
for trace in lines:
#print(trace)
basic_cpu.process_instructions(trace)
+ # wait for all instructions to finish
+ while not basic_cpu.is_idle():
+ basic_cpu.process_instructions(None)
def test_trace1(self): # TODO, assert this is valid
basic_cpu = CPU()
for trace in lines:
#print(trace)
basic_cpu.process_instructions(trace)
+ # wait for all instructions to finish
+ while not basic_cpu.is_idle():
+ basic_cpu.process_instructions(None)
+
def help():
print ("-t runs unit tests")