isa/test_runner.py: generate unique trace files

diff --git a/src/openpower/decoder/isa/test_runner.py b/src/openpower/decoder/isa/test_runner.py
index b84354cc099cfba908629b9c17b903990fc79388..828802389ca227a96339645d947a868a530cfc6c 100644 (file)
--- a/src/openpower/decoder/isa/test_runner.py
+++ b/src/openpower/decoder/isa/test_runner.py
@@ -1,3 +1,6 @@
+import tempfile
+import itertools
+import os
 from nmigen import Module, Signal
 from nmigen.sim import Simulator, Settle
 from openpower.decoder.isa.caller import ISACaller
@@ -8,6 +11,24 @@ from openpower.decoder.isa.caller import ISACaller, inject
 from openpower.decoder.isa.all import ISA
 from openpower.test.state import TestState
 from nmutil.formaltest import FHDLTestCase
+from nmutil.get_test_path import RunCounter
+from openpower.util import log
+
+
+global_run_counter = itertools.count()
+def get_temp_tracefile(test_case=None):
+    if test_case is None:
+        prefix = ("trace_test" + str(next(global_run_counter)) + "_")
+    else:
+        counter = str(RunCounter.get(test_case).next(test_case.id()))
+        prefix = ("trace_subtest" + counter + "_")
+    suffix = ".trace"
+    keep = bool(os.environ.get("TRACEFILE", ""))
+    tracefile = tempfile.NamedTemporaryFile(mode="w", encoding="UTF-8",
+        prefix=prefix, suffix=suffix, delete=not keep)
+    log("tracefile", tracefile.name,
+        ("(permanent)" if keep else "(transient)"))
+    return tracefile
 
 
 class Register:
@@ -43,6 +64,8 @@ class ISATestRunner(FHDLTestCase):
                     insncode = generator.assembly.splitlines()
                     instructions = list(zip(gen, insncode))
 
+                    tracefile = get_temp_tracefile(test)
+
                     simulator = ISA(pdecode2, test.regs,
                                     test.sprs,
                                     test.cr,
@@ -52,7 +75,8 @@ class ISATestRunner(FHDLTestCase):
                                     fpregfile=None,
                                     disassembly=insncode,
                                     bigendian=0,
-                                    mmu=False)
+                                    mmu=False,
+                                    tracefile=tracefile)
 
                     print ("GPRs")
                     simulator.gpr.dump()
@@ -114,6 +138,8 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
     insncode = generator.assembly.splitlines()
     instructions = list(zip(gen, insncode))
 
+    tracefile = get_temp_tracefile()
+
     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
                     initial_insns=gen, respect_pc=True,
                     initial_svstate=svstate,
@@ -121,7 +147,8 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
                     fpregfile=initial_fprs,
                     disassembly=insncode,
                     bigendian=0,
-                    mmu=mmu)
+                    mmu=mmu,
+                    tracefile=tracefile)
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
     sim = Simulator(m)