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diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index bd5fd6bf53189b5ac8665af9d1e51480975b7bb7..7055026b73f4284f242b2fe9356206799fcd0938 100644 (file)
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -35,7 +35,7 @@ RISC-V is the largest open-source global community for microprocessor architectu
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
+A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
 they include recently:
 
 * <https://libre-soc.org/nlnet_2022_opf_isa_wg/> - improving SVP64
@@ -51,47 +51,33 @@ EUR 100,000.
 
 # Explain what the requested budget will be used for? 
 
-* Assessment of the missing RISC-V instructions (only 96 where
-  Power ISA SFFS is 214) which are present in Power ISA 3.0
-* Implementation of the missing RISC-V instructions that bring
-  it up to par with Power ISA, in the Scalar ISA space.
-* Assessment of application of Simple-V Vector Prefixing to SVP64,
-  modernising the work already done four years ago under
-  NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
-* Implementing Simple-V in the Libre-SOC Simulator, ISACaller.
-* Assembler and disassembler of RISC-V instructions and also
-  SVP64 in the Libre-SOC infrastructure.
-* Upgrading sv-spike which was completed four years ago with
-  an early prototype Simple-V Specification
+
+Key phases of this project are:
+* Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0
+* Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space.
+* Assessment of application of Simple-V Vector Prefixing to SVP64, building on the work already done under NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
+* Implementation of Simple-V in the Libre-SOC Simulator, ISACaller.
+* Assembler and disassembler of RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
+* Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification:
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>
-* Adding a large comprehensive unit test base for the new instructions
-  which can then be tested against sv-spike as well as ISACaller.
-  Many of these were already written four years ago and need conversion
-  to the new format used in Libre-SOC
+* Adding a comprehensive unit test base for the new instructions which can then be tested against sv-spike as well as ISACaller. Conversion of previously created instructions to the new format used in Libre-SOC, and adding the newly defined and created instructions.
   <https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
-* Documentation, demonstrations and Conference Papers. Also many
-  of the other projects (cryptoprimitives, video) will need porting
-  of the Power ISA SVP64 Assembler to SimpleV-RISCV.
-* Research and assessment of ARM7 and i486 (both on opencores.org)
-  as to their feasibility for applying Simple-V Prefixing
+* Documentation, demonstrations and Conference Papers. This will include porting results of other completed projects (cryptoprimitives, video) from POWER ISA to the RISC-V/Simple-V/SVP64 environment
+* Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects
 
 
 # Does the project have other funding sources, both past and present?
 
-NGI Search, NGI POINTER, and NLnet Grants is the sole source of funding
-for this project, over the past five years. Four grants are at stages
-of completion at the time of writing (two nearing end).
+NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding
+for this development programme over the past five years, and for the project in this application. Four grants are at stages of completion at the time of writing (two nearing end).
 
 # Compare your own project with existing or historical efforts.
 
 ## What are significant technical challenges you expect to solve during the project, if any?
 
-Given that two ISAs have been Vectorised using Simple-V already, this
-project is relatively straightforward but horrendously detailed and
-comprehensive, requiring meticulous attention to detail and a very
-high standard of Project Management. This is a sustained standard
-and practices developed already over a five year period that will
-continue to be rigorously applied.
+The key technical challenge in this project is the creation of special SVP64 instructions that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. 
+
+Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
 
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?