Ensure \A_SIGNED is never used with $shiftx

It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d7d2269422b8a2bb3addc5145fd5ce34560d9976..c56f0dcabe0338b91cc308e1958756ef2053afe9 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1035,7 +1035,11 @@ namespace {
                        }
 
                        if (cell->type.in(ID($shift), ID($shiftx))) {
-                               param_bool(ID::A_SIGNED);
+                               if (cell->type == ID($shiftx)) {
+                                       param_bool(ID::A_SIGNED, /*expected=*/false);
+                               } else {
+                                       param_bool(ID::A_SIGNED);
+                               }
                                param_bool(ID::B_SIGNED);
                                port(ID::A, param(ID::A_WIDTH));
                                port(ID::B, param(ID::B_WIDTH));

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index bdb475d3b3501fd872ff45b16bd757e9952d3ca1..228b6b67afe6f284f9d22a2186252bee468c0fc1 100644 (file)
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
                cell->setPort(ID::Y, wire);
        }
 
+       if (cell_type.in(ID($shiftx))) {
+               cell->parameters[ID::A_SIGNED] = false;
+       }
+
        if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
                cell->parameters[ID::B_SIGNED] = false;
        }