Pattern matcher to check pool of bits, not exactly

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index a4602dd63a8d844136c71bb0336d25ab9b5cdafb..bd04cc40b46e24091c5b20aab416aad31d72e224 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -49,8 +49,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                cell->setPort("\\CLK", st.clock);
 
                if (st.ffA) {
+                       SigSpec A = cell->getPort("\\A");
                        SigSpec D = st.ffA->getPort("\\D");
-                       cell->setPort("\\A", D.extend_u0(30, true));
+                       SigSpec Q = st.ffA->getPort("\\Q");
+                       A.replace(Q, D);
+                       cell->setPort("\\A", A);
                        cell->setParam("\\AREG", State::S1);
                        if (st.ffA->type == "$dff")
                                cell->setPort("\\CEA2", State::S1);
@@ -59,8 +62,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                        else log_abort();
                }
                if (st.ffB) {
+                       SigSpec B = cell->getPort("\\B");
                        SigSpec D = st.ffB->getPort("\\D");
-                       cell->setPort("\\B", D.extend_u0(18, true));
+                       SigSpec Q = st.ffB->getPort("\\Q");
+                       B.replace(Q, D);
+                       cell->setPort("\\B", B);
                        cell->setParam("\\BREG", State::S1);
                        if (st.ffB->type == "$dff")
                                cell->setPort("\\CEB2", State::S1);
@@ -71,7 +77,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                if (st.ffP) {
                        SigSpec P = cell->getPort("\\P");
                        SigSpec Q = st.ffP->getPort("\\Q");
-                       Q.append(P.extract(GetSize(Q), -1));
+                       P.replace(Q, P.extract(0, GetSize(Q)));
                        cell->setPort("\\P", Q);
                        cell->setParam("\\PREG", State::S1);
                        if (st.ffP->type == "$dff")

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 4b7bea30862c94f016c04de1632bce436f91e549..60e972615a73aebbc78c39794679e3f30f03b16c 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -11,7 +11,7 @@ match ffA
        select ffA->type.in($dff, $dffe)
        select param(ffA, \CLK_POLARITY).as_bool()
        // select nusers(port(ffA, \Q)) == 2
-       index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25)
+       index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
        // DSP48E1 does not support clock inversion
        optional
 endmatch
@@ -25,7 +25,7 @@ match ffB
        select ffB->type.in($dff, $dffe)
        select param(ffB, \CLK_POLARITY).as_bool()
        // select nusers(port(ffB, \Q)) == 2
-       index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B)
+       index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
        optional
 endmatch