{
pc->emit[0] = 0xd0000000;
- if (SFILE(i, 0) == NV_FILE_IMM) {
+ if (SFILE(i, 1) == NV_FILE_IMM) {
emit_form_IMM(pc, i, 0);
if (i->opcode == NV_OP_OR)
pc->emit[0] = 0x00000001;
pc->emit[1] = 0xc0000000;
- set_dst(pc, i->def[0]);
+ pc->emit[0] |= (i->def[0]->reg.id + 1) << 2;
set_pred(pc, i);
set_src_0(pc, i->src[0]);
pc->emit[0] |= (get_immd_u32(i->src[1]) & 0x3f) << 16;
return;
assert(src0 && src1);
- if (src1->value->reg.file == NV_FILE_IMM) {
- /* should only be present from folding a constant MUL part of a MAD */
- assert(nvi->opcode == NV_OP_ADD);
+ if (src1->value->reg.file == NV_FILE_IMM)
return;
- }
if (is_cmem_load(src0->value->insn)) {
if (!is_cmem_load(src1->value->insn)) {
continue;
nvi = sti->src[0]->value->insn;
- if (!nvi || nvi->opcode == NV_OP_PHI)
+ if (!nvi || nvi->opcode == NV_OP_PHI || nv_is_vector_op(nvi->opcode))
continue;
assert(nvi->def[0] == sti->src[0]->value);
break;
case NV_OP_SUB:
switch (type) {
- case NV_TYPE_F32: u.f32 = u0.f32 - u1.f32;
- case NV_TYPE_U32: u.u32 = u0.u32 - u1.u32;
- case NV_TYPE_S32: u.s32 = u0.s32 - u1.s32;
+ case NV_TYPE_F32: u.f32 = u0.f32 - u1.f32; break;
+ case NV_TYPE_U32: u.u32 = u0.u32 - u1.u32; break;
+ case NV_TYPE_S32: u.s32 = u0.s32 - u1.s32; break;
default:
assert(0);
break;
if (insn->Dst[0].Register.WriteMask & 0x8)
dst0[3] = bld_imm_f32(bld, 1.0f);
break;
+ case TGSI_OPCODE_SSG:
+ FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
+ src0 = emit_fetch(bld, insn, 0, c);
+ src1 = bld_predicate(bld, src0, FALSE);
+ temp = bld_insn_2(bld, NV_OP_AND, src0, bld_imm_u32(bld, 0x80000000));
+ temp = bld_insn_2(bld, NV_OP_OR, temp, bld_imm_f32(bld, 1.0f));
+ dst0[c] = bld_insn_2(bld, NV_OP_XOR, temp, temp);
+ dst0[c]->insn->cc = NV_CC_EQ;
+ nv_reference(bld->pc, &dst0[c]->insn->flags_src, src1);
+ }
+ break;
case TGSI_OPCODE_SUB:
FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
src0 = emit_fetch(bld, insn, 0, c);