abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 402f41597b204b3e21903843346981c40b8bbe1a..7b6b851b36b591a4a7732d4ce395feca7f172dfc 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -174,11 +174,12 @@ struct XAigerWriter
                                undriven_bits.insert(bit);
                                unused_bits.insert(bit);
 
-                               bool keep = wire->get_bool_attribute(ID::keep);
-                               if (wire->port_input || keep)
+                               bool scc = wire->attributes.count(ID(abc9_scc));
+                               if (wire->port_input || scc)
                                        input_bits.insert(bit);
 
-                               if (wire->port_output || keep) {
+                               bool keep = wire->get_bool_attribute(ID::keep);
+                               if (wire->port_output || keep || scc) {
                                        if (bit != wirebit)
                                                alias_map[wirebit] = bit;
                                        output_bits.insert(wirebit);

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index b0bd81698570560fb0e35ebf963780e1c902f0d0..27e9fd2398f233328665cb2fe8248c98201e454c 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -110,14 +110,13 @@ void mark_scc(RTLIL::Module *module)
                        if (c.second.is_fully_const()) continue;
                        if (cell->output(c.first)) {
                                SigBit b = c.second.as_bit();
+                               // TODO: Don't be as heavy handed as to
+                               //       mark the entire wire as part of the scc
                                Wire *w = b.wire;
-                               w->set_bool_attribute(ID::keep);
-                               w->attributes[ID(abc9_scc_id)] = id.as_int();
+                               w->set_bool_attribute(ID(abc9_scc));
                        }
                }
        }
-
-       module->fixup_ports();
 }
 
 void prep_dff(RTLIL::Module *module)
@@ -967,10 +966,8 @@ void reintegrate(RTLIL::Module *module)
                RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
                RTLIL::Wire *wire = module->wire(port);
                log_assert(wire);
-               if (wire->attributes.erase(ID(abc9_scc_id))) {
-                       auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
-                       log_assert(r);
-               }
+               wire->attributes.erase(ID(abc9_scc));
+
                RTLIL::Wire *remap_wire = module->wire(remap_name(port));
                RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
                log_assert(GetSize(signal) >= GetSize(remap_wire));