dynamically redirect mmu load into single sv_proc_t::mmu_load fn

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3ee1ad84a4a74a56f2044532e6be0f4a856072f9..59268bf01bc56166d30e5d75f56c6139d0ca2594 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -2,6 +2,7 @@
 #include "processor.h"
 #include "mulhi.h"
 #include "sv_reg.h"
+#include "sv_mmu.h"
 
 void (sv_proc_t::WRITE_FRD)(sv_float32_t value)
 {
@@ -925,6 +926,32 @@ sv_float128_t sv_proc_t::f64_to_f128( sv_float64_t a)
 
 //-----
 
+sv_reg_t sv_proc_t::mmu_load(reg_spec_t const& spec, sv_reg_t const& offs,
+                                size_t width, bool ext)
+{
+    reg_t reg = READ_REG(spec);
+    sv_reg_t addr = rv_add(reg, offs);
+    switch (width)
+    {
+        case 8:
+            if (ext) return p->get_mmu()->load_uint8(addr);
+            else     return p->get_mmu()->load_int8(addr);
+        case 16:
+            if (ext) return p->get_mmu()->load_uint16(addr);
+            else     return p->get_mmu()->load_int16(addr);
+            break;
+        case 32:
+            if (ext) return p->get_mmu()->load_uint32(addr);
+            else     return p->get_mmu()->load_int32(addr);
+            break;
+        case 64:
+            if (ext) return p->get_mmu()->load_uint64(addr);
+            else     return p->get_mmu()->load_int64(addr);
+            break;
+    }
+    return 0;
+}
+
 sv_reg_t sv_proc_t::adjust_load(sv_reg_t const& v, size_t width, bool ext)
 {
     return v;

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 30a00bcf4ecb6cda2e4bd986d59f2d1d9511458f..76a22d45c7fb2fb3ea71c52435e656d41da77b56 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -267,6 +267,9 @@ public:
     sv_freg_t fsgnj128(sv_freg_t a, sv_freg_t b, bool n, bool x);
 
     sv_reg_t adjust_load(sv_reg_t const& v, size_t width, bool ext);
+    sv_reg_t mmu_load(reg_spec_t const& spec, sv_reg_t const& offs,
+                                size_t width, bool ext);
+
 
 #include "sv_insn_decl.h"
 };

diff --git a/riscv/sv_mmu.cc b/riscv/sv_mmu.cc
index 829e39f46f3e880fe37e3e9d921fccada31a9c02..8a79af7b3671d17f622b6fde625e86bdb469ac2e 100644 (file)
--- a/riscv/sv_mmu.cc
+++ b/riscv/sv_mmu.cc
@@ -1,28 +1,25 @@
 #include "sv_mmu.h"
 
-#define sv_load_func(type, ext) \
+#define sv_load_func(type, width, ext) \
 sv_reg_t sv_mmu_t::load_##type(reg_spec_t const& spec, sv_reg_t const& offs) { \
-  reg_t reg = proc->s.READ_REG(spec); \
-  sv_reg_t addr = proc->s.rv_add(reg, offs); \
-  type##_t v = mmu_t::load_##type(addr); \
-  return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
+  return proc->s.mmu_load(spec, offs, width, ext); \
 } \
 sv_reg_t sv_mmu_t::load_##type(reg_t const& addr) { \
   type##_t v = mmu_t::load_##type(addr); \
-  return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
+  return proc->s.adjust_load(sv_reg_t(v), width, ext); \
 } 
 
 // load value from memory at aligned address; zero extend to register width
-sv_load_func(uint8, true )
-sv_load_func(uint16, true )
-sv_load_func(uint32, true )
-sv_load_func(uint64, true )
+sv_load_func(uint8, 8, true )
+sv_load_func(uint16, 16, true )
+sv_load_func(uint32, 32, true )
+sv_load_func(uint64, 64, true )
 
 // load value from memory at aligned address; sign extend to register width
-sv_load_func(int8, false )
-sv_load_func(int16, false )
-sv_load_func(int32, false )
-sv_load_func(int64, false )
+sv_load_func(int8, 8, false )
+sv_load_func(int16, 16, false )
+sv_load_func(int32, 32, false )
+sv_load_func(int64, 64, false )
 
 #define sv_store_func(type) \
 void sv_mmu_t::store_##type(sv_reg_t const& addr, type##_t val) { \