This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
typedef RubyTester::SenderState SenderState;
-Check::Check(const Address& address, const Address& pc,
- int _num_writers, int _num_readers, RubyTester* _tester)
+Check::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
+ RubyTester* _tester)
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
{
}
// Prefetches are assumed to be 0 sized
- Request *req = new Request(m_address.getAddress(), 0, flags,
- m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
+ Request *req = new Request(m_address, 0, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
req->setThreadContext(index, 0);
PacketPtr pkt = new Packet(req, cmd);
Request::Flags flags;
- Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
+ Request *req = new Request(m_address, CHECK_SIZE, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
Packet::Command cmd;
Request::Flags flags;
// Create the particular address for the next byte to be written
- Address writeAddr(m_address.getAddress() + m_store_count);
+ Addr writeAddr(m_address + m_store_count);
// Stores are assumed to be 1 byte-sized
- Request *req = new Request(writeAddr.getAddress(), 1, flags,
- m_tester_ptr->masterId(), curTick(),
- m_pc.getAddress());
+ Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
+ curTick(), m_pc);
req->setThreadContext(index, 0);
Packet::Command cmd;
}
// Checks are sized depending on the number of bytes written
- Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
+ Request *req = new Request(m_address, CHECK_SIZE, flags,
+ m_tester_ptr->masterId(), curTick(), m_pc);
req->setThreadContext(index, 0);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
void
Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
{
- Address address = data->getAddress();
+ Addr address = data->getAddress();
// This isn't exactly right since we now have multi-byte checks
// assert(getAddress() == address);
- assert(getAddress().getLineAddress() == address.getLineAddress());
+ assert(makeLineAddress(m_address) == makeLineAddress(address));
assert(data != NULL);
DPRINTF(RubyTest, "RubyTester Callback\n");
}
DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc,
- getAddress().getLineAddress());
+ makeLineAddress(m_address));
DPRINTF(RubyTest, "Callback done\n");
debugPrint();
}
void
-Check::changeAddress(const Address& address)
+Check::changeAddress(Addr address)
{
assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
m_status = TesterStatus_Idle;
{
DPRINTF(RubyTest,
"[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n",
- m_address.getAddress(), (int)m_value,
- TesterStatus_to_string(m_status).c_str(),
+ m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
m_initiatingNode, m_store_count);
}
class Check
{
public:
- Check(const Address& address, const Address& pc, int _num_writers,
+ Check(Addr address, Addr pc, int _num_writers,
int _num_readers, RubyTester* _tester);
void initiate(); // Does Action or Check or nether
void performCallback(NodeID proc, SubBlock* data, Cycles curTime);
- const Address& getAddress() { return m_address; }
- void changeAddress(const Address& address);
+ Addr getAddress() const { return m_address; }
+ void changeAddress(Addr address);
void print(std::ostream& out) const;
uint8_t m_value;
int m_store_count;
NodeID m_initiatingNode;
- Address m_address;
- Address m_pc;
+ Addr m_address;
+ Addr m_pc;
RubyAccessMode m_access_mode;
int m_num_writers;
int m_num_readers;
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
{
- physical_address_t physical = 0;
- Address address;
+ Addr physical = 0;
const int size1 = 32;
const int size2 = 100;
physical = 1000;
for (int i = 0; i < size1; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += CHECK_SIZE;
}
physical = 1000;
for (int i = 0; i < size2; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += 256;
}
physical = 1000 + CHECK_SIZE;
for (int i = 0; i < size2; i++) {
// Setup linear addresses
- address.setAddress(physical);
- addCheck(address);
+ addCheck(physical);
physical += 256;
}
}
}
void
-CheckTable::addCheck(const Address& address)
+CheckTable::addCheck(Addr address)
{
if (floorLog2(CHECK_SIZE) != 0) {
- if (address.bitSelect(0, CHECK_SIZE_BITS - 1) != 0) {
+ if (bitSelect(address, 0, CHECK_SIZE_BITS - 1) != 0) {
panic("Check not aligned");
}
}
for (int i = 0; i < CHECK_SIZE; i++) {
- if (m_lookup_map.count(Address(address.getAddress()+i))) {
+ if (m_lookup_map.count(address+i)) {
// A mapping for this byte already existed, discard the
// entire check
return;
}
}
- Check* check_ptr = new Check(address, Address(100 + m_check_vector.size()),
+ Check* check_ptr = new Check(address, 100 + m_check_vector.size(),
m_num_writers, m_num_readers, m_tester_ptr);
for (int i = 0; i < CHECK_SIZE; i++) {
// Insert it once per byte
- m_lookup_map[Address(address.getAddress() + i)] = check_ptr;
+ m_lookup_map[address + i] = check_ptr;
}
m_check_vector.push_back(check_ptr);
}
}
Check*
-CheckTable::getCheck(const Address& address)
+CheckTable::getCheck(const Addr address)
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
- m5::hash_map<Address, Check*>::iterator i = m_lookup_map.find(address);
+ m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;
~CheckTable();
Check* getRandomCheck();
- Check* getCheck(const Address& address);
+ Check* getCheck(Addr address);
// bool isPresent(const Address& address) const;
// void removeCheckFromTable(const Address& address);
void print(std::ostream& out) const;
private:
- void addCheck(const Address& address);
+ void addCheck(Addr address);
// Private copy constructor and assignment operator
CheckTable(const CheckTable& obj);
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
- m5::hash_map<Address, Check*> m_lookup_map;
+ m5::hash_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;
{
SubBlock subBlock;
- SenderState(Address addr, int size) : subBlock(addr, size) {}
+ SenderState(Addr addr, int size) : subBlock(addr, size) {}
};
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
- void wakeUpAllBuffers(Address a);
+ void wakeUpBuffers(Addr a);
+ void wakeUpAllBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
// inclusive cache returns L0 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
if(is_valid(Dcache_entry)) {
return Dcache_entry;
return Icache_entry;
}
- Entry getDCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
return Dcache_entry;
}
- Entry getICacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
return Icache_entry;
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
if(is_valid(tbe)) {
return State:I;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
// MUST CHANGE
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L0Cache_State_to_permission(state));
}
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
- void wakeUpAllBuffers(Address a);
+ void wakeUpBuffers(Addr a);
+ void wakeUpAllBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
// inclusive cache returns L1 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
Entry cache_entry := static_cast(Entry, "pointer", cache[addr]);
return cache_entry;
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if(is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
return State:I;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
// MUST CHANGE
if(is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
// Class for messages sent between the L0 and the L1 controllers.
structure(CoherenceMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address of the cache block";
+ Addr addr, desc="Physical address of the cache block";
CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)";
RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Sender, desc="What component sent this message";
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
// inclusive cache returns L1 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
return L1Icache_entry;
}
- Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
return L1Dcache_entry;
}
- Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
return L1Icache_entry;
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
if(is_valid(tbe)) {
return State:NP;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
// MUST CHANGE
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
}
}
- void enqueuePrefetch(Address address, RubyRequestType type) {
+ void enqueuePrefetch(Addr address, RubyRequestType type) {
enqueue(optionalQueue_out, RubyRequest, 1) {
out_msg.LineAddress := address;
out_msg.Type := type;
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="Data is Dirty";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
void profileMsgDelay(int virtualNetworkType, Cycles c);
// inclusive cache, returns L2 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L2cache[addr]);
}
- bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) {
if (is_valid(cache_entry)) {
return cache_entry.Sharers.isElement(requestor);
} else {
}
}
- void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if(is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
return State:NP;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
// MUST CHANGE
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L2Cache_State_to_permission(state));
}
}
- Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
+ Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr,
MachineID requestor, Entry cache_entry) {
if(type == CoherenceRequestType:GETS) {
return Event:L1_GETS;
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
+ Addr PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
int Len, desc="...";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
bool functionalRead(Packet *pkt);
int functionalWrite(Packet *pkt);
}
void set_tbe(TBE tbe);
void unset_tbe();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
} else if (directory.isPresent(addr)) {
}
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
return num_functional_writes;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
if (directory.isPresent(addr)) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
MessageBuffer mandatoryQueue;
State cur_state;
- State getState(Address addr) {
+ State getState(Addr addr) {
return cur_state;
}
- void setState(Address addr, State state) {
+ void setState(Addr addr, State state) {
cur_state := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("DMA does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("DMA does not support functional write.");
}
// RequestMsg
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Requestor , desc="What component request";
// ResponseMsg
structure(ResponseMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
MachineID Sender, desc="What component sent the data";
NetDest Destination, desc="Node to whom the data is sent";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
void unset_tbe();
void profileMsgDelay(int virtualNetworkType, Cycles b);
- Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr address), return_by_pointer="yes" {
return static_cast(Entry, "pointer", cacheMemory.lookup(address));
}
}
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
}
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return L1Cache_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
+ Addr PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
int Len, desc="...";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
// ** OBJECTS **
void set_tbe(TBE b);
void unset_tbe();
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
} else if (directory.isPresent(addr)) {
}
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return Directory_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
if (directory.isPresent(addr)) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
MessageBuffer mandatoryQueue;
State cur_state;
- State getState(Address addr) {
+ State getState(Addr addr) {
return cur_state;
}
- void setState(Address addr, State state) {
+ void setState(Addr addr, State state) {
cur_state := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("DMA does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("DMA does not support functional write.");
}
// RequestMsg (and also forwarded requests)
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Multicast destination mask";
// ResponseMsg (and also unblock requests)
structure(ResponseMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
MachineID Sender, desc="Node who sent the data";
NetDest Destination, desc="Node to whom the data is sent";
structure(DMARequestMsg, desc="...", interface="Message") {
DMARequestType Type, desc="Request type (read/write)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
structure(DMAResponseMsg, desc="...", interface="Message") {
DMAResponseType Type, desc="Response type (DATA/ACK)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
MessageSizeType MessageSize, desc="size category of the message";
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
bool Dirty, desc="Is the data dirty (different than memory)?";
}
structure(TBETable, external ="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
void set_cache_entry(AbstractCacheEntry b);
TimerTable useTimerTable;
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
return L1Icache_entry;
}
- Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L1Dcache.lookup(addr));
}
- Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L1Icache.lookup(addr));
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if(is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
return State:I;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
if (is_valid(tbe)) {
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
Entry cache_entry := getCacheEntry(addr);
if(is_valid(cache_entry)) {
testAndRead(addr, cache_entry.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
Entry cache_entry := getCacheEntry(addr);
// ** IN_PORTS **
// Use Timer
- in_port(useTimerTable_in, Address, useTimerTable) {
+ in_port(useTimerTable_in, Addr, useTimerTable) {
if (useTimerTable_in.isReady()) {
trigger(Event:Use_Timeout, useTimerTable.readyAddress(),
getCacheEntry(useTimerTable.readyAddress()),
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
- Address PC, desc="Program counter of request";
+ Addr PC, desc="Program counter of request";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, desc="Is the data dirty (different than memory)?";
}
structure(TBETable, external = "yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
structure(PerfectCacheMemory, external = "yes") {
- void allocate(Address);
- void deallocate(Address);
- DirEntry lookup(Address);
- bool isTagPresent(Address);
+ void allocate(Addr);
+ void deallocate(Addr);
+ DirEntry lookup(Addr);
+ bool isTagPresent(Addr);
}
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
void set_tbe(TBE b);
void unset_tbe();
- Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr address), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L2cache[address]);
}
- bool isDirTagPresent(Address addr) {
+ bool isDirTagPresent(Addr addr) {
return (localDirectory.isTagPresent(addr) );
}
- DirEntry getDirEntry(Address address), return_by_pointer="yes" {
+ DirEntry getDirEntry(Addr address), return_by_pointer="yes" {
return localDirectory.lookup(address);
}
- bool isOnlySharer(Entry cache_entry, Address addr, MachineID shar_id) {
+ bool isOnlySharer(Entry cache_entry, Addr addr, MachineID shar_id) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
if (cache_entry.Sharers.count() > 1) {
}
}
- void copyCacheStateToDir(Entry cache_entry, Address addr) {
+ void copyCacheStateToDir(Entry cache_entry, Addr addr) {
assert(localDirectory.isTagPresent(addr) == false);
assert(is_valid(cache_entry));
localDirectory.allocate(addr);
}
- void copyDirToCache(Entry cache_entry, Address addr) {
+ void copyDirToCache(Entry cache_entry, Addr addr) {
assert(is_valid(cache_entry));
DirEntry dir_entry := getDirEntry(addr);
cache_entry.Sharers := dir_entry.Sharers;
}
- void recordLocalSharerInDir(Entry cache_entry, Address addr, MachineID shar_id) {
+ void recordLocalSharerInDir(Entry cache_entry, Addr addr, MachineID shar_id) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
cache_entry.Sharers.add(shar_id);
}
}
- void recordNewLocalExclusiveInDir(Entry cache_entry, Address addr, MachineID exc_id) {
+ void recordNewLocalExclusiveInDir(Entry cache_entry, Addr addr, MachineID exc_id) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
}
}
- void removeAllLocalSharersFromDir(Entry cache_entry, Address addr) {
+ void removeAllLocalSharersFromDir(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
cache_entry.Sharers.clear();
}
}
- void removeSharerFromDir(Entry cache_entry, Address addr, MachineID sender) {
+ void removeSharerFromDir(Entry cache_entry, Addr addr, MachineID sender) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
cache_entry.Sharers.remove(sender);
}
}
- void removeOwnerFromDir(Entry cache_entry, Address addr, MachineID sender) {
+ void removeOwnerFromDir(Entry cache_entry, Addr addr, MachineID sender) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
cache_entry.OwnerValid := false;
}
}
- bool isLocalSharer(Entry cache_entry, Address addr, MachineID shar_id) {
+ bool isLocalSharer(Entry cache_entry, Addr addr, MachineID shar_id) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
return cache_entry.Sharers.isElement(shar_id);
}
}
- NetDest getLocalSharers(Entry cache_entry, Address addr) {
+ NetDest getLocalSharers(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
return cache_entry.Sharers;
}
}
- MachineID getLocalOwner(Entry cache_entry, Address addr) {
+ MachineID getLocalOwner(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
return cache_entry.Owner;
}
}
- int countLocalSharers(Entry cache_entry, Address addr) {
+ int countLocalSharers(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
return cache_entry.Sharers.count();
}
}
- bool isLocalOwnerValid(Entry cache_entry, Address addr) {
+ bool isLocalOwnerValid(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
return cache_entry.OwnerValid;
}
}
- int countLocalSharersExceptRequestor(Entry cache_entry, Address addr, MachineID requestor) {
+ int countLocalSharersExceptRequestor(Entry cache_entry, Addr addr, MachineID requestor) {
if (is_valid(cache_entry)) {
assert (localDirectory.isTagPresent(addr) == false);
if (cache_entry.Sharers.isElement(requestor)) {
}
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
return CoherenceRequestType_to_string(type);
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((localDirectory.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
if (is_valid(tbe)) {
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L2Cache_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
}
structure(TBE, desc="...") {
- Address PhysicalAddress, desc="Physical address for this entry";
+ Addr PhysicalAddress, desc="Physical address for this entry";
int Len, desc="Length of request";
DataBlock DataBlk, desc="DataBlk";
MachineID Requestor, desc="original requestor";
}
structure(TBETable, external = "yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
// ** OBJECTS **
void set_tbe(TBE b);
void unset_tbe();
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
return getDirectoryEntry(addr).DirectoryState;
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
if (directory.isPresent(addr)) {
if (state == State:I) {
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
if (directory.isPresent(addr)) {
DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
if (directory.isPresent(addr)) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
functionalMemoryRead(pkt);
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
return num_functional_writes;
// if no sharers, then directory can be considered
// both a sharer and exclusive w.r.t. coherence checking
- bool isBlockShared(Address addr) {
+ bool isBlockShared(Addr addr) {
if (directory.isPresent(addr)) {
if (getDirectoryEntry(addr).DirectoryState == State:I) {
return true;
return false;
}
- bool isBlockExclusive(Address addr) {
+ bool isBlockExclusive(Addr addr) {
if (directory.isPresent(addr)) {
if (getDirectoryEntry(addr).DirectoryState == State:I) {
return true;
desc="Queue off-chip writeback request") {
peek(unblockNetwork_in, ResponseMsg) {
DataBlock DataBlk := in_msg.DataBlk;
- DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress),
+ DataBlk.copyPartial(tbe.DataBlk, getOffset(tbe.PhysicalAddress),
tbe.Len);
queueMemoryWrite(tbe.Requestor, address, to_memory_controller_latency,
DataBlk);
}
structure(TBE, desc="...") {
- Address address, desc="Physical address";
+ Addr address, desc="Physical address";
int NumAcks, default="0", desc="Number of Acks pending";
DataBlock DataBlk, desc="Data";
}
structure(TBETable, external = "yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
MessageBuffer mandatoryQueue;
void set_tbe(TBE b);
void unset_tbe();
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
return cur_state;
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
cur_state := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("DMA does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("DMA does not support functional write.");
}
// TriggerMsg
structure(TriggerMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
TriggerType Type, desc="Type of trigger";
bool functionalRead(Packet *pkt) {
// RequestMsg (and also forwarded requests)
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
int Len, desc="Length of Request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
MachineID Requestor, desc="Node who initiated the request";
// ResponseMsg (and also unblock requests)
structure(ResponseMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
MachineID Sender, desc="Node who sent the data";
MachineType SenderMachine, desc="type of component sending msg";
// TBE fields
structure(TBE, desc="...") {
- Address addr, desc="Physical address for this TBE";
+ Addr addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
int IssueCount, default="0", desc="The number of times we've issued a request for this line.";
- Address PC, desc="Program counter of request";
+ Addr PC, desc="Program counter of request";
bool WentPersistent, default="false", desc="Request went persistent";
bool ExternalResponse, default="false", desc="Response came from an external controller";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
structure(PersistentTable, external="yes") {
- void persistentRequestLock(Address, MachineID, AccessType);
- void persistentRequestUnlock(Address, MachineID);
- bool okToIssueStarving(Address, MachineID);
- MachineID findSmallest(Address);
- AccessType typeOfSmallest(Address);
- void markEntries(Address);
- bool isLocked(Address);
- int countStarvingForAddress(Address);
- int countReadStarvingForAddress(Address);
+ void persistentRequestLock(Addr, MachineID, AccessType);
+ void persistentRequestUnlock(Addr, MachineID);
+ bool okToIssueStarving(Addr, MachineID);
+ MachineID findSmallest(Addr);
+ AccessType typeOfSmallest(Addr);
+ void markEntries(Addr);
+ bool isLocked(Addr);
+ int countStarvingForAddress(Addr);
+ int countReadStarvingForAddress(Addr);
}
void set_cache_entry(AbstractCacheEntry b);
void set_tbe(TBE b);
void unset_tbe();
void wakeUpAllBuffers();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
Cycles curCycle();
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
}
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
return L1Icache_entry;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
num_functional_writes := num_functional_writes +
testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
return num_functional_writes;
}
- Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
return L1Dcache_entry;
}
- Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
+ Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
return L1Icache_entry;
}
return 0;
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
}
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
if (is_valid(tbe)) {
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := L1_TBEs[addr];
if(is_valid(tbe)) {
return L1Cache_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
}
// NOTE: direct local hits should not call this function
- bool isExternalHit(Address addr, MachineID sender) {
+ bool isExternalHit(Addr addr, MachineID sender) {
if (machineIDToMachineType(sender) == MachineType:L1Cache) {
return true;
} else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
return true;
}
- bool okToIssueStarving(Address addr, MachineID machineID) {
+ bool okToIssueStarving(Addr addr, MachineID machineID) {
return persistentTable.okToIssueStarving(addr, machineID);
}
- void markPersistentEntries(Address addr) {
+ void markPersistentEntries(Addr addr) {
persistentTable.markEntries(addr);
}
// ** IN_PORTS **
// Use Timer
- in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
+ in_port(useTimerTable_in, Addr, useTimerTable, rank=5) {
if (useTimerTable_in.isReady()) {
TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
}
// Reissue Timer
- in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
+ in_port(reissueTimerTable_in, Addr, reissueTimerTable, rank=4) {
if (reissueTimerTable_in.isReady()) {
trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
getCacheEntry(reissueTimerTable.readyAddress()),
}
structure(PerfectCacheMemory, external="yes") {
- void allocate(Address);
- void deallocate(Address);
- DirEntry lookup(Address);
- bool isTagPresent(Address);
+ void allocate(Addr);
+ void deallocate(Addr);
+ DirEntry lookup(Addr);
+ bool isTagPresent(Addr);
}
structure(PersistentTable, external="yes") {
- void persistentRequestLock(Address, MachineID, AccessType);
- void persistentRequestUnlock(Address, MachineID);
- MachineID findSmallest(Address);
- AccessType typeOfSmallest(Address);
- void markEntries(Address);
- bool isLocked(Address);
- int countStarvingForAddress(Address);
- int countReadStarvingForAddress(Address);
+ void persistentRequestLock(Addr, MachineID, AccessType);
+ void persistentRequestUnlock(Addr, MachineID);
+ MachineID findSmallest(Addr);
+ AccessType typeOfSmallest(Addr);
+ void markEntries(Addr);
+ bool isLocked(Addr);
+ int countStarvingForAddress(Addr);
+ int countReadStarvingForAddress(Addr);
}
PersistentTable persistentTable;
void set_cache_entry(AbstractCacheEntry b);
void unset_cache_entry();
- Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr address), return_by_pointer="yes" {
Entry cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
return cache_entry;
}
- DirEntry getDirEntry(Address address), return_by_pointer="yes" {
+ DirEntry getDirEntry(Addr address), return_by_pointer="yes" {
return localDirectory.lookup(address);
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
num_functional_writes := num_functional_writes +
testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
}
}
- State getState(Entry cache_entry, Address addr) {
+ State getState(Entry cache_entry, Addr addr) {
if (is_valid(cache_entry)) {
return cache_entry.CacheState;
} else if (persistentTable.isLocked(addr)) {
}
}
- void setState(Entry cache_entry, Address addr, State state) {
+ void setState(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
// Make sure the token count is in range
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
Entry cache_entry := getCacheEntry(addr);
if(is_valid(cache_entry)) {
return L2Cache_State_to_permission(cache_entry.CacheState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L2Cache_State_to_permission(state));
}
}
- void removeSharer(Address addr, NodeID id) {
+ void removeSharer(Addr addr, NodeID id) {
if (localDirectory.isTagPresent(addr)) {
DirEntry dir_entry := getDirEntry(addr);
}
}
- bool sharersExist(Address addr) {
+ bool sharersExist(Addr addr) {
if (localDirectory.isTagPresent(addr)) {
DirEntry dir_entry := getDirEntry(addr);
if (dir_entry.Sharers.count() > 0) {
}
}
- bool exclusiveExists(Address addr) {
+ bool exclusiveExists(Addr addr) {
if (localDirectory.isTagPresent(addr)) {
DirEntry dir_entry := getDirEntry(addr);
if (dir_entry.exclusive) {
}
// assumes that caller will check to make sure tag is present
- Set getSharers(Address addr) {
+ Set getSharers(Addr addr) {
DirEntry dir_entry := getDirEntry(addr);
return dir_entry.Sharers;
}
- void setNewWriter(Address addr, NodeID id) {
+ void setNewWriter(Addr addr, NodeID id) {
if (localDirectory.isTagPresent(addr) == false) {
localDirectory.allocate(addr);
}
dir_entry.exclusive := true;
}
- void addNewSharer(Address addr, NodeID id) {
+ void addNewSharer(Addr addr, NodeID id) {
if (localDirectory.isTagPresent(addr) == false) {
localDirectory.allocate(addr);
}
// dir_entry.exclusive := false;
}
- void clearExclusiveBitIfExists(Address addr) {
+ void clearExclusiveBitIfExists(Addr addr) {
if (localDirectory.isTagPresent(addr)) {
DirEntry dir_entry := getDirEntry(addr);
dir_entry.exclusive := false;
}
structure(PersistentTable, external="yes") {
- void persistentRequestLock(Address, MachineID, AccessType);
- void persistentRequestUnlock(Address, MachineID);
- bool okToIssueStarving(Address, MachineID);
- MachineID findSmallest(Address);
- AccessType typeOfSmallest(Address);
- void markEntries(Address);
- bool isLocked(Address);
- int countStarvingForAddress(Address);
- int countReadStarvingForAddress(Address);
+ void persistentRequestLock(Addr, MachineID, AccessType);
+ void persistentRequestUnlock(Addr, MachineID);
+ bool okToIssueStarving(Addr, MachineID);
+ MachineID findSmallest(Addr);
+ AccessType typeOfSmallest(Addr);
+ void markEntries(Addr);
+ bool isLocked(Addr);
+ int countStarvingForAddress(Addr);
+ int countReadStarvingForAddress(Addr);
}
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
+ Addr PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Current view of the associated address range";
int Len, desc="...";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
// ** OBJECTS **
void set_tbe(TBE b);
void unset_tbe();
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- State getState(TBE tbe, Address addr) {
+ State getState(TBE tbe, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
} else {
}
}
- void setState(TBE tbe, Address addr, State state) {
+ void setState(TBE tbe, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return Directory_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
- bool okToIssueStarving(Address addr, MachineID machinID) {
+ bool okToIssueStarving(Addr addr, MachineID machinID) {
return persistentTable.okToIssueStarving(addr, machineID);
}
- void markPersistentEntries(Address addr) {
+ void markPersistentEntries(Addr addr) {
persistentTable.markEntries(addr);
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
}
// Reissue Timer
- in_port(reissueTimerTable_in, Address, reissueTimerTable) {
+ in_port(reissueTimerTable_in, Addr, reissueTimerTable) {
if (reissueTimerTable_in.isReady()) {
trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
TBEs[reissueTimerTable.readyAddress()]);
peek(responseNetwork_in, ResponseMsg) {
DataBlock DataBlk := tbe.DataBlk;
tbe.DataBlk := in_msg.DataBlk;
- tbe.DataBlk.copyPartial(DataBlk, addressOffset(tbe.PhysicalAddress),
+ tbe.DataBlk.copyPartial(DataBlk, getOffset(tbe.PhysicalAddress),
tbe.Len);
}
}
MessageBuffer mandatoryQueue;
State cur_state;
- State getState(Address addr) {
+ State getState(Addr addr) {
return cur_state;
}
- void setState(Address addr, State state) {
+ void setState(Addr addr, State state) {
cur_state := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("DMA does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("DMA does not support functional write.");
}
// PersistentMsg
structure(PersistentMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
PersistentRequestType Type, desc="Type of starvation request";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination set";
// RequestMsg
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Multicast destination mask";
// ResponseMsg
structure(ResponseMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
MachineID Sender, desc="Node who sent the data";
NetDest Destination, desc="Node to whom the data is sent";
structure(DMARequestMsg, desc="...", interface="Message") {
DMARequestType Type, desc="Request type (read/write)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
structure(DMAResponseMsg, desc="...", interface="Message") {
DMAResponseType Type, desc="Response type (DATA/ACK)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
MessageSizeType MessageSize, desc="size category of the message";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
void set_tbe(TBE b);
void unset_tbe();
void wakeUpAllBuffers();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
Cycles curCycle();
- Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr address), return_by_pointer="yes" {
Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
if(is_valid(L2cache_entry)) {
return L2cache_entry;
return L1Icache_entry;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
Entry cache_entry := getCacheEntry(addr);
if(is_valid(cache_entry)) {
testAndRead(addr, cache_entry.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
Entry cache_entry := getCacheEntry(addr);
return num_functional_writes;
}
- Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
+ Entry getL2CacheEntry(Addr address), return_by_pointer="yes" {
Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
return L2cache_entry;
}
- Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getL1DCacheEntry(Addr address), return_by_pointer="yes" {
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
return L1Dcache_entry;
}
- Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
+ Entry getL1ICacheEntry(Addr address), return_by_pointer="yes" {
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
return L1Icache_entry;
}
- State getState(TBE tbe, Entry cache_entry, Address addr) {
+ State getState(TBE tbe, Entry cache_entry, Addr addr) {
if(is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
return State:I;
}
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
}
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return L1Cache_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
if (is_valid(cache_entry)) {
cache_entry.changePermission(L1Cache_State_to_permission(state));
}
if (L2cache.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
- Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
+ Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
}
} else {
// No room in the L1, so we need to make room
- Address l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
+ Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
if (L2cache.cacheAvail(l1i_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
getL1ICacheEntry(l1i_victim_addr),
TBEs[l1i_victim_addr]);
} else {
- Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
+ Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
if (L2cache.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
} else {
- Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
+ Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
}
} else {
// No room in the L1, so we need to make room
- Address l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
+ Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
if (L2cache.cacheAvail(l1d_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
getL1DCacheEntry(l1d_victim_addr),
TBEs[l1d_victim_addr]);
} else {
- Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
+ Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
+ Addr PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
CoherenceResponseType ResponseType, desc="The type for the subsequent response message";
int Acks, default="0", desc="The number of acks that the waiting response represents";
}
structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
}
void set_cache_entry(AbstractCacheEntry b);
void unset_cache_entry();
void set_tbe(TBE a);
void unset_tbe();
- void wakeUpBuffers(Address a);
+ void wakeUpBuffers(Addr a);
Cycles curCycle();
// ** OBJECTS **
TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
- PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" {
+ PfEntry getProbeFilterEntry(Addr addr), return_by_pointer="yes" {
if (probe_filter_enabled || full_bit_dir_enabled) {
PfEntry pfEntry := static_cast(PfEntry, "pointer", probeFilter.lookup(addr));
return pfEntry;
return OOD;
}
- State getState(TBE tbe, PfEntry pf_entry, Address addr) {
+ State getState(TBE tbe, PfEntry pf_entry, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
} else {
}
}
- void setState(TBE tbe, PfEntry pf_entry, Address addr, State state) {
+ void setState(TBE tbe, PfEntry pf_entry, Addr addr, State state) {
if (is_valid(tbe)) {
tbe.TBEState := state;
}
getDirectoryEntry(addr).DirectoryState := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
return Directory_State_to_permission(tbe.TBEState);
return AccessPermission:NotPresent;
}
- void setAccessPermission(PfEntry pf_entry, Address addr, State state) {
+ void setAccessPermission(PfEntry pf_entry, Addr addr, State state) {
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
}
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
TBE tbe := TBEs[addr];
MessageBuffer mandatoryQueue;
State cur_state;
- State getState(Address addr) {
+ State getState(Addr addr) {
return cur_state;
}
- void setState(Address addr, State state) {
+ void setState(Addr addr, State state) {
cur_state := state;
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("DMA does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("DMA does not support functional write.");
}
// TriggerMsg
structure(TriggerMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
TriggerType Type, desc="Type of trigger";
bool functionalRead(Packet *pkt) {
// RequestMsg (and also forwarded requests)
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
MachineID Requestor, desc="Node who initiated the request";
NetDest MergedRequestors, desc="Merge set of read requestors";
// ResponseMsg (and also unblock requests)
structure(ResponseMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
MachineID Sender, desc="Node who sent the data";
MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
structure(DMARequestMsg, desc="...", interface="Message") {
DMARequestType Type, desc="Request type (read/write)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
structure(DMAResponseMsg, desc="...", interface="Message") {
DMAResponseType Type, desc="Response type (DATA/ACK)";
- Address PhysicalAddress, desc="Physical address for this request";
- Address LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
MessageSizeType MessageSize, desc="size category of the message";
}
- State getState(Entry cache_entry, Address addr) {
+ State getState(Entry cache_entry, Addr addr) {
return State:I;
}
- void setState(Entry cache_entry, Address addr, State state) {
+ void setState(Entry cache_entry, Addr addr, State state) {
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ void setAccessPermission(Entry cache_entry, Addr addr, State state) {
}
- Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ Entry getCacheEntry(Addr address), return_by_pointer="yes" {
return OOD;
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("Network test does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("Network test does not support functional write.");
}
}
// ** OBJECTS **
- State getState(Address addr) {
+ State getState(Addr addr) {
return State:I;
}
- void setState(Address addr, State state) {
+ void setState(Addr addr, State state) {
}
- AccessPermission getAccessPermission(Address addr) {
+ AccessPermission getAccessPermission(Addr addr) {
return AccessPermission:NotPresent;
}
- void setAccessPermission(Address addr, State state) {
+ void setAccessPermission(Addr addr, State state) {
}
- void functionalRead(Address addr, Packet *pkt) {
+ void functionalRead(Addr addr, Packet *pkt) {
error("Network test does not support functional read.");
}
- int functionalWrite(Address addr, Packet *pkt) {
+ int functionalWrite(Addr addr, Packet *pkt) {
error("Network test does not support functional write.");
}
// RequestMsg (and also forwarded requests)
structure(RequestMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Multicast destination mask";
// Mapping functions
int machineCount(MachineType machType);
-MachineID mapAddressToRange(Address addr, MachineType type,
+MachineID mapAddressToRange(Addr addr, MachineType type,
int low, int high);
-MachineID mapAddressToRange(Address addr, MachineType type,
+MachineID mapAddressToRange(Addr addr, MachineType type,
int low, int high, NodeID n);
NetDest broadcast(MachineType type);
-MachineID map_Address_to_DMA(Address addr);
-MachineID map_Address_to_Directory(Address addr);
-NodeID map_Address_to_DirectoryNode(Address addr);
+MachineID map_Address_to_DMA(Addr addr);
+MachineID map_Address_to_Directory(Addr addr);
+NodeID map_Address_to_DirectoryNode(Addr addr);
NodeID machineIDToNodeID(MachineID machID);
NodeID machineIDToVersion(MachineID machID);
MachineType machineIDToMachineType(MachineID machID);
// Functions implemented in the AbstractController class for
// making timing access to the memory maintained by the
// memory controllers.
-void queueMemoryRead(MachineID id, Address addr, Cycles latency);
-void queueMemoryWrite(MachineID id, Address addr, Cycles latency,
+void queueMemoryRead(MachineID id, Addr addr, Cycles latency);
+void queueMemoryWrite(MachineID id, Addr addr, Cycles latency,
DataBlock block);
-void queueMemoryWritePartial(MachineID id, Address addr, Cycles latency,
+void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency,
DataBlock block, int size);
// Functions implemented in the AbstractController class for
external_type(uint64, primitive="yes");
external_type(PacketPtr, primitive="yes");
external_type(Packet, primitive="yes");
-external_type(Address);
+external_type(Addr, primitive="yes");
external_type(Cycles, primitive="yes", default="Cycles(0)");
structure(DataBlock, external = "yes", desc="..."){
void copyPartial(DataBlock, int, int);
}
-bool testAndRead(Address addr, DataBlock datablk, Packet *pkt);
-bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt);
+bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
+bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
// AccessPermission
// The following five states define the access permission of all memory blocks.
// CacheMsg
structure(SequencerMsg, desc="...", interface="Message") {
- Address LineAddress, desc="Line address for this request";
- Address PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
- Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
+ Addr ProgramCounter, desc="Program counter of the instruction that caused the miss";
RubyAccessMode AccessMode, desc="user/supervisor access type";
DataBlock DataBlk, desc="Data";
int Len, desc="size in bytes of access";
// Message to and from Memory Control
structure(MemoryMsg, desc="...", interface="Message") {
- Address addr, desc="Physical address for this request";
+ Addr addr, desc="Physical address for this request";
MemoryRequestType Type, desc="Type of memory request (MEMORY_READ or MEMORY_WB)";
MachineID Sender, desc="What component sent the data";
MachineID OriginalRequestorMachId, desc="What component originally requested";
}
structure (Sequencer, external = "yes") {
- void readCallback(Address, DataBlock);
- void readCallback(Address, DataBlock, bool);
- void readCallback(Address, DataBlock, bool, MachineType);
- void readCallback(Address, DataBlock, bool, MachineType,
+ void readCallback(Addr, DataBlock);
+ void readCallback(Addr, DataBlock, bool);
+ void readCallback(Addr, DataBlock, bool, MachineType);
+ void readCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
- void writeCallback(Address, DataBlock);
- void writeCallback(Address, DataBlock, bool);
- void writeCallback(Address, DataBlock, bool, MachineType);
- void writeCallback(Address, DataBlock, bool, MachineType,
+ void writeCallback(Addr, DataBlock);
+ void writeCallback(Addr, DataBlock, bool);
+ void writeCallback(Addr, DataBlock, bool, MachineType);
+ void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
- void checkCoherence(Address);
- void evictionCallback(Address);
+ void checkCoherence(Addr);
+ void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
- bool checkResourceAvailable(CacheResourceType, Address);
- void invalidateSC(Address);
+ bool checkResourceAvailable(CacheResourceType, Addr);
+ void invalidateSC(Addr);
}
structure(RubyRequest, desc="...", interface="Message", external="yes") {
- Address LineAddress, desc="Line address for this request";
- Address PhysicalAddress, desc="Physical address for this request";
+ Addr LineAddress, desc="Line address for this request";
+ Addr PhysicalAddress, desc="Physical address for this request";
RubyRequestType Type, desc="Type of request (LD, ST, etc)";
- Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
+ Addr ProgramCounter, desc="Program counter of the instruction that caused the miss";
RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
structure (DirectoryMemory, external = "yes") {
- AbstractEntry allocate(Address, AbstractEntry);
- AbstractEntry lookup(Address);
- bool isPresent(Address);
- void invalidateBlock(Address);
+ AbstractEntry allocate(Addr, AbstractEntry);
+ AbstractEntry lookup(Addr);
+ bool isPresent(Addr);
+ void invalidateBlock(Addr);
void recordRequestType(DirectoryRequestType);
}
}
structure (CacheMemory, external = "yes") {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- AbstractCacheEntry allocate(Address, AbstractCacheEntry);
- AbstractCacheEntry allocate(Address, AbstractCacheEntry, bool);
- void allocateVoid(Address, AbstractCacheEntry);
- void deallocate(Address);
- AbstractCacheEntry lookup(Address);
- bool isTagPresent(Address);
+ bool cacheAvail(Addr);
+ Addr cacheProbe(Addr);
+ AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
+ AbstractCacheEntry allocate(Addr, AbstractCacheEntry, bool);
+ void allocateVoid(Addr, AbstractCacheEntry);
+ void deallocate(Addr);
+ AbstractCacheEntry lookup(Addr);
+ bool isTagPresent(Addr);
Cycles getTagLatency();
Cycles getDataLatency();
- void setMRU(Address);
- void recordRequestType(CacheRequestType, Address);
- bool checkResourceAvailable(CacheResourceType, Address);
+ void setMRU(Addr);
+ void recordRequestType(CacheRequestType, Addr);
+ bool checkResourceAvailable(CacheResourceType, Addr);
int getCacheSize();
int getNumBlocks();
- Address getAddressAtIdx(int);
+ Addr getAddressAtIdx(int);
Scalar demand_misses;
Scalar demand_hits;
structure (TimerTable, inport="yes", external = "yes") {
bool isReady();
- Address readyAddress();
- void set(Address, Cycles);
- void unset(Address);
- bool isSet(Address);
+ Addr readyAddress();
+ void set(Addr, Cycles);
+ void unset(Addr);
+ bool isSet(Addr);
}
structure (GenericBloomFilter, external = "yes") {
void clear(int);
- void increment(Address, int);
- void decrement(Address, int);
- void set(Address, int);
- void unset(Address, int);
+ void increment(Addr, int);
+ void decrement(Addr, int);
+ void set(Addr, int);
+ void unset(Addr, int);
- bool isSet(Address, int);
- int getCount(Address, int);
+ bool isSet(Addr, int);
+ int getCount(Addr, int);
}
structure (Prefetcher, external = "yes") {
- void observeMiss(Address, RubyRequestType);
- void observePfHit(Address);
- void observePfMiss(Address);
+ void observeMiss(Addr, RubyRequestType);
+ void observePfHit(Addr);
+ void observePfMiss(Addr);
}
Cycles zero_time();
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
-int addressToInt(Address addr);
+int addressToInt(Addr addr);
void procProfileCoherenceRequest(NodeID node, bool needCLB);
void dirProfileCoherenceRequest(NodeID node, bool needCLB);
int max_tokens();
-Address setOffset(Address addr, int offset);
-Address makeLineAddress(Address addr);
-int addressOffset(Address addr);
+Addr setOffset(Addr addr, int offset);
+Addr makeLineAddress(Addr addr);
+int getOffset(Addr addr);
int mod(int val, int mod);
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/system/System.hh"
-physical_address_t
-Address::getLineAddress() const
+Addr
+bitSelect(Addr addr, unsigned int small, unsigned int big)
{
- return bitSelect(RubySystem::getBlockSizeBits(), ADDRESS_WIDTH);
-}
+ assert(big >= small);
-physical_address_t
-Address::getOffset() const
-{
- return bitSelect(0, RubySystem::getBlockSizeBits() - 1);
+ if (big >= ADDRESS_WIDTH - 1) {
+ return (addr >> small);
+ } else {
+ Addr mask = ~((Addr)~0 << (big + 1));
+ // FIXME - this is slow to manipulate a 64-bit number using 32-bits
+ Addr partial = (addr & mask);
+ return (partial >> small);
+ }
}
-void
-Address::makeLineAddress()
+Addr
+bitRemove(Addr addr, unsigned int small, unsigned int big)
{
- m_address = maskLowOrderBits(RubySystem::getBlockSizeBits());
-}
+ assert(big >= small);
-// returns the next stride address based on line address
-void
-Address::makeNextStrideAddress(int stride)
-{
- m_address = maskLowOrderBits(RubySystem::getBlockSizeBits())
- + RubySystem::getBlockSizeBytes()*stride;
+ if (small >= ADDRESS_WIDTH - 1) {
+ return addr;
+ } else if (big >= ADDRESS_WIDTH - 1) {
+ Addr mask = (Addr)~0 >> small;
+ return (addr & mask);
+ } else if (small == 0) {
+ Addr mask = (Addr)~0 << big;
+ return (addr & mask);
+ } else {
+ Addr mask = ~((Addr)~0 << small);
+ Addr lower_bits = addr & mask;
+ mask = (Addr)~0 << (big + 1);
+ Addr higher_bits = addr & mask;
+
+ // Shift the valid high bits over the removed section
+ higher_bits = higher_bits >> (big - small + 1);
+ return (higher_bits | lower_bits);
+ }
}
-int64
-Address::memoryModuleIndex() const
+Addr
+maskLowOrderBits(Addr addr, unsigned int number)
{
- int64 index =
- bitSelect(RubySystem::getBlockSizeBits() +
- RubySystem::getMemorySizeBits(), ADDRESS_WIDTH);
- assert (index >= 0);
- return index;
+ Addr mask;
- // int64 indexHighPortion =
- // address.bitSelect(MEMORY_SIZE_BITS - 1,
- // PAGE_SIZE_BITS + NUMBER_OF_MEMORY_MODULE_BITS);
- // int64 indexLowPortion =
- // address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS - 1);
- //
- // int64 index = indexLowPortion |
- // (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS));
-
- /*
- Round-robin mapping of addresses, at page size granularity
-
-ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS
- | | | |
- \ / \ / \ / \ / 0
- -----------------------------------------------------------------------
- | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
- | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
- -----------------------------------------------------------------------
- indexHighPortion indexLowPortion
- <------->
- NUMBER_OF_MEMORY_MODULE_BITS
- */
+ if (number >= ADDRESS_WIDTH - 1) {
+ mask = ~0;
+ } else {
+ mask = (Addr)~0 << number;
+ }
+ return (addr & mask);
}
-void
-Address::print(std::ostream& out) const
+Addr
+maskHighOrderBits(Addr addr, unsigned int number)
{
- using namespace std;
- out << "[" << hex << "0x" << m_address << "," << " line 0x"
- << maskLowOrderBits(RubySystem::getBlockSizeBits()) << dec << "]"
- << flush;
-}
+ Addr mask;
-void
-Address::output(std::ostream& out) const
-{
- // Note: this outputs addresses in the form "ffff", not "0xffff".
- // This code should always be able to write out addresses in a
- // format that can be read in by the below input() method. Please
- // don't change this without talking to Milo first.
- out << std::hex << m_address << std::dec;
+ if (number >= ADDRESS_WIDTH - 1) {
+ mask = ~0;
+ } else {
+ mask = (Addr)~0 >> number;
+ }
+ return (addr & mask);
}
-void
-Address::input(std::istream& in)
+Addr
+shiftLowOrderBits(Addr addr, unsigned int number)
{
- // Note: this only works with addresses in the form "ffff", not
- // "0xffff". This code should always be able to read in addresses
- // written out by the above output() method. Please don't change
- // this without talking to Milo first.
- in >> std::hex >> m_address >> std::dec;
+ return (addr >> number);
}
-Address::Address(const Address& obj)
+Addr
+getOffset(Addr addr)
{
- m_address = obj.m_address;
+ return bitSelect(addr, 0, RubySystem::getBlockSizeBits() - 1);
}
-Address&
-Address::operator=(const Address& obj)
+Addr
+makeLineAddress(Addr addr)
{
- if (this == &obj) {
- // assert(false);
- } else {
- m_address = obj.m_address;
- }
- return *this;
+ return maskLowOrderBits(addr, RubySystem::getBlockSizeBits());
}
-Address
-next_stride_address(const Address& addr, int stride)
+// returns the next stride address based on line address
+Addr
+makeNextStrideAddress(Addr addr, int stride)
{
- Address temp = addr;
- temp.makeNextStrideAddress(stride);
- return temp;
+ return maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
+ + RubySystem::getBlockSizeBytes() * stride;
}
#include <iostream>
#include "base/hashmap.hh"
-#include "mem/ruby/common/TypeDefines.hh"
+#include "base/types.hh"
const uint32_t ADDRESS_WIDTH = 64; // address width in bytes
-class Address;
-typedef Address PhysAddress;
-typedef Address VirtAddress;
-
-class Address
-{
- public:
- Address()
- : m_address(0)
- { }
-
- explicit
- Address(physical_address_t address)
- : m_address(address)
- { }
-
- Address(const Address& obj);
- Address& operator=(const Address& obj);
-
- void setAddress(physical_address_t address) { m_address = address; }
- physical_address_t getAddress() const {return m_address;}
- // selects bits inclusive
- physical_address_t bitSelect(unsigned int small, unsigned int big) const;
- physical_address_t bitRemove(unsigned int small, unsigned int big) const;
- physical_address_t maskLowOrderBits(unsigned int number) const;
- physical_address_t maskHighOrderBits(unsigned int number) const;
- physical_address_t shiftLowOrderBits(unsigned int number) const;
-
- physical_address_t getLineAddress() const;
- physical_address_t getOffset() const;
- void makeLineAddress();
- void makeNextStrideAddress(int stride);
-
- int64 memoryModuleIndex() const;
-
- void print(std::ostream& out) const;
- void output(std::ostream& out) const;
- void input(std::istream& in);
-
- void
- setOffset(int offset)
- {
- // first, zero out the offset bits
- makeLineAddress();
- m_address |= (physical_address_t) offset;
- }
-
- private:
- physical_address_t m_address;
-};
-
-inline Address
-line_address(const Address& addr)
-{
- Address temp(addr);
- temp.makeLineAddress();
- return temp;
-}
-
-inline bool
-operator<(const Address& obj1, const Address& obj2)
-{
- return obj1.getAddress() < obj2.getAddress();
-}
-
-inline std::ostream&
-operator<<(std::ostream& out, const Address& obj)
-{
- obj.print(out);
- out << std::flush;
- return out;
-}
-
-inline bool
-operator==(const Address& obj1, const Address& obj2)
-{
- return (obj1.getAddress() == obj2.getAddress());
-}
-
-inline bool
-operator!=(const Address& obj1, const Address& obj2)
-{
- return (obj1.getAddress() != obj2.getAddress());
-}
-
-// rips bits inclusive
-inline physical_address_t
-Address::bitSelect(unsigned int small, unsigned int big) const
-{
- physical_address_t mask;
- assert(big >= small);
-
- if (big >= ADDRESS_WIDTH - 1) {
- return (m_address >> small);
- } else {
- mask = ~((physical_address_t)~0 << (big + 1));
- // FIXME - this is slow to manipulate a 64-bit number using 32-bits
- physical_address_t partial = (m_address & mask);
- return (partial >> small);
- }
-}
-
-// removes bits inclusive
-inline physical_address_t
-Address::bitRemove(unsigned int small, unsigned int big) const
-{
- physical_address_t mask;
- assert(big >= small);
-
- if (small >= ADDRESS_WIDTH - 1) {
- return m_address;
- } else if (big >= ADDRESS_WIDTH - 1) {
- mask = (physical_address_t)~0 >> small;
- return (m_address & mask);
- } else if (small == 0) {
- mask = (physical_address_t)~0 << big;
- return (m_address & mask);
- } else {
- mask = ~((physical_address_t)~0 << small);
- physical_address_t lower_bits = m_address & mask;
- mask = (physical_address_t)~0 << (big + 1);
- physical_address_t higher_bits = m_address & mask;
-
- // Shift the valid high bits over the removed section
- higher_bits = higher_bits >> (big - small + 1);
- return (higher_bits | lower_bits);
- }
-}
-
-inline physical_address_t
-Address::maskLowOrderBits(unsigned int number) const
-{
- physical_address_t mask;
-
- if (number >= ADDRESS_WIDTH - 1) {
- mask = ~0;
- } else {
- mask = (physical_address_t)~0 << number;
- }
- return (m_address & mask);
-}
-
-inline physical_address_t
-Address::maskHighOrderBits(unsigned int number) const
-{
- physical_address_t mask;
-
- if (number >= ADDRESS_WIDTH - 1) {
- mask = ~0;
- } else {
- mask = (physical_address_t)~0 >> number;
- }
- return (m_address & mask);
-}
-
-inline physical_address_t
-Address::shiftLowOrderBits(unsigned int number) const
-{
- return (m_address >> number);
-}
-
-Address next_stride_address(const Address& addr, int stride);
-
-__hash_namespace_begin
-template <> struct hash<Address>
-{
- size_t
- operator()(const Address &s) const
- {
- return (size_t)s.getAddress();
- }
-};
-__hash_namespace_end
-
-namespace std {
-template <> struct equal_to<Address>
-{
- bool
- operator()(const Address& s1, const Address& s2) const
- {
- return s1 == s2;
- }
-};
-} // namespace std
+// selects bits inclusive
+Addr bitSelect(Addr addr, unsigned int small, unsigned int big);
+Addr bitRemove(Addr addr, unsigned int small, unsigned int big);
+Addr maskLowOrderBits(Addr addr, unsigned int number);
+Addr maskHighOrderBits(Addr addr, unsigned int number);
+Addr shiftLowOrderBits(Addr addr, unsigned int number);
+Addr getOffset(Addr addr);
+Addr makeLineAddress(Addr addr);
+Addr makeNextStrideAddress(Addr addr, int stride);
#endif // __MEM_RUBY_COMMON_ADDRESS_HH__
using m5::stl_helpers::operator<<;
-SubBlock::SubBlock(const Address& addr, int size)
+SubBlock::SubBlock(Addr addr, int size)
{
m_address = addr;
resize(size);
{
int size = getSize();
assert(size > 0);
- int offset = m_address.getOffset();
+ int offset = getOffset(m_address);
for (int i = 0; i < size; i++) {
this->setByte(i, data.getByte(offset + i));
}
{
int size = getSize();
assert(size > 0);
- int offset = m_address.getOffset();
+ int offset = getOffset(m_address);
for (int i = 0; i < size; i++) {
// This will detect crossing a cache line boundary
data.setByte(offset + i, this->getByte(i));
{
public:
SubBlock() { }
- SubBlock(const Address& addr, int size);
+ SubBlock(Addr addr, int size);
~SubBlock() { }
- const Address& getAddress() const { return m_address; }
- void setAddress(const Address& addr) { m_address = addr; }
+ Addr getAddress() const { return m_address; }
+ void setAddress(Addr addr) { m_address = addr; }
int getSize() const { return m_data.size(); }
void resize(int size) { m_data.resize(size); }
void internalMergeFrom(const DataBlock& data);
// Data Members (m_ prefix)
- Address m_address;
+ Addr m_address;
std::vector<uint8_t> m_data;
};
typedef unsigned long long uint64;
typedef long long int64;
-typedef uint64 physical_address_t;
-
typedef unsigned int LinkID;
typedef unsigned int NodeID;
typedef unsigned int SwitchID;
public:
virtual ~AbstractBloomFilter() {};
virtual void clear() = 0;
- virtual void increment(const Address& addr) = 0;
- virtual void decrement(const Address& addr) = 0;
+ virtual void increment(Addr addr) = 0;
+ virtual void decrement(Addr addr) = 0;
virtual void merge(AbstractBloomFilter * other_filter) = 0;
- virtual void set(const Address& addr) = 0;
- virtual void unset(const Address& addr) = 0;
+ virtual void set(Addr addr) = 0;
+ virtual void unset(Addr addr) = 0;
- virtual bool isSet(const Address& addr) = 0;
- virtual int getCount(const Address& addr) = 0;
+ virtual bool isSet(Addr addr) = 0;
+ virtual int getCount(Addr addr) = 0;
virtual int getTotalCount() = 0;
virtual void print(std::ostream& out) const = 0;
- virtual int getIndex(const Address& addr) = 0;
+ virtual int getIndex(Addr addr) = 0;
virtual int readBit(const int index) = 0;
virtual void writeBit(const int index, const int value) = 0;
};
}
void
-BlockBloomFilter::increment(const Address& addr)
+BlockBloomFilter::increment(Addr addr)
{
// Not used
}
void
-BlockBloomFilter::decrement(const Address& addr)
+BlockBloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-BlockBloomFilter::set(const Address& addr)
+BlockBloomFilter::set(Addr addr)
{
int i = get_index(addr);
m_filter[i] = 1;
}
void
-BlockBloomFilter::unset(const Address& addr)
+BlockBloomFilter::unset(Addr addr)
{
int i = get_index(addr);
m_filter[i] = 0;
}
bool
-BlockBloomFilter::isSet(const Address& addr)
+BlockBloomFilter::isSet(Addr addr)
{
int i = get_index(addr);
return (m_filter[i]);
}
int
-BlockBloomFilter::getCount(const Address& addr)
+BlockBloomFilter::getCount(Addr addr)
{
return m_filter[get_index(addr)];
}
}
int
-BlockBloomFilter::getIndex(const Address& addr)
+BlockBloomFilter::getIndex(Addr addr)
{
return get_index(addr);
}
}
int
-BlockBloomFilter::get_index(const Address& addr)
+BlockBloomFilter::get_index(Addr addr)
{
// Pull out some bit field ==> B1
// Pull out additional bits, not the same as B1 ==> B2
// XOR B1 and B2 to get hash index
- physical_address_t block_bits =
- addr.bitSelect(RubySystem::getBlockSizeBits(),
+ Addr block_bits = bitSelect(addr, RubySystem::getBlockSizeBits(),
2 * RubySystem::getBlockSizeBits() - 1);
int offset = 5;
- physical_address_t other_bits =
- addr.bitSelect(2 * RubySystem::getBlockSizeBits() + offset,
+ Addr other_bits = bitSelect(addr,
+ 2 * RubySystem::getBlockSizeBits() + offset,
2 * RubySystem::getBlockSizeBits() + offset +
m_filter_size_bits - 1);
int index = block_bits ^ other_bits;
~BlockBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
void print(std::ostream& out) const;
private:
- int get_index(const Address& addr);
+ int get_index(Addr addr);
std::vector<int> m_filter;
int m_filter_size;
}
void
-BulkBloomFilter::increment(const Address& addr)
+BulkBloomFilter::increment(Addr addr)
{
// Not used
}
void
-BulkBloomFilter::decrement(const Address& addr)
+BulkBloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-BulkBloomFilter::set(const Address& addr)
+BulkBloomFilter::set(Addr addr)
{
// c0 contains the cache index bits
int set_bits = m_sector_bits;
int block_bits = RubySystem::getBlockSizeBits();
- int c0 = addr.bitSelect( block_bits, block_bits + set_bits - 1);
+ int c0 = bitSelect(addr, block_bits, block_bits + set_bits - 1);
// c1 contains the lower m_sector_bits permuted bits
//Address permuted_bits = permute(addr);
//int c1 = permuted_bits.bitSelect(0, set_bits-1);
- int c1 = addr.bitSelect( block_bits+set_bits, (block_bits+2*set_bits) - 1);
+ int c1 = bitSelect(addr, block_bits+set_bits, (block_bits+2*set_bits) - 1);
//assert(c0 < (m_filter_size/2));
//assert(c0 + (m_filter_size/2) < m_filter_size);
//assert(c1 < (m_filter_size/2));
}
void
-BulkBloomFilter::unset(const Address& addr)
+BulkBloomFilter::unset(Addr addr)
{
// not used
}
bool
-BulkBloomFilter::isSet(const Address& addr)
+BulkBloomFilter::isSet(Addr addr)
{
// c0 contains the cache index bits
int set_bits = m_sector_bits;
int block_bits = RubySystem::getBlockSizeBits();
- int c0 = addr.bitSelect( block_bits, block_bits + set_bits - 1);
+ int c0 = bitSelect(addr, block_bits, block_bits + set_bits - 1);
// c1 contains the lower 10 permuted bits
//Address permuted_bits = permute(addr);
//int c1 = permuted_bits.bitSelect(0, set_bits-1);
- int c1 = addr.bitSelect( block_bits+set_bits, (block_bits+2*set_bits) - 1);
+ int c1 = bitSelect(addr, block_bits+set_bits, (block_bits+2*set_bits) - 1);
//assert(c0 < (m_filter_size/2));
//assert(c0 + (m_filter_size/2) < m_filter_size);
//assert(c1 < (m_filter_size/2));
}
int
-BulkBloomFilter::getCount(const Address& addr)
+BulkBloomFilter::getCount(Addr addr)
{
// not used
return 0;
}
int
-BulkBloomFilter::getIndex(const Address& addr)
+BulkBloomFilter::getIndex(Addr addr)
{
return get_index(addr);
}
}
int
-BulkBloomFilter::get_index(const Address& addr)
+BulkBloomFilter::get_index(Addr addr)
{
- return addr.bitSelect(RubySystem::getBlockSizeBits(),
- RubySystem::getBlockSizeBits() +
- m_filter_size_bits - 1);
+ return bitSelect(addr, RubySystem::getBlockSizeBits(),
+ RubySystem::getBlockSizeBits() +
+ m_filter_size_bits - 1);
}
-Address
-BulkBloomFilter::permute(const Address & addr)
+Addr
+BulkBloomFilter::permute(Addr addr)
{
// permutes the original address bits according to Table 5
int block_offset = RubySystem::getBlockSizeBits();
- physical_address_t part1 = addr.bitSelect(block_offset, block_offset + 6),
- part2 = addr.bitSelect(block_offset + 9, block_offset + 9),
- part3 = addr.bitSelect(block_offset + 11, block_offset + 11),
- part4 = addr.bitSelect(block_offset + 17, block_offset + 17),
- part5 = addr.bitSelect(block_offset + 7, block_offset + 8),
- part6 = addr.bitSelect(block_offset + 10, block_offset + 10),
- part7 = addr.bitSelect(block_offset + 12, block_offset + 12),
- part8 = addr.bitSelect(block_offset + 13, block_offset + 13),
- part9 = addr.bitSelect(block_offset + 15, block_offset + 16),
- part10 = addr.bitSelect(block_offset + 18, block_offset + 20),
- part11 = addr.bitSelect(block_offset + 14, block_offset + 14);
-
- physical_address_t result =
+ Addr part1 = bitSelect(addr, block_offset, block_offset + 6),
+ part2 = bitSelect(addr, block_offset + 9, block_offset + 9),
+ part3 = bitSelect(addr, block_offset + 11, block_offset + 11),
+ part4 = bitSelect(addr, block_offset + 17, block_offset + 17),
+ part5 = bitSelect(addr, block_offset + 7, block_offset + 8),
+ part6 = bitSelect(addr, block_offset + 10, block_offset + 10),
+ part7 = bitSelect(addr, block_offset + 12, block_offset + 12),
+ part8 = bitSelect(addr, block_offset + 13, block_offset + 13),
+ part9 = bitSelect(addr, block_offset + 15, block_offset + 16),
+ part10 = bitSelect(addr, block_offset + 18, block_offset + 20),
+ part11 = bitSelect(addr, block_offset + 14, block_offset + 14);
+
+ Addr result =
(part1 << 14) | (part2 << 13) | (part3 << 12) | (part4 << 11) |
(part5 << 9) | (part6 << 8) | (part7 << 7) | (part8 << 6) |
(part9 << 4) | (part10 << 1) | (part11);
// assume 32 bit addresses (both virtual and physical)
// select the remaining high-order 11 bits
- physical_address_t remaining_bits =
- addr.bitSelect(block_offset + 21, 31) << 21;
+ Addr remaining_bits =
+ bitSelect(addr, block_offset + 21, 31) << 21;
result = result | remaining_bits;
- return Address(result);
+ return result;
}
~BulkBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
void print(std::ostream& out) const;
private:
- int get_index(const Address& addr);
- Address permute(const Address & addr);
+ int get_index(Addr addr);
+ Addr permute(Addr addr);
std::vector<int> m_filter;
std::vector<int> m_temp_filter;
}
void
-GenericBloomFilter::increment(const Address& addr)
+GenericBloomFilter::increment(Addr addr)
{
m_filter->increment(addr);
}
void
-GenericBloomFilter::decrement(const Address& addr)
+GenericBloomFilter::decrement(Addr addr)
{
m_filter->decrement(addr);
}
}
void
-GenericBloomFilter::set(const Address& addr)
+GenericBloomFilter::set(Addr addr)
{
m_filter->set(addr);
}
void
-GenericBloomFilter::unset(const Address& addr)
+GenericBloomFilter::unset(Addr addr)
{
m_filter->unset(addr);
}
bool
-GenericBloomFilter::isSet(const Address& addr)
+GenericBloomFilter::isSet(Addr addr)
{
return m_filter->isSet(addr);
}
int
-GenericBloomFilter::getCount(const Address& addr)
+GenericBloomFilter::getCount(Addr addr)
{
return m_filter->getCount(addr);
}
}
int
-GenericBloomFilter::getIndex(const Address& addr)
+GenericBloomFilter::getIndex(Addr addr)
{
return m_filter->getIndex(addr);
}
~GenericBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(GenericBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
AbstractBloomFilter *
getFilter()
{
return m_filter;
}
- bool isSet(const Address& addr);
+ bool isSet(Addr addr);
- int getCount(const Address& addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
}
void
-H3BloomFilter::increment(const Address& addr)
+H3BloomFilter::increment(Addr addr)
{
// Not used
}
void
-H3BloomFilter::decrement(const Address& addr)
+H3BloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-H3BloomFilter::set(const Address& addr)
+H3BloomFilter::set(Addr addr)
{
for (int i = 0; i < m_num_hashes; i++) {
int idx = get_index(addr, i);
}
void
-H3BloomFilter::unset(const Address& addr)
+H3BloomFilter::unset(Addr addr)
{
cout << "ERROR: Unset should never be called in a Bloom filter";
assert(0);
}
bool
-H3BloomFilter::isSet(const Address& addr)
+H3BloomFilter::isSet(Addr addr)
{
bool res = true;
}
int
-H3BloomFilter::getCount(const Address& addr)
+H3BloomFilter::getCount(Addr addr)
{
return isSet(addr)? 1: 0;
}
int
-H3BloomFilter::getIndex(const Address& addr)
+H3BloomFilter::getIndex(Addr addr)
{
return 0;
}
}
int
-H3BloomFilter::get_index(const Address& addr, int i)
+H3BloomFilter::get_index(Addr addr, int i)
{
- uint64 x = addr.getLineAddress();
+ uint64 x = makeLineAddress(addr);
// uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
int y = hash_H3(x,i);
#include <vector>
#include "mem/ruby/common/Address.hh"
+#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/filters/AbstractBloomFilter.hh"
class H3BloomFilter : public AbstractBloomFilter
~H3BloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
void print(std::ostream& out) const;
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
}
private:
- int get_index(const Address& addr, int hashNumber);
+ int get_index(Addr addr, int hashNumber);
int hash_H3(uint64 value, int index);
}
void
-LSB_CountingBloomFilter::increment(const Address& addr)
+LSB_CountingBloomFilter::increment(Addr addr)
{
int i = get_index(addr);
if (m_filter[i] < m_count)
void
-LSB_CountingBloomFilter::decrement(const Address& addr)
+LSB_CountingBloomFilter::decrement(Addr addr)
{
int i = get_index(addr);
if (m_filter[i] > 0)
}
void
-LSB_CountingBloomFilter::set(const Address& addr)
+LSB_CountingBloomFilter::set(Addr addr)
{
// TODO
}
void
-LSB_CountingBloomFilter::unset(const Address& addr)
+LSB_CountingBloomFilter::unset(Addr addr)
{
// TODO
}
bool
-LSB_CountingBloomFilter::isSet(const Address& addr)
+LSB_CountingBloomFilter::isSet(Addr addr)
{
// TODO
return false;
}
int
-LSB_CountingBloomFilter::getCount(const Address& addr)
+LSB_CountingBloomFilter::getCount(Addr addr)
{
return m_filter[get_index(addr)];
}
}
int
-LSB_CountingBloomFilter::getIndex(const Address& addr)
+LSB_CountingBloomFilter::getIndex(Addr addr)
{
return get_index(addr);
}
}
int
-LSB_CountingBloomFilter::get_index(const Address& addr)
+LSB_CountingBloomFilter::get_index(Addr addr)
{
- return addr.bitSelect(RubySystem::getBlockSizeBits(),
- RubySystem::getBlockSizeBits() +
- m_filter_size_bits - 1);
+ return bitSelect(addr, RubySystem::getBlockSizeBits(),
+ RubySystem::getBlockSizeBits() +
+ m_filter_size_bits - 1);
}
~LSB_CountingBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
void print(std::ostream& out) const;
private:
- int get_index(const Address& addr);
+ int get_index(Addr addr);
std::vector<int> m_filter;
int m_filter_size;
}
void
-MultiBitSelBloomFilter::increment(const Address& addr)
+MultiBitSelBloomFilter::increment(Addr addr)
{
// Not used
}
void
-MultiBitSelBloomFilter::decrement(const Address& addr)
+MultiBitSelBloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-MultiBitSelBloomFilter::set(const Address& addr)
+MultiBitSelBloomFilter::set(Addr addr)
{
for (int i = 0; i < m_num_hashes; i++) {
int idx = get_index(addr, i);
}
void
-MultiBitSelBloomFilter::unset(const Address& addr)
+MultiBitSelBloomFilter::unset(Addr addr)
{
cout << "ERROR: Unset should never be called in a Bloom filter";
assert(0);
}
bool
-MultiBitSelBloomFilter::isSet(const Address& addr)
+MultiBitSelBloomFilter::isSet(Addr addr)
{
bool res = true;
}
int
-MultiBitSelBloomFilter::getCount(const Address& addr)
+MultiBitSelBloomFilter::getCount(Addr addr)
{
return isSet(addr)? 1: 0;
}
int
-MultiBitSelBloomFilter::getIndex(const Address& addr)
+MultiBitSelBloomFilter::getIndex(Addr addr)
{
return 0;
}
}
int
-MultiBitSelBloomFilter::get_index(const Address& addr, int i)
+MultiBitSelBloomFilter::get_index(Addr addr, int i)
{
// m_skip_bits is used to perform BitSelect after skipping some
// bits. Used to simulate BitSel hashing on larger than cache-line
// granularities
- uint64 x = (addr.getLineAddress()) >> m_skip_bits;
+ uint64 x = (makeLineAddress(addr) >> m_skip_bits);
int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits);
//36-bit addresses, 6-bit cache lines
#include <vector>
#include "mem/ruby/common/Address.hh"
+#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/filters/AbstractBloomFilter.hh"
class MultiBitSelBloomFilter : public AbstractBloomFilter
~MultiBitSelBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
void print(std::ostream& out) const;
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
}
private:
- int get_index(const Address& addr, int hashNumber);
+ int get_index(Addr addr, int hashNumber);
int hash_bitsel(uint64 value, int index, int jump, int maxBits,
int numBits);
}
void
-MultiGrainBloomFilter::increment(const Address& addr)
+MultiGrainBloomFilter::increment(Addr addr)
{
// Not used
}
void
-MultiGrainBloomFilter::decrement(const Address& addr)
+MultiGrainBloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-MultiGrainBloomFilter::set(const Address& addr)
+MultiGrainBloomFilter::set(Addr addr)
{
int i = get_block_index(addr);
assert(i < m_filter_size);
}
void
-MultiGrainBloomFilter::unset(const Address& addr)
+MultiGrainBloomFilter::unset(Addr addr)
{
// not used
}
bool
-MultiGrainBloomFilter::isSet(const Address& addr)
+MultiGrainBloomFilter::isSet(Addr addr)
{
int i = get_block_index(addr);
assert(i < m_filter_size);
}
int
-MultiGrainBloomFilter::getCount(const Address& addr)
+MultiGrainBloomFilter::getCount(Addr addr)
{
// not used
return 0;
}
int
-MultiGrainBloomFilter::getIndex(const Address& addr)
+MultiGrainBloomFilter::getIndex(Addr addr)
{
return 0;
// TODO
}
int
-MultiGrainBloomFilter::get_block_index(const Address& addr)
+MultiGrainBloomFilter::get_block_index(Addr addr)
{
// grap a chunk of bits after byte offset
- return addr.bitSelect(RubySystem::getBlockSizeBits(),
- RubySystem::getBlockSizeBits() +
- m_filter_size_bits - 1);
+ return bitSelect(addr, RubySystem::getBlockSizeBits(),
+ RubySystem::getBlockSizeBits() +
+ m_filter_size_bits - 1);
}
int
-MultiGrainBloomFilter::get_page_index(const Address & addr)
+MultiGrainBloomFilter::get_page_index(Addr addr)
{
int bits = RubySystem::getBlockSizeBits() + m_filter_size_bits - 1;
// grap a chunk of bits after first chunk
- return addr.bitSelect(bits, bits + m_page_filter_size_bits - 1);
+ return bitSelect(addr, bits, bits + m_page_filter_size_bits - 1);
}
~MultiGrainBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
void print(std::ostream& out) const;
private:
- int get_block_index(const Address& addr);
- int get_page_index(const Address & addr);
+ int get_block_index(Addr addr);
+ int get_page_index(Addr addr);
// The block filter
std::vector<int> m_filter;
}
void
-NonCountingBloomFilter::increment(const Address& addr)
+NonCountingBloomFilter::increment(Addr addr)
{
// Not used
}
void
-NonCountingBloomFilter::decrement(const Address& addr)
+NonCountingBloomFilter::decrement(Addr addr)
{
// Not used
}
}
void
-NonCountingBloomFilter::set(const Address& addr)
+NonCountingBloomFilter::set(Addr addr)
{
int i = get_index(addr);
m_filter[i] = 1;
}
void
-NonCountingBloomFilter::unset(const Address& addr)
+NonCountingBloomFilter::unset(Addr addr)
{
int i = get_index(addr);
m_filter[i] = 0;
}
bool
-NonCountingBloomFilter::isSet(const Address& addr)
+NonCountingBloomFilter::isSet(Addr addr)
{
int i = get_index(addr);
return (m_filter[i]);
int
-NonCountingBloomFilter::getCount(const Address& addr)
+NonCountingBloomFilter::getCount(Addr addr)
{
return m_filter[get_index(addr)];
}
}
int
-NonCountingBloomFilter::getIndex(const Address& addr)
+NonCountingBloomFilter::getIndex(Addr addr)
{
return get_index(addr);
}
}
int
-NonCountingBloomFilter::get_index(const Address& addr)
+NonCountingBloomFilter::get_index(Addr addr)
{
- return addr.bitSelect(RubySystem::getBlockSizeBits() + m_offset,
- RubySystem::getBlockSizeBits() + m_offset +
- m_filter_size_bits - 1);
+ return bitSelect(addr, RubySystem::getBlockSizeBits() + m_offset,
+ RubySystem::getBlockSizeBits() + m_offset +
+ m_filter_size_bits - 1);
}
~NonCountingBloomFilter();
void clear();
- void increment(const Address& addr);
- void decrement(const Address& addr);
+ void increment(Addr addr);
+ void decrement(Addr addr);
void merge(AbstractBloomFilter * other_filter);
- void set(const Address& addr);
- void unset(const Address& addr);
+ void set(Addr addr);
+ void unset(Addr addr);
- bool isSet(const Address& addr);
- int getCount(const Address& addr);
+ bool isSet(Addr addr);
+ int getCount(Addr addr);
int getTotalCount();
- int getIndex(const Address& addr);
+ int getIndex(Addr addr);
int readBit(const int index);
void writeBit(const int index, const int value);
}
private:
- int get_index(const Address& addr);
+ int get_index(Addr addr);
std::vector<int> m_filter;
int m_filter_size;
}
void
-MessageBuffer::reanalyzeMessages(const Address& addr)
+MessageBuffer::reanalyzeMessages(Addr addr)
{
DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
assert(m_stall_msg_map.count(addr) > 0);
}
void
-MessageBuffer::stallMessage(const Address& addr)
+MessageBuffer::stallMessage(Addr addr)
{
DPRINTF(RubyQueue, "Stalling due to %s\n", addr);
assert(isReady());
- assert(addr.getOffset() == 0);
+ assert(getOffset(addr) == 0);
MsgPtr message = m_prio_heap.front();
dequeue();
typedef MessageBufferParams Params;
MessageBuffer(const Params *p);
- void reanalyzeMessages(const Address& addr);
+ void reanalyzeMessages(Addr addr);
void reanalyzeAllMessages();
- void stallMessage(const Address& addr);
+ void stallMessage(Addr addr);
// TRUE if head of queue timestamp <= SystemTime
bool isReady() const;
// use a std::map for the stalled messages as this container is
// sorted and ensures a well-defined iteration order
- typedef std::map< Address, std::list<MsgPtr> > StallMsgMapType;
+ typedef std::map<Addr, std::list<MsgPtr> > StallMsgMapType;
StallMsgMapType m_stall_msg_map;
{ }
~AccessTraceForAddress();
- void setAddress(const Address& addr) { m_addr = addr; }
+ void setAddress(Addr addr) { m_addr = addr; }
void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss);
int getTotal() const;
int getSharing() const { return m_sharing; }
int getTouchedBy() const { return m_touched_by.count(); }
- const Address& getAddress() const { return m_addr; }
+ Addr getAddress() const { return m_addr; }
void addSample(int value);
void print(std::ostream& out) const;
}
private:
- Address m_addr;
+ Addr m_addr;
uint64 m_loads;
uint64 m_stores;
uint64 m_atomics;
// Helper functions
AccessTraceForAddress&
-lookupTraceForAddress(const Address& addr, AddressMap& record_map)
+lookupTraceForAddress(Addr addr, AddressMap& record_map)
{
// we create a static default object here that is used to insert
// since the insertion will create a copy of the object in the
}
void
-AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
+AddressProfiler::profileGetX(Addr datablock, Addr PC,
const Set& owner, const Set& sharers,
NodeID requestor)
{
}
void
-AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
+AddressProfiler::profileGetS(Addr datablock, Addr PC,
const Set& owner, const Set& sharers,
NodeID requestor)
{
}
void
-AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
+AddressProfiler::addTraceSample(Addr data_addr, Addr pc_addr,
RubyRequestType type,
RubyAccessMode access_mode, NodeID id,
bool sharing_miss)
}
// record data address trace info
- data_addr.makeLineAddress();
+ data_addr = makeLineAddress(data_addr);
lookupTraceForAddress(data_addr, m_dataAccessTrace).
update(type, access_mode, id, sharing_miss);
// record macro data address trace info
// 6 for datablock, 4 to make it 16x more coarse
- Address macro_addr(data_addr.maskLowOrderBits(10));
+ Addr macro_addr = maskLowOrderBits(data_addr, 10);
lookupTraceForAddress(macro_addr, m_macroBlockAccessTrace).
update(type, access_mode, id, sharing_miss);
}
void
-AddressProfiler::profileRetry(const Address& data_addr, AccessType type,
- int count)
+AddressProfiler::profileRetry(Addr data_addr, AccessType type, int count)
{
m_retryProfileHisto.add(count);
if (type == AccessType_Read) {
class AddressProfiler
{
public:
- typedef m5::hash_map<Address, AccessTraceForAddress> AddressMap;
+ typedef m5::hash_map<Addr, AccessTraceForAddress> AddressMap;
public:
AddressProfiler(int num_of_sequencers, Profiler *profiler);
void printStats(std::ostream& out) const;
void clearStats();
- void addTraceSample(Address data_addr, Address pc_addr,
+ void addTraceSample(Addr data_addr, Addr pc_addr,
RubyRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss);
- void profileRetry(const Address& data_addr, AccessType type, int count);
- void profileGetX(const Address& datablock, const Address& PC,
+ void profileRetry(Addr data_addr, AccessType type, int count);
+ void profileGetX(Addr datablock, Addr PC,
const Set& owner, const Set& sharers, NodeID requestor);
- void profileGetS(const Address& datablock, const Address& PC,
+ void profileGetS(Addr datablock, Addr PC,
const Set& owner, const Set& sharers, NodeID requestor);
void print(std::ostream& out) const;
int m_num_of_sequencers;
};
-AccessTraceForAddress& lookupTraceForAddress(const Address& addr,
+AccessTraceForAddress& lookupTraceForAddress(Addr addr,
AddressProfiler::AddressMap&
record_map);
Histogram* StoreTrace::s_store_last_to_stolen_ptr = NULL;
Histogram* StoreTrace::s_store_first_to_last_ptr = NULL;
-StoreTrace::StoreTrace(const Address& addr)
+StoreTrace::StoreTrace(Addr addr)
: m_store_count(-1), m_store_first_to_stolen(-1),
m_store_last_to_stolen(-1), m_store_first_to_last(-1)
{
{
public:
StoreTrace() { }
- explicit StoreTrace(const Address& addr);
+ explicit StoreTrace(Addr addr);
~StoreTrace();
void store(NodeID node);
static Histogram* s_store_last_to_stolen_ptr;
static Histogram* s_store_first_to_last_ptr;
- Address m_addr;
+ Addr m_addr;
NodeID m_last_writer;
Tick m_first_store;
Tick m_last_store;
AbstractCacheEntry::AbstractCacheEntry()
{
m_Permission = AccessPermission_NotPresent;
- m_Address.setAddress(0);
+ m_Address = 0;
m_locked = -1;
}
{ panic("getDataBlk() not implemented!"); }
- Address m_Address; // Address of this block, required by CacheMemory
+ Addr m_Address; // Address of this block, required by CacheMemory
int m_locked; // Holds info whether the address is locked,
// required for implementing LL/SC
};
}
void
-AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
+AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
{
if (m_waiting_buffers.count(addr) == 0) {
MsgVecType* msgVec = new MsgVecType;
}
void
-AbstractController::wakeUpBuffers(Address addr)
+AbstractController::wakeUpBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
}
void
-AbstractController::wakeUpAllBuffers(Address addr)
+AbstractController::wakeUpAllBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
}
void
-AbstractController::blockOnQueue(Address addr, MessageBuffer* port)
+AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
{
m_is_blocking = true;
m_block_map[addr] = port;
}
void
-AbstractController::unblock(Address addr)
+AbstractController::unblock(Addr addr)
{
m_block_map.erase(addr);
if (m_block_map.size() == 0) {
}
void
-AbstractController::queueMemoryRead(const MachineID &id, Address addr,
+AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
Cycles latency)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createRead(req);
}
void
-AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
+AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
Cycles latency, const DataBlock &block)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
}
void
-AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr,
+AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
Cycles latency,
const DataBlock &block, int size)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
uint8_t *newData = new uint8_t[size];
pkt->dataDynamic(newData);
- memcpy(newData, block.getData(addr.getOffset(), size), size);
+ memcpy(newData, block.getData(getOffset(addr), size), size);
SenderState *s = new SenderState(id);
pkt->pushSenderState(s);
assert(pkt->isResponse());
std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
- (*msg).m_addr.setAddress(pkt->getAddr());
+ (*msg).m_addr = pkt->getAddr();
(*msg).m_Sender = m_machineID;
SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
// return instance name
- void blockOnQueue(Address, MessageBuffer*);
- void unblock(Address);
+ void blockOnQueue(Addr, MessageBuffer*);
+ void unblock(Addr);
virtual MessageBuffer* getMandatoryQueue() const = 0;
virtual MessageBuffer* getMemoryQueue() const = 0;
- virtual AccessPermission getAccessPermission(const Address& addr) = 0;
+ virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
virtual void print(std::ostream & out) const = 0;
virtual void wakeup() = 0;
//! These functions are used by ruby system to read/write the data blocks
//! that exist with in the controller.
- virtual void functionalRead(const Address &addr, PacketPtr) = 0;
+ virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
void functionalMemoryRead(PacketPtr);
//! The return value indicates the number of messages written with the
//! data from the packet.
virtual int functionalWriteBuffers(PacketPtr&) = 0;
- virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
+ virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
int functionalMemoryWrite(PacketPtr);
//! Function for enqueuing a prefetch request
- virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
+ virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
{ fatal("Prefetches not implemented!");}
//! Function for collating statistics from all the controllers of this
BaseMasterPort& getMasterPort(const std::string& if_name,
PortID idx = InvalidPortID);
- void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
- void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
+ void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
+ void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
const DataBlock &block);
- void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
+ void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
const DataBlock &block, int size);
void recvTimingResp(PacketPtr pkt);
//! Profiles the delay associated with messages.
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
- void stallBuffer(MessageBuffer* buf, Address addr);
- void wakeUpBuffers(Address addr);
- void wakeUpAllBuffers(Address addr);
+ void stallBuffer(MessageBuffer* buf, Addr addr);
+ void wakeUpBuffers(Addr addr);
+ void wakeUpAllBuffers(Addr addr);
void wakeUpAllBuffers();
protected:
Network* m_net_ptr;
bool m_is_blocking;
- std::map<Address, MessageBuffer*> m_block_map;
+ std::map<Addr, MessageBuffer*> m_block_map;
typedef std::vector<MessageBuffer*> MsgVecType;
typedef std::set<MessageBuffer*> MsgBufType;
- typedef std::map< Address, MsgVecType* > WaitingBufType;
+ typedef std::map<Addr, MsgVecType* > WaitingBufType;
WaitingBufType m_waiting_buffers;
unsigned int m_in_ports;
Addr wBase = pkt->getAddr();
Addr wTail = wBase + pkt->getSize();
- Addr mBase = m_PhysicalAddress.getAddress();
+ Addr mBase = m_PhysicalAddress;
Addr mTail = mBase + m_Size;
const uint8_t * pktData = pkt->getConstPtr<uint8_t>();
class RubyRequest : public Message
{
public:
- Address m_PhysicalAddress;
- Address m_LineAddress;
+ Addr m_PhysicalAddress;
+ Addr m_LineAddress;
RubyRequestType m_Type;
- Address m_ProgramCounter;
+ Addr m_ProgramCounter;
RubyAccessMode m_AccessMode;
int m_Size;
PrefetchBit m_Prefetch;
pkt(_pkt),
m_contextId(_proc_id)
{
- m_LineAddress = m_PhysicalAddress;
- m_LineAddress.makeLineAddress();
+ m_LineAddress = makeLineAddress(m_PhysicalAddress);
}
RubyRequest(Tick curTime) : Message(curTime) {}
MsgPtr clone() const
{ return std::shared_ptr<Message>(new RubyRequest(*this)); }
- const Address& getLineAddress() const { return m_LineAddress; }
- const Address& getPhysicalAddress() const { return m_PhysicalAddress; }
+ Addr getLineAddress() const { return m_LineAddress; }
+ Addr getPhysicalAddress() const { return m_PhysicalAddress; }
const RubyRequestType& getType() const { return m_Type; }
- const Address& getProgramCounter() const { return m_ProgramCounter; }
+ Addr getProgramCounter() const { return m_ProgramCounter; }
const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
const int& getSize() const { return m_Size; }
const PrefetchBit& getPrefetch() const { return m_Prefetch; }
return out;
}
-#endif
+#endif // __MEM_RUBY_SLICC_INTERFACE_RUBY_REQUEST_HH__
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system
inline NodeID
-map_Address_to_DirectoryNode(const Address& addr)
+map_Address_to_DirectoryNode(Addr addr)
{
return DirectoryMemory::mapAddressToDirectoryVersion(addr);
}
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system
inline MachineID
-map_Address_to_Directory(const Address &addr)
+map_Address_to_Directory(Addr addr)
{
MachineID mach =
{MachineType_Directory, map_Address_to_DirectoryNode(addr)};
}
inline MachineID
-mapAddressToRange(const Address & addr, MachineType type, int low_bit,
+mapAddressToRange(Addr addr, MachineType type, int low_bit,
int num_bits, int cluster_id = 0)
{
MachineID mach = {type, 0};
if (num_bits == 0)
mach.num = cluster_id;
else
- mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1)
+ mach.num = bitSelect(addr, low_bit, low_bit + num_bits - 1)
+ (1 << num_bits) * cluster_id;
return mach;
}
#include <cassert>
#include "debug/RubySlicc.hh"
+#include "mem/packet.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
-#include "mem/packet.hh"
+#include "mem/ruby/common/TypeDefines.hh"
inline Cycles zero_time() { return Cycles(0); }
}
inline int
-addressToInt(Address addr)
-{
- assert(!(addr.getAddress() & 0xffffffff00000000));
-
- return (int)addr.getAddress();
-}
-
-// Appends an offset to an address
-inline Address
-setOffset(Address addr, int offset)
+addressToInt(Addr addr)
{
- Address result = addr;
- result.setOffset(offset);
- return result;
-}
-
-// Makes an address into a line address
-inline Address
-makeLineAddress(Address addr)
-{
- Address result = addr;
- result.makeLineAddress();
- return result;
-}
-
-inline int
-addressOffset(Address addr)
-{
- return addr.getOffset();
+ assert(!(addr & 0xffffffff00000000));
+ return addr;
}
inline int
* returned if the data block was read, otherwise false is returned.
*/
inline bool
-testAndRead(Address addr, DataBlock& blk, Packet *pkt)
+testAndRead(Addr addr, DataBlock& blk, Packet *pkt)
{
- Address pktLineAddr(pkt->getAddr());
- pktLineAddr.makeLineAddress();
-
- Address lineAddr = addr;
- lineAddr.makeLineAddress();
+ Addr pktLineAddr = makeLineAddress(pkt->getAddr());
+ Addr lineAddr = makeLineAddress(addr);
if (pktLineAddr == lineAddr) {
uint8_t *data = pkt->getPtr<uint8_t>();
unsigned int size_in_bytes = pkt->getSize();
- unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
+ unsigned startByte = pkt->getAddr() - lineAddr;
for (unsigned i = 0; i < size_in_bytes; ++i) {
data[i] = blk.getByte(i + startByte);
* returned if the data block was written, otherwise false is returned.
*/
inline bool
-testAndWrite(Address addr, DataBlock& blk, Packet *pkt)
+testAndWrite(Addr addr, DataBlock& blk, Packet *pkt)
{
- Address pktLineAddr(pkt->getAddr());
- pktLineAddr.makeLineAddress();
-
- Address lineAddr = addr;
- lineAddr.makeLineAddress();
+ Addr pktLineAddr = makeLineAddress(pkt->getAddr());
+ Addr lineAddr = makeLineAddress(addr);
if (pktLineAddr == lineAddr) {
const uint8_t *data = pkt->getConstPtr<uint8_t>();
unsigned int size_in_bytes = pkt->getSize();
- unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
+ unsigned startByte = pkt->getAddr() - lineAddr;
for (unsigned i = 0; i < size_in_bytes; ++i) {
blk.setByte(i + startByte, data[i]);
// convert a Address to its location in the cache
int64
-CacheMemory::addressToCacheSet(const Address& address) const
+CacheMemory::addressToCacheSet(Addr address) const
{
- assert(address == line_address(address));
- return address.bitSelect(m_start_index_bit,
- m_start_index_bit + m_cache_num_set_bits - 1);
+ assert(address == makeLineAddress(address));
+ return bitSelect(address, m_start_index_bit,
+ m_start_index_bit + m_cache_num_set_bits - 1);
}
// Given a cache index: returns the index of the tag in a set.
// returns -1 if the tag is not found.
int
-CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
+CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const
{
- assert(tag == line_address(tag));
+ assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
+ m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
if (it != m_tag_index.end())
if (m_cache[cacheSet][it->second]->m_Permission !=
AccessPermission_NotPresent)
// returns -1 if the tag is not found.
int
CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
- const Address& tag) const
+ Addr tag) const
{
- assert(tag == line_address(tag));
+ assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
+ m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
if (it != m_tag_index.end())
return it->second;
return -1; // Not found
// Given an unique cache block identifier (idx): return the valid address
// stored by the cache block. If the block is invalid/notpresent, the
// function returns the 0 address
-Address
+Addr
CacheMemory::getAddressAtIdx(int idx) const
{
- Address tmp(0);
+ Addr tmp(0);
int set = idx / m_cache_assoc;
assert(set < m_cache_num_sets);
}
bool
-CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
+CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
}
bool
-CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
+CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
// tests to see if an address is present in the cache
bool
-CacheMemory::isTagPresent(const Address& address) const
+CacheMemory::isTagPresent(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
// a) a tag match on this address or there is
// b) an unused line in the same cache "way"
bool
-CacheMemory::cacheAvail(const Address& address) const
+CacheMemory::cacheAvail(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
}
AbstractCacheEntry*
-CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch)
+CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(!isTagPresent(address));
assert(cacheAvail(address));
DPRINTF(RubyCache, "address: %s\n", address);
}
void
-CacheMemory::deallocate(const Address& address)
+CacheMemory::deallocate(Addr address)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(isTagPresent(address));
DPRINTF(RubyCache, "address: %s\n", address);
int64 cacheSet = addressToCacheSet(address);
}
// Returns with the physical address of the conflicting cache line
-Address
-CacheMemory::cacheProbe(const Address& address) const
+Addr
+CacheMemory::cacheProbe(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(!cacheAvail(address));
int64 cacheSet = addressToCacheSet(address);
// looks an address up in the cache
AbstractCacheEntry*
-CacheMemory::lookup(const Address& address)
+CacheMemory::lookup(Addr address)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if(loc == -1) return NULL;
// looks an address up in the cache
const AbstractCacheEntry*
-CacheMemory::lookup(const Address& address) const
+CacheMemory::lookup(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if(loc == -1) return NULL;
// Sets the most recently used bit for a cache block
void
-CacheMemory::setMRU(const Address& address)
+CacheMemory::setMRU(Addr address)
{
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
}
if (request_type != RubyRequestType_NULL) {
- tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(),
+ tr->addRecord(cntrl, m_cache[i][j]->m_Address,
0, request_type,
m_replacementPolicy_ptr->getLastAccess(i, j),
m_cache[i][j]->getDataBlk());
}
void
-CacheMemory::setLocked(const Address& address, int context)
+CacheMemory::setLocked(Addr address, int context)
{
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
}
void
-CacheMemory::clearLocked(const Address& address)
+CacheMemory::clearLocked(Addr address)
{
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
}
bool
-CacheMemory::isLocked(const Address& address, int context)
+CacheMemory::isLocked(Addr address, int context)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
int64 cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
// assumption: SLICC generated files will only call this function
// once **all** resources are granted
void
-CacheMemory::recordRequestType(CacheRequestType requestType, Address addr)
+CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr)
{
DPRINTF(RubyStats, "Recorded statistic: %s\n",
CacheRequestType_to_string(requestType));
}
bool
-CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
+CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
{
if (!m_resource_stalls) {
return true;
// Public Methods
// perform a cache access and see if we hit or not. Return true on a hit.
- bool tryCacheAccess(const Address& address, RubyRequestType type,
+ bool tryCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr);
// similar to above, but doesn't require full access check
- bool testCacheAccess(const Address& address, RubyRequestType type,
+ bool testCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr);
// tests to see if an address is present in the cache
- bool isTagPresent(const Address& address) const;
+ bool isTagPresent(Addr address) const;
// Returns true if there is:
// a) a tag match on this address or there is
// b) an unused line in the same cache "way"
- bool cacheAvail(const Address& address) const;
+ bool cacheAvail(Addr address) const;
// find an unused entry and sets the tag appropriate for the address
- AbstractCacheEntry* allocate(const Address& address,
+ AbstractCacheEntry* allocate(Addr address,
AbstractCacheEntry* new_entry, bool touch);
- AbstractCacheEntry* allocate(const Address& address,
- AbstractCacheEntry* new_entry)
+ AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
{
return allocate(address, new_entry, true);
}
- void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
+ void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
{
allocate(address, new_entry, true);
}
// Explicitly free up this address
- void deallocate(const Address& address);
+ void deallocate(Addr address);
// Returns with the physical address of the conflicting cache line
- Address cacheProbe(const Address& address) const;
+ Addr cacheProbe(Addr address) const;
// looks an address up in the cache
- AbstractCacheEntry* lookup(const Address& address);
- const AbstractCacheEntry* lookup(const Address& address) const;
+ AbstractCacheEntry* lookup(Addr address);
+ const AbstractCacheEntry* lookup(Addr address) const;
Cycles getTagLatency() const { return tagArray.getLatency(); }
Cycles getDataLatency() const { return dataArray.getLatency(); }
void recordCacheContents(int cntrl, CacheRecorder* tr) const;
// Set this address to most recently used
- void setMRU(const Address& address);
+ void setMRU(Addr address);
- void setLocked (const Address& addr, int context);
- void clearLocked (const Address& addr);
- bool isLocked (const Address& addr, int context);
+ void setLocked (Addr addr, int context);
+ void clearLocked (Addr addr);
+ bool isLocked (Addr addr, int context);
// Print cache contents
void print(std::ostream& out) const;
void printData(std::ostream& out) const;
void regStats();
- bool checkResourceAvailable(CacheResourceType res, Address addr);
- void recordRequestType(CacheRequestType requestType, Address addr);
+ bool checkResourceAvailable(CacheResourceType res, Addr addr);
+ void recordRequestType(CacheRequestType requestType, Addr addr);
public:
Stats::Scalar m_demand_hits;
int getCacheSize() const { return m_cache_size; }
int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
- Address getAddressAtIdx(int idx) const;
+ Addr getAddressAtIdx(int idx) const;
private:
// convert a Address to its location in the cache
- int64 addressToCacheSet(const Address& address) const;
+ int64 addressToCacheSet(Addr address) const;
// Given a cache tag: returns the index of the tag in a set.
// returns -1 if the tag is not found.
- int findTagInSet(int64 line, const Address& tag) const;
- int findTagInSetIgnorePermissions(int64 cacheSet,
- const Address& tag) const;
+ int findTagInSet(int64 line, Addr tag) const;
+ int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
// Private copy constructor and assignment operator
CacheMemory(const CacheMemory& obj);
// The first index is the # of cache lines.
// The second index is the the amount associativity.
- m5::hash_map<Address, int> m_tag_index;
+ m5::hash_map<Addr, int> m_tag_index;
std::vector<std::vector<AbstractCacheEntry*> > m_cache;
AbstractReplacementPolicy *m_replacementPolicy_ptr;
DirectoryMemory::~DirectoryMemory()
{
// free up all the directory entries
- for (uint64 i = 0; i < m_num_entries; i++) {
+ for (uint64_t i = 0; i < m_num_entries; i++) {
if (m_entries[i] != NULL) {
delete m_entries[i];
}
delete [] m_entries;
}
-uint64
-DirectoryMemory::mapAddressToDirectoryVersion(PhysAddress address)
+uint64_t
+DirectoryMemory::mapAddressToDirectoryVersion(Addr address)
{
if (m_num_directories_bits == 0)
return 0;
- uint64 ret = address.bitSelect(m_numa_high_bit - m_num_directories_bits + 1,
- m_numa_high_bit);
+ uint64_t ret = bitSelect(address,
+ m_numa_high_bit - m_num_directories_bits + 1,
+ m_numa_high_bit);
return ret;
}
bool
-DirectoryMemory::isPresent(PhysAddress address)
+DirectoryMemory::isPresent(Addr address)
{
bool ret = (mapAddressToDirectoryVersion(address) == m_version);
return ret;
}
-uint64
-DirectoryMemory::mapAddressToLocalIdx(PhysAddress address)
+uint64_t
+DirectoryMemory::mapAddressToLocalIdx(Addr address)
{
- uint64 ret;
+ uint64_t ret;
if (m_num_directories_bits > 0) {
- ret = address.bitRemove(m_numa_high_bit - m_num_directories_bits + 1,
- m_numa_high_bit);
+ ret = bitRemove(address, m_numa_high_bit - m_num_directories_bits + 1,
+ m_numa_high_bit);
} else {
- ret = address.getAddress();
+ ret = address;
}
return ret >> (RubySystem::getBlockSizeBits());
}
AbstractEntry*
-DirectoryMemory::lookup(PhysAddress address)
+DirectoryMemory::lookup(Addr address)
{
assert(isPresent(address));
DPRINTF(RubyCache, "Looking up address: %s\n", address);
}
AbstractEntry*
-DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry)
+DirectoryMemory::allocate(Addr address, AbstractEntry *entry)
{
assert(isPresent(address));
- uint64 idx;
+ uint64_t idx;
DPRINTF(RubyCache, "Looking up address: %s\n", address);
idx = mapAddressToLocalIdx(address);
void init();
- uint64 mapAddressToLocalIdx(PhysAddress address);
- static uint64 mapAddressToDirectoryVersion(PhysAddress address);
+ uint64_t mapAddressToLocalIdx(Addr address);
+ static uint64_t mapAddressToDirectoryVersion(Addr address);
- uint64 getSize() { return m_size_bytes; }
+ uint64_t getSize() { return m_size_bytes; }
- bool isPresent(PhysAddress address);
- AbstractEntry* lookup(PhysAddress address);
- AbstractEntry* allocate(const PhysAddress& address,
- AbstractEntry* new_entry);
+ bool isPresent(Addr address);
+ AbstractEntry *lookup(Addr address);
+ AbstractEntry *allocate(Addr address, AbstractEntry* new_entry);
void print(std::ostream& out) const;
void recordRequestType(DirectoryRequestType requestType);
AbstractEntry **m_entries;
// int m_size; // # of memory module blocks this directory is
// responsible for
- uint64 m_size_bytes;
- uint64 m_size_bits;
- uint64 m_num_entries;
+ uint64_t m_size_bytes;
+ uint64_t m_size_bits;
+ uint64_t m_num_entries;
int m_version;
static int m_num_directories;
public:
// old constructor
MemoryNode(const Cycles& time, int counter, const PacketPtr p,
- const physical_address_t addr, const bool is_mem_read)
+ Addr addr, const bool is_mem_read)
: m_time(time), pkt(p)
{
m_msg_counter = counter;
// new constructor
MemoryNode(const Cycles& time, const PacketPtr p,
- const physical_address_t addr, const bool is_mem_read,
+ Addr addr, const bool is_mem_read,
const bool is_dirty_wb)
: m_time(time), pkt(p)
{
Cycles m_time;
int m_msg_counter;
PacketPtr pkt;
- physical_address_t m_addr;
+ Addr m_addr;
bool m_is_mem_read;
bool m_is_dirty_wb;
};
PerfectCacheMemory();
// tests to see if an address is present in the cache
- bool isTagPresent(const Address& address) const;
+ bool isTagPresent(Addr address) const;
// Returns true if there is:
// a) a tag match on this address or there is
// b) an Invalid line in the same cache "way"
- bool cacheAvail(const Address& address) const;
+ bool cacheAvail(Addr address) const;
// find an Invalid entry and sets the tag appropriate for the address
- void allocate(const Address& address);
+ void allocate(Addr address);
- void deallocate(const Address& address);
+ void deallocate(Addr address);
// Returns with the physical address of the conflicting cache line
- Address cacheProbe(const Address& newAddress) const;
+ Addr cacheProbe(Addr newAddress) const;
// looks an address up in the cache
- ENTRY* lookup(const Address& address);
- const ENTRY* lookup(const Address& address) const;
+ ENTRY* lookup(Addr address);
+ const ENTRY* lookup(Addr address) const;
// Get/Set permission of cache block
- AccessPermission getPermission(const Address& address) const;
- void changePermission(const Address& address, AccessPermission new_perm);
+ AccessPermission getPermission(Addr address) const;
+ void changePermission(Addr address, AccessPermission new_perm);
// Print cache contents
void print(std::ostream& out) const;
PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
// Data Members (m_prefix)
- m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map;
+ m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
};
template<class ENTRY>
// tests to see if an address is present in the cache
template<class ENTRY>
inline bool
-PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
+PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const
{
- return m_map.count(line_address(address)) > 0;
+ return m_map.count(makeLineAddress(address)) > 0;
}
template<class ENTRY>
inline bool
-PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
+PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const
{
return true;
}
// appropriate for the address
template<class ENTRY>
inline void
-PerfectCacheMemory<ENTRY>::allocate(const Address& address)
+PerfectCacheMemory<ENTRY>::allocate(Addr address)
{
PerfectCacheLineState<ENTRY> line_state;
line_state.m_permission = AccessPermission_Invalid;
line_state.m_entry = ENTRY();
- m_map[line_address(address)] = line_state;
+ m_map[makeLineAddress(address)] = line_state;
}
// deallocate entry
template<class ENTRY>
inline void
-PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
+PerfectCacheMemory<ENTRY>::deallocate(Addr address)
{
- m_map.erase(line_address(address));
+ m_map.erase(makeLineAddress(address));
}
// Returns with the physical address of the conflicting cache line
template<class ENTRY>
-inline Address
-PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
+inline Addr
+PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const
{
panic("cacheProbe called in perfect cache");
return newAddress;
// looks an address up in the cache
template<class ENTRY>
inline ENTRY*
-PerfectCacheMemory<ENTRY>::lookup(const Address& address)
+PerfectCacheMemory<ENTRY>::lookup(Addr address)
{
- return &m_map[line_address(address)].m_entry;
+ return &m_map[makeLineAddress(address)].m_entry;
}
// looks an address up in the cache
template<class ENTRY>
inline const ENTRY*
-PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
+PerfectCacheMemory<ENTRY>::lookup(Addr address) const
{
- return &m_map[line_address(address)].m_entry;
+ return &m_map[makeLineAddress(address)].m_entry;
}
template<class ENTRY>
inline AccessPermission
-PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
+PerfectCacheMemory<ENTRY>::getPermission(Addr address) const
{
- return m_map[line_address(address)].m_permission;
+ return m_map[makeLineAddress(address)].m_permission;
}
template<class ENTRY>
inline void
-PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
+PerfectCacheMemory<ENTRY>::changePermission(Addr address,
AccessPermission new_perm)
{
- Address line_address = address;
- line_address.makeLineAddress();
+ Addr line_address = makeLineAddress(address);
PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
line_state.m_permission = new_perm;
}
}
void
-PersistentTable::persistentRequestLock(const Address& address,
+PersistentTable::persistentRequestLock(Addr address,
MachineID locker,
AccessType type)
{
MachineID locker = (MachineID) persistent_randomize[llocker];
#endif
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
static const PersistentTableEntry dflt;
pair<AddressMap::iterator, bool> r =
}
void
-PersistentTable::persistentRequestUnlock(const Address& address,
+PersistentTable::persistentRequestUnlock(Addr address,
MachineID unlocker)
{
#if 0
MachineID unlocker = (MachineID) persistent_randomize[uunlocker];
#endif
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(m_map.count(address));
PersistentTableEntry& entry = m_map[address];
}
bool
-PersistentTable::okToIssueStarving(const Address& address,
+PersistentTable::okToIssueStarving(Addr address,
MachineID machId) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::const_iterator i = m_map.find(address);
if (i == m_map.end()) {
}
MachineID
-PersistentTable::findSmallest(const Address& address) const
+PersistentTable::findSmallest(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::const_iterator i = m_map.find(address);
assert(i != m_map.end());
const PersistentTableEntry& entry = i->second;
}
AccessType
-PersistentTable::typeOfSmallest(const Address& address) const
+PersistentTable::typeOfSmallest(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::const_iterator i = m_map.find(address);
assert(i != m_map.end());
const PersistentTableEntry& entry = i->second;
}
void
-PersistentTable::markEntries(const Address& address)
+PersistentTable::markEntries(Addr address)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::iterator i = m_map.find(address);
if (i == m_map.end())
return;
}
bool
-PersistentTable::isLocked(const Address& address) const
+PersistentTable::isLocked(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
// If an entry is present, it must be locked
return m_map.count(address) > 0;
}
int
-PersistentTable::countStarvingForAddress(const Address& address) const
+PersistentTable::countStarvingForAddress(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::const_iterator i = m_map.find(address);
if (i == m_map.end())
return 0;
}
int
-PersistentTable::countReadStarvingForAddress(const Address& address) const
+PersistentTable::countReadStarvingForAddress(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
AddressMap::const_iterator i = m_map.find(address);
if (i == m_map.end())
return 0;
~PersistentTable();
// Public Methods
- void persistentRequestLock(const Address& address, MachineID locker,
+ void persistentRequestLock(Addr address, MachineID locker,
AccessType type);
- void persistentRequestUnlock(const Address& address, MachineID unlocker);
- bool okToIssueStarving(const Address& address, MachineID machID) const;
- MachineID findSmallest(const Address& address) const;
- AccessType typeOfSmallest(const Address& address) const;
- void markEntries(const Address& address);
- bool isLocked(const Address& addr) const;
- int countStarvingForAddress(const Address& addr) const;
- int countReadStarvingForAddress(const Address& addr) const;
+ void persistentRequestUnlock(Addr address, MachineID unlocker);
+ bool okToIssueStarving(Addr address, MachineID machID) const;
+ MachineID findSmallest(Addr address) const;
+ AccessType typeOfSmallest(Addr address) const;
+ void markEntries(Addr address);
+ bool isLocked(Addr addr) const;
+ int countStarvingForAddress(Addr addr) const;
+ int countReadStarvingForAddress(Addr addr) const;
void print(std::ostream& out) const;
PersistentTable& operator=(const PersistentTable& obj);
// Data Members (m_prefix)
- typedef m5::hash_map<Address, PersistentTableEntry> AddressMap;
+ typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap;
AddressMap m_map;
};
m_array(p->num_streams), m_train_misses(p->train_misses),
m_num_startup_pfs(p->num_startup_pfs), m_num_unit_filters(p->unit_filter),
m_num_nonunit_filters(p->nonunit_filter),
- m_unit_filter(p->unit_filter, Address(0)),
- m_negative_filter(p->unit_filter, Address(0)),
- m_nonunit_filter(p->nonunit_filter, Address(0)),
+ m_unit_filter(p->unit_filter, 0),
+ m_negative_filter(p->unit_filter, 0),
+ m_nonunit_filter(p->nonunit_filter, 0),
m_prefetch_cross_pages(p->cross_page),
m_page_shift(p->sys->getPageShift())
{
}
void
-Prefetcher::observeMiss(const Address& address, const RubyRequestType& type)
+Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
{
DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address);
- Address line_addr = line_address(address);
+ Addr line_addr = makeLineAddress(address);
numMissObserved++;
// check to see if we have already issued a prefetch for this block
}
void
-Prefetcher::observePfMiss(const Address& address)
+Prefetcher::observePfMiss(Addr address)
{
numPartialHits++;
DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address);
}
void
-Prefetcher::observePfHit(const Address& address)
+Prefetcher::observePfHit(Addr address)
{
numHits++;
DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address);
}
void
-Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream)
+Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
{
// get our corresponding stream fetcher
if (stream == NULL) {
}
// extend this prefetching stream by 1 (or more)
- Address page_addr = pageAddress(stream->m_address);
- Address line_addr = next_stride_address(stream->m_address,
- stream->m_stride);
+ Addr page_addr = pageAddress(stream->m_address);
+ Addr line_addr = makeNextStrideAddress(stream->m_address,
+ stream->m_stride);
// possibly stop prefetching at page boundaries
if (page_addr != pageAddress(line_addr)) {
void
Prefetcher::clearNonunitEntry(uint32_t index)
{
- m_nonunit_filter[index].setAddress(0);
+ m_nonunit_filter[index] = 0;
m_nonunit_stride[index] = 0;
m_nonunit_hit[index] = 0;
}
void
-Prefetcher::initializeStream(const Address& address, int stride,
+Prefetcher::initializeStream(Addr address, int stride,
uint32_t index, const RubyRequestType& type)
{
numAllocatedStreams++;
// initialize the stream prefetcher
PrefetchEntry *mystream = &(m_array[index]);
- mystream->m_address = line_address(address);
+ mystream->m_address = makeLineAddress(address);
mystream->m_stride = stride;
mystream->m_use_time = m_controller->curCycle();
mystream->m_is_valid = true;
mystream->m_type = type;
// create a number of initial prefetches for this stream
- Address page_addr = pageAddress(mystream->m_address);
- Address line_addr = line_address(mystream->m_address);
- Address prev_addr = line_addr;
+ Addr page_addr = pageAddress(mystream->m_address);
+ Addr line_addr = makeLineAddress(mystream->m_address);
// insert a number of prefetches into the prefetch table
for (int k = 0; k < m_num_startup_pfs; k++) {
- line_addr = next_stride_address(line_addr, stride);
+ line_addr = makeNextStrideAddress(line_addr, stride);
// possibly stop prefetching at page boundaries
if (page_addr != pageAddress(line_addr)) {
numPagesCrossed++;
numPrefetchRequested++;
DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
m_controller->enqueuePrefetch(line_addr, m_array[index].m_type);
- prev_addr = line_addr;
}
// update the address to be the last address prefetched
}
PrefetchEntry *
-Prefetcher::getPrefetchEntry(const Address &address, uint32_t &index)
+Prefetcher::getPrefetchEntry(Addr address, uint32_t &index)
{
// search all streams for a match
for (int i = 0; i < m_num_streams; i++) {
// search all the outstanding prefetches for this stream
if (m_array[i].m_is_valid) {
for (int j = 0; j < m_num_startup_pfs; j++) {
- if (next_stride_address(m_array[i].m_address,
+ if (makeNextStrideAddress(m_array[i].m_address,
-(m_array[i].m_stride*j)) == address) {
return &(m_array[i]);
}
}
bool
-Prefetcher::accessUnitFilter(std::vector<Address>& filter_table,
- uint32_t *filter_hit, uint32_t &index, const Address &address,
+Prefetcher::accessUnitFilter(std::vector<Addr>& filter_table,
+ uint32_t *filter_hit, uint32_t &index, Addr address,
int stride, bool &alloc)
{
//reset the alloc flag
alloc = false;
- Address line_addr = line_address(address);
+ Addr line_addr = makeLineAddress(address);
for (int i = 0; i < m_num_unit_filters; i++) {
if (filter_table[i] == line_addr) {
- filter_table[i] = next_stride_address(filter_table[i], stride);
+ filter_table[i] = makeNextStrideAddress(filter_table[i], stride);
filter_hit[i]++;
if (filter_hit[i] >= m_train_misses) {
alloc = true;
// enter this address in the table
int local_index = index;
- filter_table[local_index] = next_stride_address(line_addr, stride);
+ filter_table[local_index] = makeNextStrideAddress(line_addr, stride);
filter_hit[local_index] = 0;
local_index = local_index + 1;
if (local_index >= m_num_unit_filters) {
}
bool
-Prefetcher::accessNonunitFilter(const Address& address, int *stride,
+Prefetcher::accessNonunitFilter(Addr address, int *stride,
bool &alloc)
{
//reset the alloc flag
alloc = false;
/// look for non-unit strides based on a (user-defined) page size
- Address page_addr = pageAddress(address);
- Address line_addr = line_address(address);
+ Addr page_addr = pageAddress(address);
+ Addr line_addr = makeLineAddress(address);
for (uint32_t i = 0; i < m_num_nonunit_filters; i++) {
if (pageAddress(m_nonunit_filter[i]) == page_addr) {
// hit in the non-unit filter
// compute the actual stride (for this reference)
- int delta = line_addr.getAddress() - m_nonunit_filter[i].getAddress();
+ int delta = line_addr - m_nonunit_filter[i];
if (delta != 0) {
// no zero stride prefetches
// increment count (if > 2) allocate stream
m_nonunit_hit[i]++;
if (m_nonunit_hit[i] > m_train_misses) {
- //This stride HAS to be the multiplicative constant of
- //dataBlockBytes (bc next_stride_address is calculated based
- //on this multiplicative constant!)
- *stride = m_nonunit_stride[i]/RubySystem::getBlockSizeBytes();
+ // This stride HAS to be the multiplicative constant of
+ // dataBlockBytes (bc makeNextStrideAddress is
+ // calculated based on this multiplicative constant!)
+ *stride = m_nonunit_stride[i] /
+ RubySystem::getBlockSizeBytes();
// clear this filter entry
clearNonunitEntry(i);
alloc = true;
}
} else {
- // delta didn't match ... reset m_nonunit_hit count for this entry
+ // delta didn't match ... reset m_nonunit_hit count for
+ // this entry
m_nonunit_hit[i] = 0;
}
}
}
-Address
-Prefetcher::pageAddress(const Address& addr) const
+Addr
+Prefetcher::pageAddress(Addr addr) const
{
- Address temp = addr;
- temp.maskLowOrderBits(m_page_shift);
- return temp;
+ return maskLowOrderBits(addr, m_page_shift);
}
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef PREFETCHER_H
-#define PREFETCHER_H
+#ifndef __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
+#define __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
// Implements Power 4 like prefetching
}
//! The base address for the stream prefetch
- Address m_address;
+ Addr m_address;
//! stride distance to get next address from
int m_stride;
Prefetcher(const Params *p);
~Prefetcher();
- void issueNextPrefetch(const Address &address, PrefetchEntry *stream);
+ void issueNextPrefetch(Addr address, PrefetchEntry *stream);
/**
* Implement the prefetch hit(miss) callback interface.
* These functions are called by the cache when it hits(misses)
* on a line with the line's prefetch bit set. If this address
* hits in m_array we will continue prefetching the stream.
*/
- void observePfHit(const Address& address);
- void observePfMiss(const Address& address);
+ void observePfHit(Addr address);
+ void observePfMiss(Addr address);
/**
* Observe a memory miss from the cache.
*
* @param address The physical address that missed out of the cache.
*/
- void observeMiss(const Address& address, const RubyRequestType& type);
+ void observeMiss(Addr address, const RubyRequestType& type);
/**
* Print out some statistics
void clearNonunitEntry(uint32_t index);
//! allocate a new stream buffer at a specific index
- void initializeStream(const Address& address, int stride,
+ void initializeStream(Addr address, int stride,
uint32_t index, const RubyRequestType& type);
//! get pointer to the matching stream entry, returns NULL if not found
//! index holds the multiple of the stride this address is.
- PrefetchEntry* getPrefetchEntry(const Address &address,
+ PrefetchEntry* getPrefetchEntry(Addr address,
uint32_t &index);
/// access a unit stride filter to determine if there is a hit
- bool accessUnitFilter(std::vector<Address>& filter_table,
- uint32_t *hit_table, uint32_t &index, const Address &address,
+ bool accessUnitFilter(std::vector<Addr>& filter_table,
+ uint32_t *hit_table, uint32_t &index, Addr address,
int stride, bool &alloc);
/// access a unit stride filter to determine if there is a hit
- bool accessNonunitFilter(const Address& address, int *stride,
+ bool accessNonunitFilter(Addr address, int *stride,
bool &alloc);
/// determine the page aligned address
- Address pageAddress(const Address& addr) const;
+ Addr pageAddress(Addr addr) const;
//! number of prefetch streams available
uint32_t m_num_streams;
/// a unit stride filter array: helps reduce BW requirement of
/// prefetching
- std::vector<Address> m_unit_filter;
+ std::vector<Addr> m_unit_filter;
/// a round robin pointer into the unit filter group
uint32_t m_unit_filter_index;
//! An array used to count the of times particular filter entries
//! a negative nit stride filter array: helps reduce BW requirement
//! of prefetching
- std::vector<Address> m_negative_filter;
+ std::vector<Addr> m_negative_filter;
/// a round robin pointer into the negative filter group
uint32_t m_negative_filter_index;
/// An array used to count the of times particular filter entries
/// a non-unit stride filter array: helps reduce BW requirement of
/// prefetching
- std::vector<Address> m_nonunit_filter;
+ std::vector<Addr> m_nonunit_filter;
/// An array of strides (in # of cache lines) for the filter entries
int *m_nonunit_stride;
/// An array used to count the of times particular filter entries
Stats::Scalar numMissedPrefetchedBlocks;
};
-#endif // PREFETCHER_H
+#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
RubyMemoryControl::recvTimingReq(PacketPtr pkt)
{
Cycles arrival_time = curCycle();
- physical_address_t addr = pkt->getAddr();
+ Addr addr = pkt->getAddr();
bool is_mem_read = pkt->isRead();
access(pkt);
{
m_msg_counter++;
memRef->m_msg_counter = m_msg_counter;
- physical_address_t addr = memRef->m_addr;
+ Addr addr = memRef->m_addr;
int bank = getBank(addr);
m_profiler_ptr->profileMemReq(bank);
// getBank returns an integer that is unique for each
// bank across this memory controller.
const int
-RubyMemoryControl::getBank(const physical_address_t addr) const
+RubyMemoryControl::getBank(const Addr addr) const
{
int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1);
int rank = (addr >> m_rank_bit_0) & (m_ranks_per_dimm - 1);
}
const int
-RubyMemoryControl::getRank(const physical_address_t addr) const
+RubyMemoryControl::getRank(const Addr addr) const
{
int bank = getBank(addr);
int rank = (bank / m_banks_per_rank);
// Not used!
const int
-RubyMemoryControl::getChannel(const physical_address_t addr) const
+RubyMemoryControl::getChannel(const Addr addr) const
{
assert(false);
return -1;
// Not used!
const int
-RubyMemoryControl::getRow(const physical_address_t addr) const
+RubyMemoryControl::getRow(const Addr addr) const
{
assert(false);
return -1;
void print(std::ostream& out) const;
void regStats();
- const int getBank(const physical_address_t addr) const;
- const int getRank(const physical_address_t addr) const;
+ const int getBank(const Addr addr) const;
+ const int getRank(const Addr addr) const;
// not used in Ruby memory controller
- const int getChannel(const physical_address_t addr) const;
- const int getRow(const physical_address_t addr) const;
+ const int getChannel(const Addr addr) const;
+ const int getRow(const Addr addr) const;
//added by SS
int getBanksPerRank() { return m_banks_per_rank; };
{
}
- bool isPresent(const Address& address) const;
- void allocate(const Address& address);
- void deallocate(const Address& address);
+ bool isPresent(Addr address) const;
+ void allocate(Addr address);
+ void deallocate(Addr address);
bool
areNSlotsAvailable(int n) const
{
return (m_number_of_TBEs - m_map.size()) >= n;
}
- ENTRY* lookup(const Address& address);
+ ENTRY* lookup(Addr address);
// Print cache contents
void print(std::ostream& out) const;
TBETable& operator=(const TBETable& obj);
// Data Members (m_prefix)
- m5::hash_map<Address, ENTRY> m_map;
+ m5::hash_map<Addr, ENTRY> m_map;
private:
int m_number_of_TBEs;
template<class ENTRY>
inline bool
-TBETable<ENTRY>::isPresent(const Address& address) const
+TBETable<ENTRY>::isPresent(Addr address) const
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(m_map.size() <= m_number_of_TBEs);
return !!m_map.count(address);
}
template<class ENTRY>
inline void
-TBETable<ENTRY>::allocate(const Address& address)
+TBETable<ENTRY>::allocate(Addr address)
{
assert(!isPresent(address));
assert(m_map.size() < m_number_of_TBEs);
template<class ENTRY>
inline void
-TBETable<ENTRY>::deallocate(const Address& address)
+TBETable<ENTRY>::deallocate(Addr address)
{
assert(isPresent(address));
assert(m_map.size() > 0);
// looks an address up in the cache
template<class ENTRY>
inline ENTRY*
-TBETable<ENTRY>::lookup(const Address& address)
+TBETable<ENTRY>::lookup(Addr address)
{
if(m_map.find(address) != m_map.end()) return &(m_map.find(address)->second);
return NULL;
m_clockobj_ptr = NULL;
m_next_valid = false;
- m_next_address = Address(0);
+ m_next_address = 0;
}
bool
return (m_clockobj_ptr->curCycle() >= m_next_time);
}
-const Address&
+Addr
TimerTable::readyAddress() const
{
assert(isReady());
}
void
-TimerTable::set(const Address& address, Cycles relative_latency)
+TimerTable::set(Addr address, Cycles relative_latency)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(relative_latency > 0);
assert(!m_map.count(address));
}
void
-TimerTable::unset(const Address& address)
+TimerTable::unset(Addr address)
{
- assert(address == line_address(address));
+ assert(address == makeLineAddress(address));
assert(m_map.count(address));
m_map.erase(address);
}
bool isReady() const;
- const Address& readyAddress() const;
- bool isSet(const Address& address) const { return !!m_map.count(address); }
- void set(const Address& address, Cycles relative_latency);
- void set(const Address& address, uint64_t relative_latency)
+ Addr readyAddress() const;
+ bool isSet(Addr address) const { return !!m_map.count(address); }
+ void set(Addr address, Cycles relative_latency);
+ void set(Addr address, uint64_t relative_latency)
{ set(address, Cycles(relative_latency)); }
- void unset(const Address& address);
+ void unset(Addr address);
void print(std::ostream& out) const;
private:
// use a std::map for the address map as this container is sorted
// and ensures a well-defined iteration order
- typedef std::map<Address, Cycles> AddressMap;
+ typedef std::map<Addr, Cycles> AddressMap;
AddressMap m_map;
mutable bool m_next_valid;
mutable Cycles m_next_time; // Only valid if m_next_valid is true
- mutable Address m_next_address; // Only valid if m_next_valid is true
+ mutable Addr m_next_address; // Only valid if m_next_valid is true
//! Object used for querying time.
ClockedObject* m_clockobj_ptr;
}
void
-CacheRecorder::addRecord(int cntrl, const physical_address_t data_addr,
- const physical_address_t pc_addr,
+CacheRecorder::addRecord(int cntrl, Addr data_addr, Addr pc_addr,
RubyRequestType type, Tick time, DataBlock& data)
{
TraceRecord* rec = (TraceRecord*)malloc(sizeof(TraceRecord) +
public:
int m_cntrl_id;
Tick m_time;
- physical_address_t m_data_address;
- physical_address_t m_pc_address;
+ Addr m_data_address;
+ Addr m_pc_address;
RubyRequestType m_type;
uint8_t m_data[0];
uint64_t uncompressed_trace_size,
std::vector<Sequencer*>& SequencerMap,
uint64_t block_size_bytes);
- void addRecord(int cntrl, const physical_address_t data_addr,
- const physical_address_t pc_addr, RubyRequestType type,
- Tick time, DataBlock& data);
+ void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
+ RubyRequestType type, Tick time, DataBlock& data);
uint64 aggregateRecords(uint8_t** data, uint64 size);
panic("DMASequencer should never see an inhibited request\n");
assert(isPhysMemAddress(pkt->getAddr()));
- assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
+ assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
RubySystem::getBlockSizeBytes());
// Submit the ruby request
return RequestStatus_BufferFull;
}
- uint64_t paddr = pkt->getAddr();
+ Addr paddr = pkt->getAddr();
uint8_t* data = pkt->getPtr<uint8_t>();
int len = pkt->getSize();
bool write = pkt->isWrite();
std::shared_ptr<SequencerMsg> msg =
std::make_shared<SequencerMsg>(clockEdge());
- msg->getPhysicalAddress() = Address(paddr);
- msg->getLineAddress() = line_address(msg->getPhysicalAddress());
+ msg->getPhysicalAddress() = paddr;
+ msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
int offset = paddr & m_data_block_mask;
std::shared_ptr<SequencerMsg> msg =
std::make_shared<SequencerMsg>(clockEdge());
- msg->getPhysicalAddress() = Address(active_request.start_paddr +
- active_request.bytes_completed);
+ msg->getPhysicalAddress() = active_request.start_paddr +
+ active_request.bytes_completed;
- assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
- msg->getLineAddress() = line_address(msg->getPhysicalAddress());
+ assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
+ msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
msg->getType() = (active_request.write ? SequencerRequestType_ST :
SequencerRequestType_LD);
PortID id, RubySystem *_ruby_system,
bool _access_backing_store);
void hitCallback(PacketPtr pkt);
- void evictionCallback(const Address& address);
+ void evictionCallback(Addr address);
protected:
bool recvTimingReq(PacketPtr pkt);
return true;
}
- assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
+ assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
RubySystem::getBlockSizeBytes());
// Submit the ruby request
}
assert(pkt->getAddr() + pkt->getSize() <=
- line_address(Address(pkt->getAddr())).getAddress() +
- RubySystem::getBlockSizeBytes());
+ makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
if (access_backing_store) {
// The attached physmem contains the official version of data.
}
void
-RubyPort::ruby_eviction_callback(const Address& address)
+RubyPort::ruby_eviction_callback(Addr address)
{
DPRINTF(RubyPort, "Sending invalidations.\n");
// This request is deleted in the stack-allocated packet destructor
// when this function exits
// TODO: should this really be using funcMasterId?
- RequestPtr req =
- new Request(address.getAddress(), 0, 0, Request::funcMasterId);
+ RequestPtr req = new Request(address, 0, 0, Request::funcMasterId);
// Use a single packet to signal all snooping ports of the invalidation.
// This assumes that snooping ports do NOT modify the packet/request
Packet pkt(req, MemCmd::InvalidateReq);
MemSlavePort(const std::string &_name, RubyPort *_port,
bool _access_backing_store, PortID id);
void hitCallback(PacketPtr pkt);
- void evictionCallback(const Address& address);
+ void evictionCallback(Addr address);
protected:
bool recvTimingReq(PacketPtr pkt);
protected:
void ruby_hit_callback(PacketPtr pkt);
void testDrainComplete();
- void ruby_eviction_callback(const Address& address);
+ void ruby_eviction_callback(Addr address);
/**
* Called by the PIO port when receiving a timing response.
continue;
panic("Possible Deadlock detected. Aborting!\n"
- "version: %d request.paddr: 0x%x m_readRequestTable: %d "
- "current time: %u issue_time: %d difference: %d\n", m_version,
- Address(request->pkt->getAddr()), m_readRequestTable.size(),
+ "version: %d request.paddr: 0x%x m_readRequestTable: %d "
+ "current time: %u issue_time: %d difference: %d\n", m_version,
+ request->pkt->getAddr(), m_readRequestTable.size(),
current_time * clockPeriod(), request->issue_time * clockPeriod(),
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
}
continue;
panic("Possible Deadlock detected. Aborting!\n"
- "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
- "current time: %u issue_time: %d difference: %d\n", m_version,
- Address(request->pkt->getAddr()), m_writeRequestTable.size(),
+ "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
+ "current time: %u issue_time: %d difference: %d\n", m_version,
+ request->pkt->getAddr(), m_writeRequestTable.size(),
current_time * clockPeriod(), request->issue_time * clockPeriod(),
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
}
schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
}
- Address line_addr(pkt->getAddr());
- line_addr.makeLineAddress();
+ Addr line_addr = makeLineAddress(pkt->getAddr());
// Create a default entry, mapping the address to NULL, the cast is
// there to make gcc 4.4 happy
RequestTable::value_type default_entry(line_addr,
assert(m_outstanding_count ==
m_writeRequestTable.size() + m_readRequestTable.size());
- Address line_addr(srequest->pkt->getAddr());
- line_addr.makeLineAddress();
+ Addr line_addr = makeLineAddress(srequest->pkt->getAddr());
if ((srequest->m_type == RubyRequestType_ST) ||
(srequest->m_type == RubyRequestType_RMW_Read) ||
(srequest->m_type == RubyRequestType_RMW_Write) ||
}
void
-Sequencer::invalidateSC(const Address& address)
+Sequencer::invalidateSC(Addr address)
{
RequestTable::iterator i = m_writeRequestTable.find(address);
if (i != m_writeRequestTable.end()) {
}
bool
-Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
+Sequencer::handleLlsc(Addr address, SequencerRequest* request)
{
//
// The success flag indicates whether the LLSC operation was successful.
}
void
-Sequencer::writeCallback(const Address& address, DataBlock& data,
+Sequencer::writeCallback(Addr address, DataBlock& data,
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
const Cycles firstResponseTime)
{
- assert(address == line_address(address));
- assert(m_writeRequestTable.count(line_address(address)));
+ assert(address == makeLineAddress(address));
+ assert(m_writeRequestTable.count(makeLineAddress(address)));
RequestTable::iterator i = m_writeRequestTable.find(address);
assert(i != m_writeRequestTable.end());
}
void
-Sequencer::readCallback(const Address& address, DataBlock& data,
+Sequencer::readCallback(Addr address, DataBlock& data,
bool externalHit, const MachineType mach,
Cycles initialRequestTime,
Cycles forwardRequestTime,
Cycles firstResponseTime)
{
- assert(address == line_address(address));
- assert(m_readRequestTable.count(line_address(address)));
+ assert(address == makeLineAddress(address));
+ assert(m_readRequestTable.count(makeLineAddress(address)));
RequestTable::iterator i = m_readRequestTable.find(address);
assert(i != m_readRequestTable.end());
const Cycles firstResponseTime)
{
PacketPtr pkt = srequest->pkt;
- Address request_address(pkt->getAddr());
- Address request_line_address(pkt->getAddr());
- request_line_address.makeLineAddress();
+ Addr request_address(pkt->getAddr());
+ Addr request_line_address = makeLineAddress(pkt->getAddr());
RubyRequestType type = srequest->m_type;
Cycles issued_time = srequest->issue_time;
initialRequestTime, forwardRequestTime,
firstResponseTime, curCycle());
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
curTick(), m_version, "Seq",
llscSuccess ? "Done" : "SC_Failed", "", "",
request_address, total_latency);
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
data.setData(pkt->getConstPtr<uint8_t>(),
- request_address.getOffset(), pkt->getSize());
+ getOffset(request_address), pkt->getSize());
} else if (!pkt->isFlush()) {
if ((type == RubyRequestType_LD) ||
(type == RubyRequestType_IFETCH) ||
(type == RubyRequestType_Locked_RMW_Read) ||
(type == RubyRequestType_Load_Linked)) {
memcpy(pkt->getPtr<uint8_t>(),
- data.getData(request_address.getOffset(), pkt->getSize()),
+ data.getData(getOffset(request_address), pkt->getSize()),
pkt->getSize());
DPRINTF(RubySequencer, "read data %s\n", data);
} else {
data.setData(pkt->getConstPtr<uint8_t>(),
- request_address.getOffset(), pkt->getSize());
+ getOffset(request_address), pkt->getSize());
DPRINTF(RubySequencer, "set data %s\n", data);
}
}
RubyAccessMode_Supervisor, pkt,
PrefetchBit_No, proc_id);
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
curTick(), m_version, "Seq", "Begin", "", "",
msg->getPhysicalAddress(),
RubyRequestType_to_string(secondary_type));
// upgraded when invoked, coherence violations will be checked for the
// given block
void
-Sequencer::checkCoherence(const Address& addr)
+Sequencer::checkCoherence(Addr addr)
{
#ifdef CHECK_COHERENCE
m_ruby_system->checkGlobalCoherenceInvariant(addr);
void
-Sequencer::evictionCallback(const Address& address)
+Sequencer::evictionCallback(Addr address)
{
ruby_eviction_callback(address);
}
void collateStats();
void regStats();
- void writeCallback(const Address& address,
+ void writeCallback(Addr address,
DataBlock& data,
const bool externalHit = false,
const MachineType mach = MachineType_NUM,
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
- void readCallback(const Address& address,
+ void readCallback(Addr address,
DataBlock& data,
const bool externalHit = false,
const MachineType mach = MachineType_NUM,
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
- void checkCoherence(const Address& address);
+ void checkCoherence(Addr address);
void markRemoved();
void removeRequest(SequencerRequest* request);
- void evictionCallback(const Address& address);
- void invalidateSC(const Address& address);
+ void evictionCallback(Addr address);
+ void invalidateSC(Addr address);
void recordRequestType(SequencerRequestType requestType);
Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
Cycles completionTime);
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
- bool handleLlsc(const Address& address, SequencerRequest* request);
+ bool handleLlsc(Addr address, SequencerRequest* request);
// Private copy constructor and assignment operator
Sequencer(const Sequencer& obj);
Cycles m_data_cache_hit_latency;
Cycles m_inst_cache_hit_latency;
- typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
+ typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
RequestTable m_writeRequestTable;
RequestTable m_readRequestTable;
// Global outstanding request count, across all request tables
bool
RubySystem::functionalRead(PacketPtr pkt)
{
- Address address(pkt->getAddr());
- Address line_address(address);
- line_address.makeLineAddress();
+ Addr address(pkt->getAddr());
+ Addr line_address = makeLineAddress(address);
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Read request for %s\n",address);
+ DPRINTF(RubySystem, "Functional Read request for %s\n", address);
unsigned int num_ro = 0;
unsigned int num_rw = 0;
bool
RubySystem::functionalWrite(PacketPtr pkt)
{
- Address addr(pkt->getAddr());
- Address line_addr = line_address(addr);
+ Addr addr(pkt->getAddr());
+ Addr line_addr = makeLineAddress(addr);
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Write request for %s\n",addr);
+ DPRINTF(RubySystem, "Functional Write request for %s\n", addr);
uint32_t M5_VAR_USED num_functional_writes = 0;
# Add new local vars
self.symtab.pushFrame()
- addr_type = self.symtab.find("Address", Type)
+ addr_type = self.symtab.find("Addr", Type)
if addr_type is None:
- self.error("Type 'Address' not declared.")
+ self.error("Type 'Addr' not declared.")
var = Var(self.symtab, "address", self.location, addr_type,
"addr", self.pairs)
param_types.append(type)
# Check for Address
- type = symtab.find("Address", Type)
+ type = symtab.find("Addr", Type)
if type is None:
- self.error("in_port decls require 'Address' type to be defined")
+ self.error("in_port decls require 'Addr' type to be defined")
param_types.append(type)
param_types.append(type)
# Check for Address2
- type = symtab.find("Address", Type)
+ type = symtab.find("Addr", Type)
if type is None:
- self.error("in_port decls require 'Address' type to be defined")
+ self.error("in_port decls require 'Addr' type to be defined")
param_types.append(type)
def generate(self, code, return_type):
self.in_port.assertType("InPort")
- self.address.assertType("Address")
+ self.address.assertType("Addr")
in_port_code = self.in_port.var.code
address_code = self.address.var.code
''')
code('''
- const Address addr);
+ Addr addr);
TransitionResult doTransitionWorker(${ident}_Event event,
${ident}_State state,
''')
code('''
- const Address& addr);
+ Addr addr);
int m_counters[${ident}_State_NUM][${ident}_Event_NUM];
int m_event_counters[${ident}_Event_NUM];
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
'm_tbe_ptr, ${{self.EntryType.c_ident}}*& '
- 'm_cache_entry_ptr, const Address& addr);')
+ 'm_cache_entry_ptr, Addr addr);')
elif self.TBEType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
- 'm_tbe_ptr, const Address& addr);')
+ 'm_tbe_ptr, Addr addr);')
elif self.EntryType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& '
- 'm_cache_entry_ptr, const Address& addr);')
+ 'm_cache_entry_ptr, Addr addr);')
else:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
- code('void ${{action.ident}}(const Address& addr);')
+ code('void ${{action.ident}}(Addr addr);')
# the controller internal variables
code('''
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
try {
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(const Address& addr)
+$c_ident::${{action.ident}}(Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
${{self.TBEType.c_ident}}* m_tbe_ptr,
''')
code('''
- const Address addr)
+ Addr addr)
{
''')
code.indent()
${ident}_State_to_string(next_state));
countTransition(state, event);
- DPRINTFR(ProtocolTrace, "%15d %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15d %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
code('''
} else if (result == TransitionResult_ResourceStall) {
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
addr, "Resource Stall");
} else if (result == TransitionResult_ProtocolStall) {
DPRINTF(RubyGenerated, "stalling\\n");
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
${{self.EntryType.c_ident}}*& m_cache_entry_ptr,
''')
code('''
- const Address& addr)
+ Addr addr)
{
switch(HASH_FUN(state, event)) {
''')
if self.isMachineType:
code('#include "base/misc.hh"')
code('#include "mem/ruby/common/Address.hh"')
+ code('#include "mem/ruby/common/TypeDefines.hh"')
code('struct MachineID;')
code('''
for enum in self.enums.itervalues():
if enum.ident == "DMA":
code('''
-MachineID map_Address_to_DMA(const Address &addr);
+MachineID map_Address_to_DMA(const Addr &addr);
''')
code('''
if enum.ident == "DMA":
code('''
MachineID
-map_Address_to_DMA(const Address &addr)
+map_Address_to_DMA(const Addr &addr)
{
MachineID dma = {MachineType_DMA, 0};
return dma;
projects / gem5.git / commitdiff