replace & operator with rv_and

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index 86b488314ff8ad737a232cd319dcd511e10935f9..ff50df2641632c19aa31921e833e1e22b8fbe1be 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-WRITE_RD(RS1 & RS2);
+WRITE_RD(rv_and(RS1, RS2));

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index bcc51e44071ab6bdff0ac53fd81bf3d1acf0764d..8cbd03bb157c6bccf571b1aead0b5ec9d0af62bf 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-WRITE_RD(insn.i_imm() & RS1);
+WRITE_RD(rv_and(insn.i_imm(), RS1));

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index e5be643b476defb3054763b95120af8dd2c53a7e..34ee0ca0f852c415982f16476df4c726831068c2 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -242,3 +242,8 @@ reg_t sv_proc_t::rv_mul(reg_t lhs, reg_t rhs)
     return lhs * rhs;
 }
 
+reg_t sv_proc_t::rv_and(reg_t lhs, reg_t rhs)
+{
+    return lhs & rhs;
+}
+

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 7112dd59ebbcc88058dd765f095b39c09c4c55d1..71b98018fb1351bbffab0c1b9523294bb4c67c55 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -99,6 +99,7 @@ public:
     reg_t rv_div(reg_t lhs, reg_t rhs);
     sreg_t rv_div(sreg_t lhs, sreg_t rhs);
     reg_t rv_mul(reg_t lhs, reg_t rhs);
+    reg_t rv_and(reg_t lhs, reg_t rhs);
 
 #include "sv_insn_decl.h"
 };