x86: implement fabs, fchs instructions

diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa
index 3af68cd5406113396d5cabd7022a7a768359cbf6..f278dc2f8220203ac924bd03224e829fa314e514 100644 (file)
--- a/src/arch/x86/isa/decoder/x87.isa
+++ b/src/arch/x86/isa/decoder/x87.isa
@@ -68,8 +68,8 @@ format WarnUnimpl {
             }
             0x4: decode MODRM_MOD {
                 0x3: decode MODRM_RM {
-                    0x0: fchs();
-                    0x1: fabs();
+                    0x0: Inst::FCHS();
+                    0x1: Inst::FABS();
                     0x4: ftst();
                     0x5: fxam();
                     default: Inst::UD2();

diff --git a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
index 059fb1ef152ac5c5b5cab0f0af342376c9ed983f..779f1b5b25e65423c1594d699970045cc0864634 100644 (file)
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
@@ -36,6 +36,12 @@
 # Authors: Gabe Black
 
 microcode = '''
-# FABS
-# FCHS
+
+def macroop FABS {
+    absfp st(0), st(0)
+};
+
+def macroop FCHS {
+    chsfp st(0), st(0)
+};
 '''

diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index f6cbd203668604daa485389f03af95541d7fdde6..b9aceea0972a05f0c022dba90a00a930d1c00c60 100644 (file)
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -331,4 +331,12 @@ let {{
             else if(FpSrcReg1 == FpSrcReg2)
                 ccFlagBits = ccFlagBits | ZFBit;
         '''
+
+    class absfp(FpUnaryOp):
+        code = 'FpDestReg = fabs(FpSrcReg1);'
+        flag_code = 'FSW &= (~CC1Bit);'
+
+    class chsfp(FpUnaryOp):
+        code = 'FpDestReg = (-1) * (FpSrcReg1);'
+        flag_code = 'FSW &= (~CC1Bit);'
 }};

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 05b127e374e074cc190a6e2d7e4656cba03ac105..bc6d1886cb959826a8ff2cc6a32bcfcead137aa5 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -158,7 +158,11 @@ def operands {{
         # These register should needs to be more protected so that later
         # instructions don't map their indexes with an old value.
         'nccFlagBits':   controlReg('MISCREG_RFLAGS', 65),
+
+        # Registers related to the state of x87 floating point unit.
         'TOP':           controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
+        'FSW':           controlReg('MISCREG_FSW', 67, ctype='uw'),
+
         # The segment base as used by memory instructions.
         'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
 

diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 697c81fc93aeb30944331dfe4633022bf3a29bc5..5887e748639dbf7767a17ceed26648dbf9430e1d 100644 (file)
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -79,6 +79,25 @@ namespace X86ISA
         IDBit = 1 << 21
     };
 
+    enum X87StatusBit {
+        // Exception Flags
+        IEBit = 1 << 0,
+        DEBit = 1 << 1,
+        ZEBit = 1 << 2,
+        OEBit = 1 << 3,
+        UEBit = 1 << 4,
+        PEBit = 1 << 5,
+
+        // !Exception Flags
+        StackFaultBit = 1 << 6,
+        ErrSummaryBit = 1 << 7,
+        CC0Bit = 1 << 8,
+        CC1Bit = 1 << 9,
+        CC2Bit = 1 << 10,
+        CC3Bit = 1 << 14,
+        BusyBit = 1 << 15,
+    };
+
     enum MiscRegIndex
     {
         // Control registers