l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
- cpu_seq = RubySequencer(icache = l1i_cache,
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
- cpu_seq = RubySequencer(icache = cache,
+ cpu_seq = RubySequencer(version = i,
+ icache = cache,
dcache = cache,
physMemPort = phys_mem.port,
physmem = phys_mem)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
- cpu_seq = RubySequencer(icache = l1i_cache,
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
- cpu_seq = RubySequencer(icache = l1i_cache,
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc)
- cpu_seq = RubySequencer(icache = l1i_cache,
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)