Use nonblocking

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 40e54f9f06f324258f1a07d827fd97a1d86fef24..40972766d308dcb0c08bce5161a9a824396b055e 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
        always @(posedge C)
                Q <= D;
 `else
-    always @* Q = D;
+    always @* Q <= D;
 `endif
 endmodule