InOrderCPU::~InOrderCPU()
{
delete resPool;
+
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
+ skedCache.begin();
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
+ skedCache.end();
+
+ while (sked_it != sked_end) {
+ delete (*sked_it).second;
+ sked_it++;
+ }
+ skedCache.clear();
}
std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
W.needs(Grad, GraduationUnit::GraduateInst);
- // Insert Front Schedule into our cache of
+ // Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);
void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
{
SkedID sked_id = genSkedID(inst);
+ assert(skedCache.find(sked_id) == skedCache.end());
skedCache[sked_id] = inst_sked;
}
stageBufferMax(params->stageWidth),
prevStageValid(false), nextStageValid(false), idle(false)
{
- switchedOutBuffer.resize(ThePipeline::MaxThreads);
- switchedOutValid.resize(ThePipeline::MaxThreads);
-
init(params);
}
+PipelineStage::~PipelineStage()
+{
+ for(ThreadID tid = 0; tid < numThreads; tid++) {
+ skidBuffer[tid].clear();
+ stalls[tid].resources.clear();
+ }
+}
+
void
PipelineStage::init(Params *params)
{
else
lastStallingStage[tid] = NumStages - 1;
}
+
+ if ((InOrderCPU::ThreadModel) params->threadModel ==
+ InOrderCPU::SwitchOnCacheMiss) {
+ switchedOutBuffer.resize(ThePipeline::MaxThreads);
+ switchedOutValid.resize(ThePipeline::MaxThreads);
+ }
}
stalls[tid].resources.clear();
- while (!insts[tid].empty())
- insts[tid].pop();
-
skidBuffer[tid].clear();
}
wroteToTimeBuffer = false;
public:
PipelineStage(Params *params, unsigned stage_num);
- /** MUST use init() function if this constructor is used. */
- PipelineStage() { }
-
- virtual ~PipelineStage() { }
+ virtual ~PipelineStage();
/** PipelineStage initialization. */
void init(Params *params);
*/
unsigned instsProcessed;
- /** Queue of all instructions coming from previous stage on this cycle. */
- std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
-
- /** Queue of instructions that are finished processing and ready to go
- * next stage. This is used to prevent from processing an instrution more
- * than once on any stage. NOTE: It is up to the PROGRAMMER must manage
- * this as a queue
- */
- std::list<DynInstPtr> instsToNextStage;
-
/** Skid buffer between previous stage and this one. */
std::list<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
regMap.resize(size);
}
+RegDepMap::~RegDepMap()
+{
+ for (int i = 0; i < regMap.size(); i++) {
+ regMap[i].clear();
+ }
+ regMap.clear();
+}
+
string
RegDepMap::name()
{
public:
RegDepMap(int size = TheISA::TotalNumRegs);
- ~RegDepMap() { }
+ ~RegDepMap();
std::string name();
delete [] resourceEvent;
}
- delete deniedReq;
+ delete deniedReq;
+
+ for (int i = 0; i < width; i++) {
+ delete reqs[i];
+ }
}
DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID,
res->cpu->resReqCount);
#endif
+ inst = NULL;
}
void