} // namespace FastModel
FastModel::CortexA76 *
-FastModelCortexA76Params::create()
+FastModelCortexA76Params::create() const
{
return new FastModel::CortexA76(*this);
}
FastModel::CortexA76Cluster *
-FastModelCortexA76ClusterParams::create()
+FastModelCortexA76ClusterParams::create() const
{
return new FastModel::CortexA76Cluster(*this);
}
} // namespace FastModel
FastModel::ScxEvsCortexA76x1 *
-FastModelScxEvsCortexA76x1Params::create()
+FastModelScxEvsCortexA76x1Params::create() const
{
return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this);
}
FastModel::ScxEvsCortexA76x2 *
-FastModelScxEvsCortexA76x2Params::create()
+FastModelScxEvsCortexA76x2Params::create() const
{
return new FastModel::ScxEvsCortexA76x2(name.c_str(), *this);
}
FastModel::ScxEvsCortexA76x3 *
-FastModelScxEvsCortexA76x3Params::create()
+FastModelScxEvsCortexA76x3Params::create() const
{
return new FastModel::ScxEvsCortexA76x3(name.c_str(), *this);
}
FastModel::ScxEvsCortexA76x4 *
-FastModelScxEvsCortexA76x4Params::create()
+FastModelScxEvsCortexA76x4Params::create() const
{
return new FastModel::ScxEvsCortexA76x4(name.c_str(), *this);
}
}
}
-CortexR52Cluster::CortexR52Cluster(Params &p) :
+CortexR52Cluster::CortexR52Cluster(const Params &p) :
SimObject(&p), _params(p), cores(p.cores), evs(p.evs)
{
for (int i = 0; i < p.cores.size(); i++)
} // namespace FastModel
FastModel::CortexR52 *
-FastModelCortexR52Params::create()
+FastModelCortexR52Params::create() const
{
return new FastModel::CortexR52(*this);
}
FastModel::CortexR52Cluster *
-FastModelCortexR52ClusterParams::create()
+FastModelCortexR52ClusterParams::create() const
{
return new FastModel::CortexR52Cluster(*this);
}
const Params ¶ms() { return _params; }
public:
- CortexR52(Params &p) : Base(&p, scx::scx_get_iris_connection_interface()),
- _params(p)
+ CortexR52(const Params &p) :
+ Base(&p, scx::scx_get_iris_connection_interface()), _params(p)
{}
template <class T>
CortexR52 *getCore(int num) const { return cores.at(num); }
sc_core::sc_module *getEvs() const { return evs; }
- CortexR52Cluster(Params &p);
+ CortexR52Cluster(const Params &p);
const Params ¶ms() { return _params; }
Port &getPort(const std::string &if_name,
} // namespace FastModel
FastModel::ScxEvsCortexR52x1 *
-FastModelScxEvsCortexR52x1Params::create()
+FastModelScxEvsCortexR52x1Params::create() const
{
return new FastModel::ScxEvsCortexR52x1(name.c_str(), *this);
}
FastModel::ScxEvsCortexR52x2 *
-FastModelScxEvsCortexR52x2Params::create()
+FastModelScxEvsCortexR52x2Params::create() const
{
return new FastModel::ScxEvsCortexR52x2(name.c_str(), *this);
}
FastModel::ScxEvsCortexR52x3 *
-FastModelScxEvsCortexR52x3Params::create()
+FastModelScxEvsCortexR52x3Params::create() const
{
return new FastModel::ScxEvsCortexR52x3(name.c_str(), *this);
}
FastModel::ScxEvsCortexR52x4 *
-FastModelScxEvsCortexR52x4Params::create()
+FastModelScxEvsCortexR52x4Params::create() const
{
return new FastModel::ScxEvsCortexR52x4(name.c_str(), *this);
}
} // namespace FastModel
FastModel::SCGIC *
-SCFastModelGICParams::create()
+SCFastModelGICParams::create() const
{
return new FastModel::SCGIC(*this, name.c_str());
}
FastModel::GIC *
-FastModelGICParams::create()
+FastModelGICParams::create() const
{
return new FastModel::GIC(*this);
}
} // namespace FastModel
FastModel::AmbaFromTlmBridge64 *
-AmbaFromTlmBridge64Params::create()
+AmbaFromTlmBridge64Params::create() const
{
return new FastModel::AmbaFromTlmBridge64(name.c_str());
}
} // namespace FastModel
FastModel::AmbaToTlmBridge64 *
-AmbaToTlmBridge64Params::create()
+AmbaToTlmBridge64Params::create() const
{
return new FastModel::AmbaToTlmBridge64(name.c_str());
}
namespace Iris
{
-BaseCPU::BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs) :
+BaseCPU::BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs) :
::BaseCPU::BaseCPU(params), evs(_evs),
clockEvent(nullptr), periodAttribute(nullptr)
{
class BaseCPU : public ::BaseCPU
{
public:
- BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs);
+ BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs);
virtual ~BaseCPU();
Port &
class CPU : public Iris::BaseCPU
{
public:
- CPU(IrisBaseCPUParams *params, iris::IrisConnectionInterface *iris_if) :
- BaseCPU(params, params->evs)
+ CPU(const IrisBaseCPUParams ¶ms,
+ iris::IrisConnectionInterface *iris_if) :
+ BaseCPU(params, params.evs)
{
const std::string parent_path = evs->name();
- System *sys = params->system;
+ System *sys = params.system;
int thread_id = 0;
- for (const std::string &sub_path: params->thread_paths) {
+ for (const std::string &sub_path: params.thread_paths) {
std::string path = parent_path + "." + sub_path;
auto id = thread_id++;
- auto *tc = new TC(this, id, sys, params->dtb, params->itb,
- params->isa[id], iris_if, path);
+ auto *tc = new TC(this, id, sys, params.dtb, params.itb,
+ params.isa[id], iris_if, path);
threadContexts.push_back(tc);
}
}
}
Iris::Interrupts *
-IrisInterruptsParams::create()
+IrisInterruptsParams::create() const
{
- return new Iris::Interrupts(this);
+ return new Iris::Interrupts(*this);
}
public:
typedef IrisInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params *p) : BaseInterrupts(p) {}
+ Interrupts(const Params &p) : BaseInterrupts(p) {}
bool checkInterrupts() const override { return false; }
Fault getInterrupt() override { return NoFault; }
}
Iris::ISA *
-IrisISAParams::create()
+IrisISAParams::create() const
{
- return new Iris::ISA(this);
+ return new Iris::ISA(*this);
}
class ISA : public BaseISA
{
public:
- ISA(const Params *p) : BaseISA(p) {}
+ ISA(const Params &p) : BaseISA(p) {}
void serialize(CheckpointOut &cp) const;
};
#include "arch/arm/fastmodel/iris/mmu.hh"
Iris::MMU *
-IrisMMUParams::create()
+IrisMMUParams::create() const
{
- return new Iris::MMU(this);
+ return new Iris::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const Params *p) : BaseMMU(p) {}
+ MMU(const Params &p) : BaseMMU(p) {}
};
} // namespace Iris
}
Iris::TLB *
-IrisTLBParams::create()
+IrisTLBParams::create() const
{
- return new Iris::TLB(this);
+ return new Iris::TLB(*this);
}
class TLB : public BaseTLB
{
public:
- TLB(const Params *p) : BaseTLB(p) {}
+ TLB(const Params &p) : BaseTLB(p) {}
void demapPage(Addr vaddr, uint64_t asn) override {}
void flushAll() override {}
namespace ArmISA
{
-FsFreebsd::FsFreebsd(Params *p) : ArmISA::FsWorkload(p),
- enableContextSwitchStatsDump(p->enable_context_switch_stats_dump)
+FsFreebsd::FsFreebsd(const Params &p) : ArmISA::FsWorkload(p),
+ enableContextSwitchStatsDump(p.enable_context_switch_stats_dump)
{
- if (p->panic_on_panic) {
+ if (p.panic_on_panic) {
kernelPanic = addKernelFuncEventOrPanic<PanicPCEvent>(
"panic", "Kernel panic in simulated kernel");
} else {
#endif
}
- if (p->panic_on_oops) {
+ if (p.panic_on_oops) {
kernelOops = addKernelFuncEventOrPanic<PanicPCEvent>(
"oops_exit", "Kernel oops in guest");
}
// Load symbols at physical address, we might not want
// to do this permanently, for but early bootup work
// it is helpful.
- if (params()->early_kernel_symbols) {
+ if (params().early_kernel_symbols) {
auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
kernelSymtab.insert(*phys_globals);
Loader::debugSymbolTable.insert(*phys_globals);
// device trees.
fatal_if(kernelSymtab.find("fdt_get_range") == kernelSymtab.end(),
"Kernel must have fdt support.");
- fatal_if(params()->dtb_filename == "", "dtb file is not specified.");
+ fatal_if(params().dtb_filename == "", "dtb file is not specified.");
// Kernel supports flattened device tree and dtb file specified.
// Using Device Tree Blob to describe system configuration.
- inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
- params()->atags_addr + _loadAddrOffset);
+ inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
+ params().atags_addr + _loadAddrOffset);
- auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);
+ auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()),
"Couldn't append bootargs to DTB file: %s",
- params()->dtb_filename);
+ params().dtb_filename);
Addr ra = dtb_file->findReleaseAddr();
if (ra)
bootReleaseAddr = ra & ~ULL(0x7F);
dtb_file->buildImage().
- offset(params()->atags_addr + _loadAddrOffset).
+ offset(params().atags_addr + _loadAddrOffset).
write(system->physProxy);
delete dtb_file;
// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
for (auto *tc: system->threads) {
tc->setIntReg(0, 0);
- tc->setIntReg(1, params()->machine_type);
- tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+ tc->setIntReg(1, params().machine_type);
+ tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
}
}
} // namespace ArmISA
ArmISA::FsFreebsd *
-ArmFsFreebsdParams::create()
+ArmFsFreebsdParams::create() const
{
- return new ArmISA::FsFreebsd(this);
+ return new ArmISA::FsFreebsd(*this);
}
public:
/** Boilerplate params code */
typedef ArmFsFreebsdParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(&_params);
+ return dynamic_cast<const Params &>(_params);
}
/** When enabled, dump stats/task info on context switches for
* mappings between taskIds and OS process IDs */
std::ostream* taskFile;
- FsFreebsd(Params *p);
+ FsFreebsd(const Params &p);
~FsFreebsd();
void initState() override;
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
{ 477, "mmap", mmapFunc<ArmFreebsd64> }
};
-ArmFreebsdProcess32::ArmFreebsdProcess32(ProcessParams * params,
+ArmFreebsdProcess32::ArmFreebsdProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
ArmProcess32(params, objFile, _arch)
{}
-ArmFreebsdProcess64::ArmFreebsdProcess64(ProcessParams * params,
+ArmFreebsdProcess64::ArmFreebsdProcess64(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
ArmProcess64(params, objFile, _arch)
{}
class ArmFreebsdProcess32 : public ArmProcess32, public ArmFreebsdProcessBits
{
public:
- ArmFreebsdProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
- ::Loader::Arch _arch);
+ ArmFreebsdProcess32(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
void initState() override;
class ArmFreebsdProcess64 : public ArmProcess64, public ArmFreebsdProcessBits
{
public:
- ArmFreebsdProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
- ::Loader::Arch _arch);
+ ArmFreebsdProcess64(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
void initState() override;
void syscall(ThreadContext *tc) override;
}
}
-FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p)
+FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
{
if (kernelObj) {
kernelEntry = (kernelObj->entryPoint() & loadAddrMask()) +
loadAddrOffset();
}
- bootLoaders.reserve(p->boot_loader.size());
- for (const auto &bl : p->boot_loader) {
+ bootLoaders.reserve(p.boot_loader.size());
+ for (const auto &bl : p.boot_loader) {
std::unique_ptr<Loader::ObjectFile> bl_obj;
bl_obj.reset(Loader::createObjectFile(bl));
// Put the address of the boot loader into r7 so we know
// where to branch to after the reset fault
// All other values needed by the boot loader to know what to do
- fatal_if(!arm_sys->params()->flags_addr,
+ fatal_if(!arm_sys->params().flags_addr,
"flags_addr must be set with bootloader");
- fatal_if(!arm_sys->params()->gic_cpu_addr && is_gic_v2,
+ fatal_if(!arm_sys->params().gic_cpu_addr && is_gic_v2,
"gic_cpu_addr must be set with bootloader");
for (auto *tc: arm_sys->threads) {
if (!arm_sys->highestELIs64())
tc->setIntReg(3, kernelEntry);
if (is_gic_v2)
- tc->setIntReg(4, arm_sys->params()->gic_cpu_addr);
- tc->setIntReg(5, arm_sys->params()->flags_addr);
+ tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
+ tc->setIntReg(5, arm_sys->params().flags_addr);
}
inform("Using kernel entry physical address at %#x\n", kernelEntry);
} else {
} // namespace ArmISA
ArmISA::FsWorkload *
-ArmFsWorkloadParams::create()
+ArmFsWorkloadParams::create() const
{
- return new ArmISA::FsWorkload(this);
+ return new ArmISA::FsWorkload(*this);
}
public:
typedef ArmFsWorkloadParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(&_params);
+ return dynamic_cast<const Params &>(_params);
}
Addr
return Loader::Arm64;
}
- FsWorkload(Params *p);
+ FsWorkload(const Params &p);
void initState() override;
#include "arch/arm/system.hh"
ArmISA::Interrupts *
-ArmInterruptsParams::create()
+ArmInterruptsParams::create() const
{
- return new ArmISA::Interrupts(this);
+ return new ArmISA::Interrupts(*this);
}
bool
typedef ArmInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params * p) : BaseInterrupts(p)
+ Interrupts(const Params &p) : BaseInterrupts(p)
{
clearAll();
}
namespace ArmISA
{
-ISA::ISA(Params *p) : BaseISA(p), system(NULL),
- _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
- pmu(p->pmu), impdefAsNop(p->impdef_nop),
+ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
+ _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
+ pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
// Give all ISA devices a pointer to this ISA
pmu->setISA(this);
- system = dynamic_cast<ArmSystem *>(p->system);
+ system = dynamic_cast<ArmSystem *>(p.system);
// Cache system-level properties
if (FullSystem && system) {
haveSVE = true;
havePAN = false;
haveSecEL2 = true;
- sveVL = p->sve_vl_se;
+ sveVL = p.sve_vl_se;
haveLSE = true;
haveTME = true;
}
std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
-const ArmISAParams *
+const ArmISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void
ISA::clear()
{
- const Params *p(params());
+ const Params &p(params());
// Invalidate cached copies of miscregs in the TLBs
if (tc) {
}
void
-ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
+ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
{
CPSR cpsr = 0;
cpsr.mode = MODE_USER;
miscRegs[MISCREG_CPACR] = 0;
- miscRegs[MISCREG_FPSID] = p->fpsid;
+ miscRegs[MISCREG_FPSID] = p.fpsid;
if (haveLPAE) {
TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
}
void
-ISA::clear64(const ArmISAParams *p)
+ISA::clear64(const ArmISAParams &p)
{
CPSR cpsr = 0;
Addr rvbar = system->resetAddr();
}
void
-ISA::initID32(const ArmISAParams *p)
+ISA::initID32(const ArmISAParams &p)
{
// Initialize configurable default values
uint32_t midr;
- if (p->midr != 0x0)
- midr = p->midr;
+ if (p.midr != 0x0)
+ midr = p.midr;
else if (highestELIs64)
// Cortex-A57 TRM r0p0 MIDR
midr = 0x410fd070;
miscRegs[MISCREG_MIDR_EL1] = midr;
miscRegs[MISCREG_VPIDR] = midr;
- miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
- miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
- miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
- miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
- miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
- miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+ miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
+ miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
+ miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
+ miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
+ miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
+ miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
- miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
- miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
- miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
- miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+ miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
+ miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
+ miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
+ miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 19, 4,
}
void
-ISA::initID64(const ArmISAParams *p)
+ISA::initID64(const ArmISAParams &p)
{
// Initialize configurable id registers
- miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
- miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
+ miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
+ miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
miscRegs[MISCREG_ID_AA64DFR0_EL1] =
- (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
- (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
+ (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
+ (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
- miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
- miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
- miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
- miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
- miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
- miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
+ miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
+ miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
+ miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
+ miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
miscRegs[MISCREG_ID_DFR0_EL1] =
- (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
+ (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
} // namespace ArmISA
ArmISA::ISA *
-ArmISAParams::create()
+ArmISAParams::create() const
{
- return new ArmISA::ISA(this);
+ return new ArmISA::ISA(*this);
}
void clear();
protected:
- void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
- void clear64(const ArmISAParams *p);
- void initID32(const ArmISAParams *p);
- void initID64(const ArmISAParams *p);
+ void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
+ void clear64(const ArmISAParams &p);
+ void initID32(const ArmISAParams &p);
+ void initID64(const ArmISAParams &p);
void addressTranslation(TLB::ArmTranslationType tran_type,
BaseTLB::Mode mode, Request::Flags flags, RegVal val);
typedef ArmISAParams Params;
- const Params *params() const;
+ const Params ¶ms() const;
- ISA(Params *p);
+ ISA(const Params &p);
};
}
{ 0, NUM_MISCREGS }
};
-ArmKvmCPU::ArmKvmCPU(ArmKvmCPUParams *params)
+ArmKvmCPU::ArmKvmCPU(const ArmKvmCPUParams ¶ms)
: BaseKvmCPU(params),
irqAsserted(false), fiqAsserted(false)
{
}
ArmKvmCPU *
-ArmKvmCPUParams::create()
+ArmKvmCPUParams::create() const
{
- return new ArmKvmCPU(this);
+ return new ArmKvmCPU(*this);
}
class ArmKvmCPU : public BaseKvmCPU
{
public:
- ArmKvmCPU(ArmKvmCPUParams *params);
+ ArmKvmCPU(const ArmKvmCPUParams ¶ms);
virtual ~ArmKvmCPU();
void startup();
MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
};
-ArmV8KvmCPU::ArmV8KvmCPU(ArmV8KvmCPUParams *params)
+ArmV8KvmCPU::ArmV8KvmCPU(const ArmV8KvmCPUParams ¶ms)
: BaseArmKvmCPU(params)
{
}
}
ArmV8KvmCPU *
-ArmV8KvmCPUParams::create()
+ArmV8KvmCPUParams::create() const
{
- return new ArmV8KvmCPU(this);
+ return new ArmV8KvmCPU(*this);
}
class ArmV8KvmCPU : public BaseArmKvmCPU
{
public:
- ArmV8KvmCPU(ArmV8KvmCPUParams *params);
+ ArmV8KvmCPU(const ArmV8KvmCPUParams ¶ms);
virtual ~ArmV8KvmCPU();
void startup() override;
INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
-BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params)
+BaseArmKvmCPU::BaseArmKvmCPU(const BaseArmKvmCPUParams ¶ms)
: BaseKvmCPU(params),
irqAsserted(false), fiqAsserted(false),
virtTimerPin(nullptr), prevDeviceIRQLevel(0)
if (!vm.hasKernelIRQChip())
virtTimerPin = static_cast<ArmSystem *>(system)\
- ->getGenericTimer()->params()->int_virt->get(tc);
+ ->getGenericTimer()->params().int_virt->get(tc);
}
Tick
class BaseArmKvmCPU : public BaseKvmCPU
{
public:
- BaseArmKvmCPU(BaseArmKvmCPUParams *params);
+ BaseArmKvmCPU(const BaseArmKvmCPUParams ¶ms);
virtual ~BaseArmKvmCPU();
void startup() override;
-MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
+MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams &p)
: GicV2(p),
- system(*p->system),
+ system(*p.system),
kernelGic(nullptr),
usingKvm(false)
{
if (auto vm = system.getKvmVM()) {
- kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
- p->it_lines);
+ kernelGic = new KvmKernelGicV2(*vm, p.cpu_addr, p.dist_addr,
+ p.it_lines);
}
}
}
MuxingKvmGic *
-MuxingKvmGicParams::create()
+MuxingKvmGicParams::create() const
{
- return new MuxingKvmGic(this);
+ return new MuxingKvmGic(*this);
}
class MuxingKvmGic : public GicV2
{
public: // SimObject / Serializable / Drainable
- MuxingKvmGic(const MuxingKvmGicParams *p);
+ MuxingKvmGic(const MuxingKvmGicParams &p);
~MuxingKvmGic();
void startup() override;
namespace ArmISA
{
-FsLinux::FsLinux(Params *p) : ArmISA::FsWorkload(p),
- enableContextSwitchStatsDump(p->enable_context_switch_stats_dump)
+FsLinux::FsLinux(const Params &p) : ArmISA::FsWorkload(p),
+ enableContextSwitchStatsDump(p.enable_context_switch_stats_dump)
{}
void
// Load symbols at physical address, we might not want
// to do this permanently, for but early bootup work
// it is helpful.
- if (params()->early_kernel_symbols) {
+ if (params().early_kernel_symbols) {
auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
kernelSymtab.insert(*phys_globals);
Loader::debugSymbolTable.insert(*phys_globals);
// device trees.
bool kernel_has_fdt_support =
kernelSymtab.find("unflatten_device_tree") != kernelSymtab.end();
- bool dtb_file_specified = params()->dtb_filename != "";
+ bool dtb_file_specified = params().dtb_filename != "";
if (kernel_has_fdt_support && dtb_file_specified) {
// Kernel supports flattened device tree and dtb file specified.
// Using Device Tree Blob to describe system configuration.
- inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
- params()->atags_addr + _loadAddrOffset);
+ inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
+ params().atags_addr + _loadAddrOffset);
- auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);
+ auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
if (!dtb_file->addBootCmdLine(
commandLine.c_str(), commandLine.size())) {
warn("couldn't append bootargs to DTB file: %s\n",
- params()->dtb_filename);
+ params().dtb_filename);
}
dtb_file->buildImage().
- offset(params()->atags_addr + _loadAddrOffset).
+ offset(params().atags_addr + _loadAddrOffset).
write(system->physProxy);
delete dtb_file;
} else {
DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
DDUMP(Loader, boot_data, size << 2);
- system->physProxy.writeBlob(params()->atags_addr + _loadAddrOffset,
+ system->physProxy.writeBlob(params().atags_addr + _loadAddrOffset,
boot_data, size << 2);
delete[] boot_data;
// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
for (auto *tc: system->threads) {
tc->setIntReg(0, 0);
- tc->setIntReg(1, params()->machine_type);
- tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+ tc->setIntReg(1, params().machine_type);
+ tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
}
}
}
const std::string dmesg_output = name() + ".dmesg";
- if (params()->panic_on_panic) {
+ if (params().panic_on_panic) {
kernelPanic = addKernelFuncEventOrPanic<Linux::KernelPanic>(
"panic", "Kernel panic in simulated kernel", dmesg_output);
} else {
"panic", "Kernel panic in simulated kernel", dmesg_output);
}
- if (params()->panic_on_oops) {
+ if (params().panic_on_oops) {
kernelOops = addKernelFuncEventOrPanic<Linux::KernelPanic>(
"oops_exit", "Kernel oops in guest", dmesg_output);
} else {
} // namespace ArmISA
ArmISA::FsLinux *
-ArmFsLinuxParams::create()
+ArmFsLinuxParams::create() const
{
- return new ArmISA::FsLinux(this);
+ return new ArmISA::FsLinux(*this);
}
public:
/** Boilerplate params code */
typedef ArmFsLinuxParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(&_params);
+ return dynamic_cast<const Params &>(_params);
}
/** When enabled, dump stats/task info on context switches for
* mappings between taskIds and OS process IDs */
OutputStream *taskFile = nullptr;
- FsLinux(Params *p);
+ FsLinux(const Params &p);
~FsLinux();
void initState() override;
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
{ 0x1005, "set_tls", setTLSFunc64 }
};
-ArmLinuxProcess32::ArmLinuxProcess32(ProcessParams * params,
+ArmLinuxProcess32::ArmLinuxProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
ArmProcess32(params, objFile, _arch)
{}
-ArmLinuxProcess64::ArmLinuxProcess64(ProcessParams * params,
+ArmLinuxProcess64::ArmLinuxProcess64(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
ArmProcess64(params, objFile, _arch)
{}
class ArmLinuxProcess32 : public ArmProcess32, public ArmLinuxProcessBits
{
public:
- ArmLinuxProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
- ::Loader::Arch _arch);
+ ArmLinuxProcess32(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
void initState() override;
class ArmLinuxProcess64 : public ArmProcess64, public ArmLinuxProcessBits
{
public:
- ArmLinuxProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
- ::Loader::Arch _arch);
+ ArmLinuxProcess64(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
void initState() override;
void syscall(ThreadContext *tc) override;
#include "arch/arm/mmu.hh"
ArmISA::MMU *
-ArmMMUParams::create()
+ArmMMUParams::create() const
{
- return new ArmISA::MMU(this);
+ return new ArmISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const ArmMMUParams *p)
+ MMU(const ArmMMUParams &p)
: BaseMMU(p)
{}
};
// ExeTracer Simulation Object
//
Trace::ArmNativeTrace *
-ArmNativeTraceParams::create()
+ArmNativeTraceParams::create() const
{
- return new Trace::ArmNativeTrace(this);
+ return new Trace::ArmNativeTrace(*this);
}
public:
typedef ArmNativeTraceParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- ArmNativeTrace(const Params *p) :
- NativeTrace(p), stopOnPCError(p->stop_on_pc_error)
+ ArmNativeTrace(const Params &p) :
+ NativeTrace(p), stopOnPCError(p.stop_on_pc_error)
{}
void check(NativeTraceRecord *record);
const RegVal PMU::reg_pmcr_wr_mask = 0x39;
-PMU::PMU(const ArmPMUParams *p)
+PMU::PMU(const ArmPMUParams &p)
: SimObject(p), BaseISADevice(),
reg_pmcnten(0), reg_pmcr(0),
reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
reg_pmceid0(0),reg_pmceid1(0),
clock_remainder(0),
- maximumCounterCount(p->eventCounters),
+ maximumCounterCount(p.eventCounters),
cycleCounter(*this, maximumCounterCount),
- cycleCounterEventId(p->cycleEventId),
+ cycleCounterEventId(p.cycleEventId),
swIncrementEvent(nullptr),
reg_pmcr_conf(0),
interrupt(nullptr)
maximumCounterCount);
}
- warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
+ warn_if(!p.interrupt, "ARM PMU: No interrupt specified, interrupt " \
"delivery disabled.\n");
/* Setup the performance counter ID registers */
reg_pmcr_conf.imp = 0x41; // ARM Ltd.
reg_pmcr_conf.idcode = 0x00;
- reg_pmcr_conf.n = p->eventCounters;
+ reg_pmcr_conf.n = p.eventCounters;
// Setup the hard-coded cycle counter, which is equivalent to
// architected counter event type 0x11.
PMU::setThreadContext(ThreadContext *tc)
{
DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
- auto pmu_params = static_cast<const ArmPMUParams *>(params());
+ const auto &pmu_params = static_cast<const ArmPMUParams &>(params());
- if (pmu_params->interrupt)
- interrupt = pmu_params->interrupt->get(tc);
+ if (pmu_params.interrupt)
+ interrupt = pmu_params.interrupt->get(tc);
}
void
} // namespace ArmISA
ArmISA::PMU *
-ArmPMUParams::create()
+ArmPMUParams::create() const
{
- return new ArmISA::PMU(this);
+ return new ArmISA::PMU(*this);
}
*/
class PMU : public SimObject, public ArmISA::BaseISADevice {
public:
- PMU(const ArmPMUParams *p);
+ PMU(const ArmPMUParams &p);
~PMU();
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
using namespace std;
using namespace ArmISA;
-ArmProcess::ArmProcess(ProcessParams *params, ::Loader::ObjectFile *objFile,
- ::Loader::Arch _arch)
+ArmProcess::ArmProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
: Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
+ new EmulationPageTable(params.name, params.pid, PageBytes),
objFile),
arch(_arch)
{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
+ fatal_if(params.useArchPT, "Arch page tables not implemented.");
}
-ArmProcess32::ArmProcess32(ProcessParams *params,
+ArmProcess32::ArmProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
: ArmProcess(params, objFile, _arch)
{
}
ArmProcess64::ArmProcess64(
- ProcessParams *params, ::Loader::ObjectFile *objFile,
+ const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch)
: ArmProcess(params, objFile, _arch)
{
{
protected:
::Loader::Arch arch;
- ArmProcess(ProcessParams * params, ::Loader::ObjectFile *objFile,
+ ArmProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
template<class IntType>
void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
class ArmProcess32 : public ArmProcess
{
protected:
- ArmProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
+ ArmProcess32(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
void initState() override;
class ArmProcess64 : public ArmProcess
{
protected:
- ArmProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
+ ArmProcess64(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
void initState() override;
{"stderr", ::stderr},
};
-ArmSemihosting::ArmSemihosting(const ArmSemihostingParams *p)
+ArmSemihosting::ArmSemihosting(const ArmSemihostingParams &p)
: SimObject(p),
- cmdLine(p->cmd_line),
- memReserve(p->mem_reserve),
- stackSize(p->stack_size),
- timeBase([p]{ struct tm t = p->time; return mkutctime(&t); }()),
+ cmdLine(p.cmd_line),
+ memReserve(p.mem_reserve),
+ stackSize(p.stack_size),
+ timeBase([p]{ struct tm t = p.time; return mkutctime(&t); }()),
tickShift(calcTickShift()),
semiErrno(0),
- filesRootDir(!p->files_root_dir.empty() &&
- p->files_root_dir.back() != '/' ?
- p->files_root_dir + '/' : p->files_root_dir),
- stdin(getSTDIO("stdin", p->stdin, "r")),
- stdout(getSTDIO("stdout", p->stdout, "w")),
- stderr(p->stderr == p->stdout ?
- stdout : getSTDIO("stderr", p->stderr, "w"))
+ filesRootDir(!p.files_root_dir.empty() &&
+ p.files_root_dir.back() != '/' ?
+ p.files_root_dir + '/' : p.files_root_dir),
+ stdin(getSTDIO("stdin", p.stdin, "r")),
+ stdout(getSTDIO("stdout", p.stdout, "w")),
+ stderr(p.stderr == p.stdout ?
+ stdout : getSTDIO("stderr", p.stderr, "w"))
{
// Create an empty place-holder file for position 0 as semi-hosting
// calls typically expect non-zero file handles.
ArmSemihosting *
-ArmSemihostingParams::create()
+ArmSemihostingParams::create() const
{
- return new ArmSemihosting(this);
+ return new ArmSemihosting(*this);
}
SYS_GEM5_PSEUDO_OP = 0x100
};
- ArmSemihosting(const ArmSemihostingParams *p);
+ ArmSemihosting(const ArmSemihostingParams &p);
/** Perform an Arm Semihosting call from aarch64 code. */
bool call64(ThreadContext *tc, bool gem5_ops);
using namespace ArmISA;
-Stage2MMU::Stage2MMU(const Params *p)
- : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
- port(_stage1Tlb->getTableWalker(), p->sys),
- requestorId(p->sys->getRequestorId(_stage1Tlb->getTableWalker()))
+Stage2MMU::Stage2MMU(const Params &p)
+ : SimObject(p), _stage1Tlb(p.tlb), _stage2Tlb(p.stage2_tlb),
+ port(_stage1Tlb->getTableWalker(), p.sys),
+ requestorId(p.sys->getRequestorId(_stage1Tlb->getTableWalker()))
{
// we use the stage-one table walker as the parent of the port,
// and to get our requestor id, this is done to keep things
}
ArmISA::Stage2MMU *
-ArmStage2MMUParams::create()
+ArmStage2MMUParams::create() const
{
- return new ArmISA::Stage2MMU(this);
+ return new ArmISA::Stage2MMU(*this);
}
};
typedef ArmStage2MMUParams Params;
- Stage2MMU(const Params *p);
+ Stage2MMU(const Params &p);
/**
* Get the port that ultimately belongs to the stage-two MMU, but
using namespace Linux;
using namespace ArmISA;
-ArmSystem::ArmSystem(Params *p)
+ArmSystem::ArmSystem(const Params &p)
: System(p),
- _haveSecurity(p->have_security),
- _haveLPAE(p->have_lpae),
- _haveVirtualization(p->have_virtualization),
- _haveCrypto(p->have_crypto),
+ _haveSecurity(p.have_security),
+ _haveLPAE(p.have_lpae),
+ _haveVirtualization(p.have_virtualization),
+ _haveCrypto(p.have_crypto),
_genericTimer(nullptr),
_gic(nullptr),
_pwrCtrl(nullptr),
- _highestELIs64(p->highest_el_is_64),
- _physAddrRange64(p->phys_addr_range_64),
- _haveLargeAsid64(p->have_large_asid_64),
- _haveTME(p->have_tme),
- _haveSVE(p->have_sve),
- _sveVL(p->sve_vl),
- _haveLSE(p->have_lse),
- _havePAN(p->have_pan),
- _haveSecEL2(p->have_secel2),
- semihosting(p->semihosting),
- multiProc(p->multi_proc)
-{
- if (p->auto_reset_addr) {
+ _highestELIs64(p.highest_el_is_64),
+ _physAddrRange64(p.phys_addr_range_64),
+ _haveLargeAsid64(p.have_large_asid_64),
+ _haveTME(p.have_tme),
+ _haveSVE(p.have_sve),
+ _sveVL(p.sve_vl),
+ _haveLSE(p.have_lse),
+ _havePAN(p.have_pan),
+ _haveSecEL2(p.have_secel2),
+ semihosting(p.semihosting),
+ multiProc(p.multi_proc)
+{
+ if (p.auto_reset_addr) {
_resetAddr = workload->getEntry();
} else {
- _resetAddr = p->reset_addr;
+ _resetAddr = p.reset_addr;
warn_if(workload->getEntry() != _resetAddr,
"Workload entry point %#x and reset address %#x are different",
workload->getEntry(), _resetAddr);
}
ArmSystem *
-ArmSystemParams::create()
+ArmSystemParams::create() const
{
- return new ArmSystem(this);
+ return new ArmSystem(*this);
}
static constexpr Addr PageShift = ArmISA::PageShift;
typedef ArmSystemParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- ArmSystem(Params *p);
+ ArmSystem(const Params &p);
/** true if this a multiprocessor system */
bool multiProc;
using namespace ArmISA;
-TableWalker::TableWalker(const Params *p)
+TableWalker::TableWalker(const Params &p)
: ClockedObject(p),
stage2Mmu(NULL), port(NULL), requestorId(Request::invldRequestorId),
- isStage2(p->is_stage2), tlb(NULL),
+ isStage2(p.is_stage2), tlb(NULL),
currState(NULL), pending(false),
- numSquashable(p->num_squash_per_cycle),
+ numSquashable(p.num_squash_per_cycle),
stats(this),
pendingReqs(0),
pendingChangeTick(curTick()),
// Cache system-level properties
if (FullSystem) {
- ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys);
+ ArmSystem *armSys = dynamic_cast<ArmSystem *>(p.sys);
assert(armSys);
haveSecurity = armSys->haveSecurity();
_haveLPAE = armSys->haveLPAE();
void
TableWalker::drainResume()
{
- if (params()->sys->isTimingMode() && currState) {
+ if (params().sys->isTimingMode() && currState) {
delete currState;
currState = NULL;
pendingChange();
}
ArmISA::TableWalker *
-ArmTableWalkerParams::create()
+ArmTableWalkerParams::create() const
{
- return new ArmISA::TableWalker(this);
+ return new ArmISA::TableWalker(*this);
}
LookupLevel
public:
typedef ArmTableWalkerParams Params;
- TableWalker(const Params *p);
+ TableWalker(const Params &p);
virtual ~TableWalker();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void init() override;
using namespace std;
using namespace ArmISA;
-TLB::TLB(const ArmTLBParams *p)
- : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
- isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
- directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
+TLB::TLB(const ArmTLBParams &p)
+ : BaseTLB(p), table(new TlbEntry[p.size]), size(p.size),
+ isStage2(p.is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
+ directToStage2(false), tableWalker(p.walker), stage2Tlb(NULL),
stage2Mmu(NULL), test(nullptr), stats(this), rangeMRU(1),
aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
isHyp(false), asid(0), vmid(0), hcr(0), dacr(0),
miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
{
- const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
+ const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p.sys);
tableWalker->setTlb(this);
ArmISA::TLB *
-ArmTLBParams::create()
+ArmTLBParams::create() const
{
- return new ArmISA::TLB(this);
+ return new ArmISA::TLB(*this);
}
int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
public:
- TLB(const ArmTLBParams *p);
- TLB(const Params *p, int _size, TableWalker *_walker);
+ TLB(const ArmTLBParams &p);
+ TLB(const Params &p, int _size, TableWalker *_walker);
/** Lookup an entry in the TLB
* @param vpn virtual address
ArmTranslationType tranType = NormalTran);
public:
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
inline void invalidateMiscReg() { miscRegValid = false; }
} // namespace Trace
Trace::TarmacParser *
-TarmacParserParams::create()
+TarmacParserParams::create() const
{
- return new Trace::TarmacParser(this);
+ return new Trace::TarmacParser(*this);
}
public:
typedef TarmacParserParams Params;
- TarmacParser(const Params *p) : InstTracer(p), startPc(p->start_pc),
- exitOnDiff(p->exit_on_diff),
- exitOnInsnDiff(p->exit_on_insn_diff),
- memWrCheck(p->mem_wr_check),
- ignoredAddrRange(p->ignore_mem_addr),
- cpuId(p->cpu_id),
+ TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
+ exitOnDiff(p.exit_on_diff),
+ exitOnInsnDiff(p.exit_on_insn_diff),
+ memWrCheck(p.mem_wr_check),
+ ignoredAddrRange(p.ignore_mem_addr),
+ cpuId(p.cpu_id),
macroopInProgress(false)
{
assert(!(exitOnDiff && exitOnInsnDiff));
- trace.open(p->path_to_trace.c_str());
+ trace.open(p.path_to_trace.c_str());
if (startPc == 0x0) {
started = true;
} else {
return "cpu" + std::to_string(id);
}
-TarmacTracer::TarmacTracer(const Params *p)
+TarmacTracer::TarmacTracer(const Params &p)
: InstTracer(p),
- startTick(p->start_tick),
- endTick(p->end_tick)
+ startTick(p.start_tick),
+ endTick(p.end_tick)
{
// Wrong parameter setting: The trace end happens before the
// trace start.
} // namespace Trace
Trace::TarmacTracer *
-TarmacTracerParams::create()
+TarmacTracerParams::create() const
{
- return new Trace::TarmacTracer(this);
+ return new Trace::TarmacTracer(*this);
}
public:
typedef TarmacTracerParams Params;
- TarmacTracer(const Params *p);
+ TarmacTracer(const Params &p);
/**
* Generates a TarmacTracerRecord, depending on the Tarmac version.
public:
typedef BaseInterruptsParams Params;
- BaseInterrupts(Params *p) : SimObject(p) {}
+ BaseInterrupts(const Params &p) : SimObject(p) {}
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/*
protected:
typedef BaseMMUParams Params;
- BaseMMU(const Params *p)
- : SimObject(p), dtb(p->dtb), itb(p->itb)
+ BaseMMU(const Params &p)
+ : SimObject(p), dtb(p.dtb), itb(p.itb)
{}
public:
class BaseTLB : public SimObject
{
protected:
- BaseTLB(const Params *p) : SimObject(p) {}
+ BaseTLB(const Params &p) : SimObject(p) {}
public:
}
MipsISA::Interrupts *
-MipsInterruptsParams::create()
+MipsInterruptsParams::create() const
{
- return new MipsISA::Interrupts(this);
+ return new MipsISA::Interrupts(*this);
}
public:
typedef MipsInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params * p) : BaseInterrupts(p) {}
+ Interrupts(const Params &p) : BaseInterrupts(p) {}
// post(int int_num, int index) is responsible
// for posting an interrupt. It sets a bit
"LLFlag"
};
-ISA::ISA(Params *p) : BaseISA(p), numThreads(p->num_threads),
- numVpes(p->num_vpes)
+ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
+ numVpes(p.num_vpes)
{
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
clear();
}
-const MipsISAParams *
+const MipsISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void
}
MipsISA::ISA *
-MipsISAParams::create()
+MipsISAParams::create() const
{
- return new MipsISA::ISA(this);
+ return new MipsISA::ISA(*this);
}
static std::string miscRegNames[NumMiscRegs];
public:
- const Params *params() const;
+ const Params ¶ms() const;
- ISA(Params *p);
+ ISA(const Params &p);
RegId flattenRegId(const RegId& regId) const { return regId; }
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
if (obj_file->getArch() != ::Loader::Mips)
return nullptr;
{ 4319, "eventfd" }
};
-MipsLinuxProcess::MipsLinuxProcess(ProcessParams * params,
+MipsLinuxProcess::MipsLinuxProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
MipsProcess(params, objFile)
{}
{
public:
/// Constructor.
- MipsLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ MipsLinuxProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
/// The target system's hostname.
static const char *hostname;
#include "arch/mips/mmu.hh"
MipsISA::MMU *
-MipsMMUParams::create()
+MipsMMUParams::create() const
{
- return new MipsISA::MMU(this);
+ return new MipsISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const MipsMMUParams *p)
+ MMU(const MipsMMUParams &p)
: BaseMMU(p)
{}
};
using namespace std;
using namespace MipsISA;
-MipsProcess::MipsProcess(ProcessParams *params, ::Loader::ObjectFile *objFile)
+MipsProcess::MipsProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile)
: Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
+ new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
+ fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Set up stack. On MIPS, stack starts at the top of kuseg
// user address space. MIPS stack grows down from here
Addr stack_base = 0x7FFFFFFF;
class MipsProcess : public Process
{
protected:
- MipsProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ MipsProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
void initState();
// MIPS TLB
//
-TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), nlu(0)
+TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
{
table = new PTE[size];
memset(table, 0, sizeof(PTE[size]));
}
MipsISA::TLB *
-MipsTLBParams::create()
+MipsTLBParams::create() const
{
- return new MipsISA::TLB(this);
+ return new MipsISA::TLB(*this);
}
public:
typedef MipsTLBParams Params;
- TLB(const Params *p);
+ TLB(const Params &p);
int probeEntry(Addr vpn,uint8_t) const;
MipsISA::PTE *getEntry(unsigned) const;
#include "arch/power/interrupts.hh"
PowerISA::Interrupts *
-PowerInterruptsParams::create()
+PowerInterruptsParams::create() const
{
- return new PowerISA::Interrupts(this);
+ return new PowerISA::Interrupts(*this);
}
public:
typedef PowerInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params *p) : BaseInterrupts(p) {}
+ Interrupts(const Params &p) : BaseInterrupts(p) {}
void
post(int int_num, int index)
namespace PowerISA
{
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
{
clear();
}
-const PowerISAParams *
+const PowerISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
}
PowerISA::ISA *
-PowerISAParams::create()
+PowerISAParams::create() const
{
- return new PowerISA::ISA(this);
+ return new PowerISA::ISA(*this);
}
return reg;
}
- const Params *params() const;
+ const Params ¶ms() const;
- ISA(Params *p);
+ ISA(const Params &p);
};
} // namespace PowerISA
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
if (obj_file->getArch() != ::Loader::Power)
return nullptr;
{ 346, "epoll_pwait" },
};
-PowerLinuxProcess::PowerLinuxProcess(ProcessParams * params,
- ::Loader::ObjectFile *objFile) :
+PowerLinuxProcess::PowerLinuxProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile) :
PowerProcess(params, objFile)
{}
class PowerLinuxProcess : public PowerProcess
{
public:
- PowerLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ PowerLinuxProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
void initState() override;
#include "arch/power/mmu.hh"
PowerISA::MMU *
-PowerMMUParams::create()
+PowerMMUParams::create() const
{
- return new PowerISA::MMU(this);
+ return new PowerISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const PowerMMUParams *p)
+ MMU(const PowerMMUParams &p)
: BaseMMU(p)
{}
};
using namespace PowerISA;
PowerProcess::PowerProcess(
- ProcessParams *params, ::Loader::ObjectFile *objFile)
+ const ProcessParams ¶ms, ::Loader::ObjectFile *objFile)
: Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
+ new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
+ fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Set up break point (Top of Heap)
Addr brk_point = image.maxAddr();
brk_point = roundUp(brk_point, PageBytes);
class PowerProcess : public Process
{
protected:
- PowerProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ PowerProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
void initState() override;
#define MODE2MASK(X) (1 << (X))
-TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), nlu(0)
+TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
{
table = new PowerISA::PTE[size];
memset(table, 0, sizeof(PowerISA::PTE[size]));
}
PowerISA::TLB *
-PowerTLBParams::create()
+PowerTLBParams::create() const
{
- return new PowerISA::TLB(this);
+ return new PowerISA::TLB(*this);
}
public:
typedef PowerTLBParams Params;
- TLB(const Params *p);
+ TLB(const Params &p);
virtual ~TLB();
void takeOverFrom(BaseTLB *otlb) override {}
namespace RiscvISA
{
-BareMetal::BareMetal(Params *p) : RiscvISA::FsWorkload(p),
- bootloader(Loader::createObjectFile(p->bootloader))
+BareMetal::BareMetal(const Params &p) : RiscvISA::FsWorkload(p),
+ bootloader(Loader::createObjectFile(p.bootloader))
{
- fatal_if(!bootloader, "Could not load bootloader file %s.", p->bootloader);
+ fatal_if(!bootloader, "Could not load bootloader file %s.", p.bootloader);
_resetVect = bootloader->entryPoint();
bootloaderSymtab = bootloader->symtab();
}
} // namespace RiscvISA
RiscvISA::BareMetal *
-RiscvBareMetalParams::create()
+RiscvBareMetalParams::create() const
{
- return new RiscvISA::BareMetal(this);
+ return new RiscvISA::BareMetal(*this);
}
public:
typedef RiscvBareMetalParams Params;
- BareMetal(Params *p);
+ BareMetal(const Params &p);
~BareMetal();
void initState() override;
Addr _resetVect;
public:
- FsWorkload(RiscvFsWorkloadParams *p) : Workload(p),
- _isBareMetal(p->bare_metal), _resetVect(p->reset_vect)
+ FsWorkload(const RiscvFsWorkloadParams &p) : Workload(p),
+ _isBareMetal(p.bare_metal), _resetVect(p.reset_vect)
{}
// return reset vector
#include "arch/riscv/interrupts.hh"
RiscvISA::Interrupts *
-RiscvInterruptsParams::create()
+RiscvInterruptsParams::create() const
{
- return new RiscvISA::Interrupts(this);
+ return new RiscvISA::Interrupts(*this);
}
public:
typedef RiscvInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params * p) : BaseInterrupts(p), ip(0), ie(0) {}
+ Interrupts(const Params &p) : BaseInterrupts(p), ip(0), ie(0) {}
std::bitset<NumInterruptTypes>
globalMask() const
[MISCREG_FRM] = "FRM",
}};
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
{
miscRegFile.resize(NumMiscRegs);
clear();
}
-const RiscvISAParams *
+const RiscvISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void ISA::clear()
}
RiscvISA::ISA *
-RiscvISAParams::create()
+RiscvISAParams::create() const
{
- return new RiscvISA::ISA(this);
+ return new RiscvISA::ISA(*this);
}
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
- const Params *params() const;
+ const Params ¶ms() const;
- ISA(Params *p);
+ ISA(const Params &p);
};
} // namespace RiscvISA
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
{ 2011, "getmainvars" }
};
-RiscvLinuxProcess64::RiscvLinuxProcess64(ProcessParams * params,
+RiscvLinuxProcess64::RiscvLinuxProcess64(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) : RiscvProcess64(params, objFile)
{}
syscallDescs.get(tc->readIntReg(SyscallNumReg))->doSyscall(tc);
}
-RiscvLinuxProcess32::RiscvLinuxProcess32(ProcessParams * params,
+RiscvLinuxProcess32::RiscvLinuxProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) : RiscvProcess32(params, objFile)
{}
{
public:
/// Constructor.
- RiscvLinuxProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ RiscvLinuxProcess64(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
/// The target system's hostname.
static const char *hostname;
{
public:
/// Constructor.
- RiscvLinuxProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ RiscvLinuxProcess32(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
/// The target system's hostname.
static const char *hostname;
#include "arch/riscv/mmu.hh"
RiscvISA::MMU *
-RiscvMMUParams::create()
+RiscvMMUParams::create() const
{
- return new RiscvISA::MMU(this);
+ return new RiscvISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const RiscvMMUParams *p)
+ MMU(const RiscvMMUParams &p)
: BaseMMU(p)
{}
};
} /* end namespace RiscvISA */
RiscvISA::Walker *
-RiscvPagetableWalkerParams::create()
+RiscvPagetableWalkerParams::create() const
{
- return new RiscvISA::Walker(this);
+ return new RiscvISA::Walker(*this);
}
typedef RiscvPagetableWalkerParams Params;
- const Params *
+ const Params &
params() const
{
- return static_cast<const Params *>(_params);
+ return static_cast<const Params &>(_params);
}
- Walker(const Params *params) :
+ Walker(const Params ¶ms) :
ClockedObject(params), port(name() + ".port", this),
- funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
+ funcState(this, NULL, NULL, true), tlb(NULL), sys(params.system),
requestorId(sys->getRequestorId(this)),
- numSquashable(params->num_squash_per_cycle),
+ numSquashable(params.num_squash_per_cycle),
startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
{
}
using namespace std;
using namespace RiscvISA;
-RiscvProcess::RiscvProcess(ProcessParams *params,
+RiscvProcess::RiscvProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
+ new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
+ fatal_if(params.useArchPT, "Arch page tables not implemented.");
}
-RiscvProcess64::RiscvProcess64(ProcessParams *params,
+RiscvProcess64::RiscvProcess64(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
RiscvProcess(params, objFile)
{
max_stack_size, next_thread_stack_base, mmap_end);
}
-RiscvProcess32::RiscvProcess32(ProcessParams *params,
+RiscvProcess32::RiscvProcess32(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
RiscvProcess(params, objFile)
{
class RiscvProcess : public Process
{
protected:
- RiscvProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ RiscvProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
template<class IntType>
void argsInit(int pageSize);
class RiscvProcess64 : public RiscvProcess
{
protected:
- RiscvProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ RiscvProcess64(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
void initState() override;
};
class RiscvProcess32 : public RiscvProcess
{
protected:
- RiscvProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ RiscvProcess32(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
void initState() override;
};
return (static_cast<Addr>(asid) << 48) | vpn;
}
-TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), tlb(size), lruSeq(0), stats(this)
+TLB::TLB(const Params &p)
+ : BaseTLB(p), size(p.size), tlb(size), lruSeq(0), stats(this)
{
for (size_t x = 0; x < size; x++) {
tlb[x].trieHandle = NULL;
freeList.push_back(&tlb[x]);
}
- walker = p->walker;
+ walker = p.walker;
walker->setTLB(this);
}
}
RiscvISA::TLB *
-RiscvTLBParams::create()
+RiscvTLBParams::create() const
{
- return new TLB(this);
+ return new TLB(*this);
}
public:
typedef RiscvTLBParams Params;
- TLB(const Params *p);
+ TLB(const Params &p);
Walker *getWalker();
} // namespace SparcISA
SparcISA::FsWorkload *
-SparcFsWorkloadParams::create()
+SparcFsWorkloadParams::create() const
{
- return new SparcISA::FsWorkload(this);
+ return new SparcISA::FsWorkload(*this);
}
Loader::SymbolTable defaultSymtab;
public:
- FsWorkload(SparcFsWorkloadParams *params) : Workload(params) {}
+ FsWorkload(const SparcFsWorkloadParams ¶ms) : Workload(params) {}
void initState() override;
Addr
#include "arch/sparc/interrupts.hh"
SparcISA::Interrupts *
-SparcInterruptsParams::create()
+SparcInterruptsParams::create() const
{
- return new SparcISA::Interrupts(this);
+ return new SparcISA::Interrupts(*this);
}
typedef SparcInterruptsParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Interrupts(Params * p) : BaseInterrupts(p)
+ Interrupts(const Params &p) : BaseInterrupts(p)
{
clearAll();
}
static const PSTATE PstateMask = buildPstateMask();
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
{
clear();
}
-const SparcISAParams *
+const SparcISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void
}
SparcISA::ISA *
-SparcISAParams::create()
+SparcISAParams::create() const
{
- return new SparcISA::ISA(this);
+ return new SparcISA::ISA(*this);
}
typedef SparcISAParams Params;
- const Params *params() const;
+ const Params ¶ms() const;
- ISA(Params *p);
+ ISA(const Params &p);
};
}
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
} // anonymous namespace
-Sparc32LinuxProcess::Sparc32LinuxProcess(ProcessParams * params,
+Sparc32LinuxProcess::Sparc32LinuxProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile)
: Sparc32Process(params, objFile)
{}
}
}
-Sparc64LinuxProcess::Sparc64LinuxProcess(ProcessParams * params,
+Sparc64LinuxProcess::Sparc64LinuxProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile)
: Sparc64Process(params, objFile)
{}
{
public:
/// Constructor.
- Sparc32LinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ Sparc32LinuxProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
void syscall(ThreadContext *tc) override;
{
public:
/// Constructor.
- Sparc64LinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ Sparc64LinuxProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
void syscall(ThreadContext *tc) override;
#include "arch/sparc/mmu.hh"
SparcISA::MMU *
-SparcMMUParams::create()
+SparcMMUParams::create() const
{
- return new SparcISA::MMU(this);
+ return new SparcISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const SparcMMUParams *p)
+ MMU(const SparcMMUParams &p)
: BaseMMU(p)
{}
};
// ExeTracer Simulation Object
//
Trace::SparcNativeTrace *
-SparcNativeTraceParams::create()
+SparcNativeTraceParams::create() const
{
- return new Trace::SparcNativeTrace(this);
+ return new Trace::SparcNativeTrace(*this);
};
class SparcNativeTrace : public NativeTrace
{
public:
- SparcNativeTrace(const Params *p) : NativeTrace(p)
+ SparcNativeTrace(const Params &p) : NativeTrace(p)
{}
void check(NativeTraceRecord *record);
INTREG_O0, INTREG_O1, INTREG_O2, INTREG_O3, INTREG_O4, INTREG_O5
};
-SparcProcess::SparcProcess(ProcessParams *params,
+SparcProcess::SparcProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile, Addr _StackBias)
: Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
+ new EmulationPageTable(params.name, params.pid, PageBytes),
objFile),
StackBias(_StackBias)
{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
+ fatal_if(params.useArchPT, "Arch page tables not implemented.");
// Initialize these to 0s
fillStart = 0;
spillStart = 0;
// The locations of the fill and spill handlers
Addr fillStart, spillStart;
- SparcProcess(ProcessParams * params, ::Loader::ObjectFile *objFile,
+ SparcProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
Addr _StackBias);
void initState() override;
{
protected:
- Sparc32Process(ProcessParams * params, ::Loader::ObjectFile *objFile)
+ Sparc32Process(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile)
: SparcProcess(params, objFile, 0)
{
Addr brk_point = image.maxAddr();
{
protected:
- Sparc64Process(ProcessParams * params, ::Loader::ObjectFile *objFile)
+ Sparc64Process(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile)
: SparcProcess(params, objFile, 2047)
{
Addr brk_point = image.maxAddr();
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
{ 255, "umount2" }
};
-SparcSolarisProcess::SparcSolarisProcess(ProcessParams *params,
+SparcSolarisProcess::SparcSolarisProcess(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
Sparc64Process(params, objFile)
{}
{
public:
/// Constructor.
- SparcSolarisProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+ SparcSolarisProcess(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
/// The target system's hostname.
static const char *hostname;
* */
namespace SparcISA {
-TLB::TLB(const Params *p)
- : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
+TLB::TLB(const Params &p)
+ : BaseTLB(p), size(p.size), usedEntries(0), lastReplaced(0),
cacheState(0), cacheValid(false)
{
// To make this work you'll have to change the hypervisor and OS
} // namespace SparcISA
SparcISA::TLB *
-SparcTLBParams::create()
+SparcTLBParams::create() const
{
- return new SparcISA::TLB(this);
+ return new SparcISA::TLB(*this);
}
public:
typedef SparcTLBParams Params;
- TLB(const Params *p);
+ TLB(const Params &p);
void takeOverFrom(BaseTLB *otlb) override {}
const char X86ISA::ACPI::RSDP::signature[] = "RSD PTR ";
-X86ISA::ACPI::RSDP::RSDP(Params *p) : SimObject(p), oemID(p->oem_id),
- revision(p->revision), rsdt(p->rsdt), xsdt(p->xsdt)
+X86ISA::ACPI::RSDP::RSDP(const Params &p) : SimObject(p), oemID(p.oem_id),
+ revision(p.revision), rsdt(p.rsdt), xsdt(p.xsdt)
{}
-X86ISA::ACPI::SysDescTable::SysDescTable(Params *p,
+X86ISA::ACPI::SysDescTable::SysDescTable(const Params &p,
const char * _signature, uint8_t _revision) : SimObject(p),
signature(_signature), revision(_revision),
- oemID(p->oem_id), oemTableID(p->oem_table_id),
- oemRevision(p->oem_revision),
- creatorID(p->creator_id), creatorRevision(p->creator_revision)
+ oemID(p.oem_id), oemTableID(p.oem_table_id),
+ oemRevision(p.oem_revision),
+ creatorID(p.creator_id), creatorRevision(p.creator_revision)
{}
-X86ISA::ACPI::RSDT::RSDT(Params *p) :
- SysDescTable(p, "RSDT", 1), entries(p->entries)
+X86ISA::ACPI::RSDT::RSDT(const Params &p) :
+ SysDescTable(p, "RSDT", 1), entries(p.entries)
{}
-X86ISA::ACPI::XSDT::XSDT(Params *p) :
- SysDescTable(p, "XSDT", 1), entries(p->entries)
+X86ISA::ACPI::XSDT::XSDT(const Params &p) :
+ SysDescTable(p, "XSDT", 1), entries(p.entries)
{}
X86ISA::ACPI::RSDP *
-X86ACPIRSDPParams::create()
+X86ACPIRSDPParams::create() const
{
- return new X86ISA::ACPI::RSDP(this);
+ return new X86ISA::ACPI::RSDP(*this);
}
X86ISA::ACPI::RSDT *
-X86ACPIRSDTParams::create()
+X86ACPIRSDTParams::create() const
{
- return new X86ISA::ACPI::RSDT(this);
+ return new X86ISA::ACPI::RSDT(*this);
}
X86ISA::ACPI::XSDT *
-X86ACPIXSDTParams::create()
+X86ACPIXSDTParams::create() const
{
- return new X86ISA::ACPI::XSDT(this);
+ return new X86ISA::ACPI::XSDT(*this);
}
XSDT * xsdt;
public:
- RSDP(Params *p);
+ RSDP(const Params &p);
};
class SysDescTable : public SimObject
uint32_t creatorRevision;
public:
- SysDescTable(Params *p, const char * _signature, uint8_t _revision);
+ SysDescTable(const Params &p, const char * _signature, uint8_t _revision);
};
class RSDT : public SysDescTable
std::vector<SysDescTable *> entries;
public:
- RSDT(Params *p);
+ RSDT(const Params &p);
};
class XSDT : public SysDescTable
std::vector<SysDescTable *> entries;
public:
- XSDT(Params *p);
+ XSDT(const Params &p);
};
} // namespace ACPI
}
E820Table *
-X86E820TableParams::create()
+X86E820TableParams::create() const
{
- return new E820Table(this);
+ return new E820Table(*this);
}
E820Entry *
-X86E820EntryParams::create()
+X86E820EntryParams::create() const
{
- return new E820Entry(this);
+ return new E820Entry(*this);
}
public:
typedef X86E820EntryParams Params;
- E820Entry(Params *p) :
- SimObject(p), addr(p->addr), size(p->size), type(p->range_type)
+ E820Entry(const Params &p) :
+ SimObject(p), addr(p.addr), size(p.size), type(p.range_type)
{}
};
public:
typedef X86E820TableParams Params;
- E820Table(Params *p) : SimObject(p), entries(p->entries)
+ E820Table(const Params &p) : SimObject(p), entries(p.entries)
{}
void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
return 16;
}
-X86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) :
- SimObject(p), tableAddr(0), specRev(p->spec_rev),
- defaultConfig(p->default_config), imcrPresent(p->imcr_present)
+X86ISA::IntelMP::FloatingPointer::FloatingPointer(const Params &p) :
+ SimObject(p), tableAddr(0), specRev(p.spec_rev),
+ defaultConfig(p.default_config), imcrPresent(p.imcr_present)
{}
X86ISA::IntelMP::FloatingPointer *
-X86IntelMPFloatingPointerParams::create()
+X86IntelMPFloatingPointerParams::create() const
{
- return new X86ISA::IntelMP::FloatingPointer(this);
+ return new X86ISA::IntelMP::FloatingPointer(*this);
}
Addr
return 1;
}
-X86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) :
+X86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(
+ const Params &p, uint8_t _type) :
SimObject(p), type(_type)
{}
return 1;
}
-X86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p,
+X86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(const Params &p,
uint8_t _type, uint8_t _length) :
SimObject(p), type(_type), length(_length)
{}
return offset + extOffset;
};
-X86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p),
- specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id),
- oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size),
- localApic(p->local_apic),
- baseEntries(p->base_entries), extEntries(p->ext_entries)
+X86ISA::IntelMP::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
+ specRev(p.spec_rev), oemID(p.oem_id), productID(p.product_id),
+ oemTableAddr(p.oem_table_addr), oemTableSize(p.oem_table_size),
+ localApic(p.local_apic),
+ baseEntries(p.base_entries), extEntries(p.ext_entries)
{}
X86ISA::IntelMP::ConfigTable *
-X86IntelMPConfigTableParams::create()
+X86IntelMPConfigTableParams::create() const
{
- return new X86ISA::IntelMP::ConfigTable(this);
+ return new X86ISA::IntelMP::ConfigTable(*this);
}
Addr
return 20;
}
-X86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0),
- localApicID(p->local_apic_id), localApicVersion(p->local_apic_version),
- cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags)
+X86ISA::IntelMP::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
+ localApicID(p.local_apic_id), localApicVersion(p.local_apic_version),
+ cpuFlags(0), cpuSignature(0), featureFlags(p.feature_flags)
{
- if (p->enable)
+ if (p.enable)
cpuFlags |= (1 << 0);
- if (p->bootstrap)
+ if (p.bootstrap)
cpuFlags |= (1 << 1);
- replaceBits(cpuSignature, 3, 0, p->stepping);
- replaceBits(cpuSignature, 7, 4, p->model);
- replaceBits(cpuSignature, 11, 8, p->family);
+ replaceBits(cpuSignature, 3, 0, p.stepping);
+ replaceBits(cpuSignature, 7, 4, p.model);
+ replaceBits(cpuSignature, 11, 8, p.family);
}
X86ISA::IntelMP::Processor *
-X86IntelMPProcessorParams::create()
+X86IntelMPProcessorParams::create() const
{
- return new X86ISA::IntelMP::Processor(this);
+ return new X86ISA::IntelMP::Processor(*this);
}
Addr
return 8;
}
-X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1),
- busID(p->bus_id), busType(p->bus_type)
+X86ISA::IntelMP::Bus::Bus(const Params &p) : BaseConfigEntry(p, 1),
+ busID(p.bus_id), busType(p.bus_type)
{}
X86ISA::IntelMP::Bus *
-X86IntelMPBusParams::create()
+X86IntelMPBusParams::create() const
{
- return new X86ISA::IntelMP::Bus(this);
+ return new X86ISA::IntelMP::Bus(*this);
}
Addr
return 8;
}
-X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2),
- id(p->id), version(p->version), flags(0), address(p->address)
+X86ISA::IntelMP::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
+ id(p.id), version(p.version), flags(0), address(p.address)
{
- if (p->enable)
+ if (p.enable)
flags |= 1;
}
X86ISA::IntelMP::IOAPIC *
-X86IntelMPIOAPICParams::create()
+X86IntelMPIOAPICParams::create() const
{
- return new X86ISA::IntelMP::IOAPIC(this);
+ return new X86ISA::IntelMP::IOAPIC(*this);
}
Addr
return 8;
}
-X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) :
- IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3,
- p->source_bus_id, p->source_bus_irq,
- p->dest_io_apic_id, p->dest_io_apic_intin)
+X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(const Params &p) :
+ IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 3,
+ p.source_bus_id, p.source_bus_irq,
+ p.dest_io_apic_id, p.dest_io_apic_intin)
{}
X86ISA::IntelMP::IOIntAssignment *
-X86IntelMPIOIntAssignmentParams::create()
+X86IntelMPIOIntAssignmentParams::create() const
{
- return new X86ISA::IntelMP::IOIntAssignment(this);
+ return new X86ISA::IntelMP::IOIntAssignment(*this);
}
-X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) :
- IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4,
- p->source_bus_id, p->source_bus_irq,
- p->dest_local_apic_id, p->dest_local_apic_intin)
+X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(const Params &p) :
+ IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 4,
+ p.source_bus_id, p.source_bus_irq,
+ p.dest_local_apic_id, p.dest_local_apic_intin)
{}
X86ISA::IntelMP::LocalIntAssignment *
-X86IntelMPLocalIntAssignmentParams::create()
+X86IntelMPLocalIntAssignmentParams::create() const
{
- return new X86ISA::IntelMP::LocalIntAssignment(this);
+ return new X86ISA::IntelMP::LocalIntAssignment(*this);
}
Addr
return length;
}
-X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) :
+X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(const Params &p) :
ExtConfigEntry(p, 128, 20),
- busID(p->bus_id), addrType(p->address_type),
- addr(p->address), addrLength(p->length)
+ busID(p.bus_id), addrType(p.address_type),
+ addr(p.address), addrLength(p.length)
{}
X86ISA::IntelMP::AddrSpaceMapping *
-X86IntelMPAddrSpaceMappingParams::create()
+X86IntelMPAddrSpaceMappingParams::create() const
{
- return new X86ISA::IntelMP::AddrSpaceMapping(this);
+ return new X86ISA::IntelMP::AddrSpaceMapping(*this);
}
Addr
return length;
}
-X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) :
+X86ISA::IntelMP::BusHierarchy::BusHierarchy(const Params &p) :
ExtConfigEntry(p, 129, 8),
- busID(p->bus_id), info(0), parentBus(p->parent_bus)
+ busID(p.bus_id), info(0), parentBus(p.parent_bus)
{
- if (p->subtractive_decode)
+ if (p.subtractive_decode)
info |= 1;
}
X86ISA::IntelMP::BusHierarchy *
-X86IntelMPBusHierarchyParams::create()
+X86IntelMPBusHierarchyParams::create() const
{
- return new X86ISA::IntelMP::BusHierarchy(this);
+ return new X86ISA::IntelMP::BusHierarchy(*this);
}
Addr
return length;
}
-X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) :
+X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(const Params &p) :
ExtConfigEntry(p, 130, 8),
- busID(p->bus_id), mod(0), rangeList(p->range_list)
+ busID(p.bus_id), mod(0), rangeList(p.range_list)
{
- if (p->add)
+ if (p.add)
mod |= 1;
}
X86ISA::IntelMP::CompatAddrSpaceMod *
-X86IntelMPCompatAddrSpaceModParams::create()
+X86IntelMPCompatAddrSpaceModParams::create() const
{
- return new X86ISA::IntelMP::CompatAddrSpaceMod(this);
+ return new X86ISA::IntelMP::CompatAddrSpaceMod(*this);
}
tableAddr = addr;
}
- FloatingPointer(Params * p);
+ FloatingPointer(const Params &p);
};
class BaseConfigEntry : public SimObject
virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- BaseConfigEntry(Params * p, uint8_t _type);
+ BaseConfigEntry(const Params &p, uint8_t _type);
};
class ExtConfigEntry : public SimObject
virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
+ ExtConfigEntry(const Params &p, uint8_t _type, uint8_t _length);
};
class ConfigTable : public SimObject
public:
Addr writeOut(PortProxy& proxy, Addr addr);
- ConfigTable(Params * p);
+ ConfigTable(const Params &p);
};
class Processor : public BaseConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- Processor(Params * p);
+ Processor(const Params &p);
};
class Bus : public BaseConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- Bus(Params * p);
+ Bus(const Params &p);
};
class IOAPIC : public BaseConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- IOAPIC(Params * p);
+ IOAPIC(const Params &p);
};
class IntAssignment : public BaseConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- IntAssignment(X86IntelMPBaseConfigEntryParams * p,
+ IntAssignment(const X86IntelMPBaseConfigEntryParams &p,
Enums::X86IntelMPInterruptType _interruptType,
Enums::X86IntelMPPolarity polarity,
Enums::X86IntelMPTriggerMode trigger,
typedef X86IntelMPIOIntAssignmentParams Params;
public:
- IOIntAssignment(Params * p);
+ IOIntAssignment(const Params &p);
};
class LocalIntAssignment : public IntAssignment
typedef X86IntelMPLocalIntAssignmentParams Params;
public:
- LocalIntAssignment(Params * p);
+ LocalIntAssignment(const Params &p);
};
class AddrSpaceMapping : public ExtConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- AddrSpaceMapping(Params * p);
+ AddrSpaceMapping(const Params &p);
};
class BusHierarchy : public ExtConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- BusHierarchy(Params * p);
+ BusHierarchy(const Params &p);
};
class CompatAddrSpaceMod : public ExtConfigEntry
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
- CompatAddrSpaceMod(Params * p);
+ CompatAddrSpaceMod(const Params &p);
};
} //IntelMP
return length + getStringLength();
}
-X86ISA::SMBios::SMBiosStructure::SMBiosStructure(Params * p, uint8_t _type) :
+X86ISA::SMBios::SMBiosStructure::SMBiosStructure(
+ const Params &p, uint8_t _type) :
SimObject(p), type(_type), handle(0), stringFields(false)
{}
}
int
-X86ISA::SMBios::SMBiosStructure::addString(string & newString)
+X86ISA::SMBios::SMBiosStructure::addString(const string &new_string)
{
stringFields = true;
// If a string is empty, treat it as not existing. The index for empty
// strings is 0.
- if (newString.length() == 0)
+ if (new_string.length() == 0)
return 0;
- strings.push_back(newString);
+ strings.push_back(new_string);
return strings.size();
}
}
void
-X86ISA::SMBios::SMBiosStructure::setString(int n, std::string & newString)
+X86ISA::SMBios::SMBiosStructure::setString(
+ int n, const std::string &new_string)
{
assert(n > 0 && n <= strings.size());
- strings[n - 1] = newString;
+ strings[n - 1] = new_string;
}
-X86ISA::SMBios::BiosInformation::BiosInformation(Params * p) :
+X86ISA::SMBios::BiosInformation::BiosInformation(const Params &p) :
SMBiosStructure(p, Type),
- startingAddrSegment(p->starting_addr_segment),
- romSize(p->rom_size),
- majorVer(p->major), minorVer(p->minor),
- embContFirmwareMajor(p->emb_cont_firmware_major),
- embContFirmwareMinor(p->emb_cont_firmware_minor)
+ startingAddrSegment(p.starting_addr_segment),
+ romSize(p.rom_size),
+ majorVer(p.major), minorVer(p.minor),
+ embContFirmwareMajor(p.emb_cont_firmware_major),
+ embContFirmwareMinor(p.emb_cont_firmware_minor)
{
- vendor = addString(p->vendor);
- version = addString(p->version);
- releaseDate = addString(p->release_date);
+ vendor = addString(p.vendor);
+ version = addString(p.version);
+ releaseDate = addString(p.release_date);
- characteristics = composeBitVector(p->characteristics);
+ characteristics = composeBitVector(p.characteristics);
characteristicExtBytes =
- composeBitVector(p->characteristic_ext_bytes);
+ composeBitVector(p.characteristic_ext_bytes);
}
uint16_t
return size;
}
-X86ISA::SMBios::SMBiosTable::SMBiosTable(Params * p) :
- SimObject(p), structures(p->structures)
+X86ISA::SMBios::SMBiosTable::SMBiosTable(const Params &p) :
+ SimObject(p), structures(p.structures)
{
- smbiosHeader.majorVersion = p->major_version;
- smbiosHeader.minorVersion = p->minor_version;
- assert(p->major_version <= 9);
- assert(p->minor_version <= 9);
+ smbiosHeader.majorVersion = p.major_version;
+ smbiosHeader.minorVersion = p.minor_version;
+ assert(p.major_version <= 9);
+ assert(p.minor_version <= 9);
smbiosHeader.intermediateHeader.smbiosBCDRevision =
- (p->major_version << 4) | p->minor_version;
+ (p.major_version << 4) | p.minor_version;
}
void
}
X86ISA::SMBios::BiosInformation *
-X86SMBiosBiosInformationParams::create()
+X86SMBiosBiosInformationParams::create() const
{
- return new X86ISA::SMBios::BiosInformation(this);
+ return new X86ISA::SMBios::BiosInformation(*this);
}
X86ISA::SMBios::SMBiosTable *
-X86SMBiosSMBiosTableParams::create()
+X86SMBiosSMBiosTableParams::create() const
{
- return new X86ISA::SMBios::SMBiosTable(this);
+ return new X86ISA::SMBios::SMBiosTable(*this);
}
protected:
bool stringFields;
- SMBiosStructure(Params * p, uint8_t _type);
+ SMBiosStructure(const Params &p, uint8_t _type);
std::vector<std::string> strings;
public:
- int addString(std::string & newString);
+ int addString(const std::string &new_string);
std::string readString(int n);
- void setString(int n, std::string & newString);
+ void setString(int n, const std::string &new_string);
};
class BiosInformation : public SMBiosStructure
// Offset 17h, 1 byte
uint8_t embContFirmwareMinor;
- BiosInformation(Params * p);
+ BiosInformation(const Params &p);
uint8_t getLength() { return 0x18; }
uint16_t writeOut(PortProxy& proxy, Addr addr);
std::vector<SMBiosStructure *> structures;
public:
- SMBiosTable(Params * p);
+ SMBiosTable(const Params &p);
Addr getTableAddr()
{
namespace X86ISA
{
-FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p),
- smbiosTable(p->smbios_table),
- mpFloatingPointer(p->intel_mp_pointer),
- mpConfigTable(p->intel_mp_table),
- rsdp(p->acpi_description_table_pointer)
+FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p),
+ smbiosTable(p.smbios_table),
+ mpFloatingPointer(p.intel_mp_pointer),
+ mpConfigTable(p.intel_mp_table),
+ rsdp(p.acpi_description_table_pointer)
{}
void
} // namespace X86ISA
X86ISA::FsWorkload *
-X86FsWorkloadParams::create()
+X86FsWorkloadParams::create() const
{
- return new X86ISA::FsWorkload(this);
+ return new X86ISA::FsWorkload(*this);
}
{
public:
typedef X86FsWorkloadParams Params;
- FsWorkload(Params *p);
+ FsWorkload(const Params &p);
public:
void initState() override;
void writeOutMPTable(Addr fp,
Addr &fpSize, Addr &tableSize, Addr table=0);
- const Params *params() const { return (const Params *)&_params; }
+ const Params ¶ms() const { return (const Params &)_params; }
};
} // namespace X86ISA
}
-X86ISA::Interrupts::Interrupts(Params *p)
- : BaseInterrupts(p), sys(p->system), clockDomain(*p->clk_domain),
+X86ISA::Interrupts::Interrupts(const Params &p)
+ : BaseInterrupts(p), sys(p.system), clockDomain(*p.clk_domain),
apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0),
intResponsePort(name() + ".int_responder", this, this),
- intRequestPort(name() + ".int_requestor", this, this, p->int_latency),
- pioPort(this), pioDelay(p->pio_latency)
+ intRequestPort(name() + ".int_requestor", this, this, p.int_latency),
+ pioPort(this), pioDelay(p.pio_latency)
{
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
}
X86ISA::Interrupts *
-X86LocalApicParams::create()
+X86LocalApicParams::create() const
{
- return new X86ISA::Interrupts(this);
+ return new X86ISA::Interrupts(*this);
}
void
-X86ISA::Interrupts::processApicTimerEvent() {
+X86ISA::Interrupts::processApicTimerEvent()
+{
if (triggerTimerInterrupt())
setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
}
void setThreadContext(ThreadContext *_tc) override;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/*
* Constructor.
*/
- Interrupts(Params * p);
+ Interrupts(const Params &p);
/*
* Functions for retrieving interrupts for the CPU to handle.
regVal[MISCREG_APIC_BASE] = lApicBase;
}
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
{
clear();
}
-const X86ISAParams *
+const X86ISAParams &
ISA::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
RegVal
}
X86ISA::ISA *
-X86ISAParams::create()
+X86ISAParams::create() const
{
- return new X86ISA::ISA(this);
+ return new X86ISA::ISA(*this);
}
typedef X86ISAParams Params;
- ISA(Params *p);
- const Params *params() const;
+ ISA(const Params &p);
+ const Params ¶ms() const;
RegVal readMiscRegNoEffect(int miscReg) const;
RegVal readMiscReg(int miscReg);
namespace X86ISA
{
-FsLinux::FsLinux(Params *p) : X86ISA::FsWorkload(p), e820Table(p->e820_table)
+FsLinux::FsLinux(const Params &p) :
+ X86ISA::FsWorkload(p), e820Table(p.e820_table)
{}
void
} // namespace X86ISA
X86ISA::FsLinux *
-X86FsLinuxParams::create()
+X86FsLinuxParams::create() const
{
- return new X86ISA::FsLinux(this);
+ return new X86ISA::FsLinux(*this);
}
public:
typedef X86FsLinuxParams Params;
- FsLinux(Params *p);
+ FsLinux(const Params &p);
void initState() override;
};
{
public:
Process *
- load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+ load(const ProcessParams ¶ms, ::Loader::ObjectFile *obj_file) override
{
auto arch = obj_file->getArch();
auto opsys = obj_file->getOpSys();
#include "arch/x86/mmu.hh"
X86ISA::MMU *
-X86MMUParams::create()
+X86MMUParams::create() const
{
- return new X86ISA::MMU(this);
+ return new X86ISA::MMU(*this);
}
class MMU : public BaseMMU
{
public:
- MMU(const X86MMUParams *p)
+ MMU(const X86MMUParams &p)
: BaseMMU(p)
{}
};
}
-X86NativeTrace::X86NativeTrace(const Params *p)
- : NativeTrace(p)
+X86NativeTrace::X86NativeTrace(const Params &p) : NativeTrace(p)
{
checkRcx = true;
checkR11 = true;
// ExeTracer Simulation Object
//
Trace::X86NativeTrace *
-X86NativeTraceParams::create()
+X86NativeTraceParams::create() const
{
- return new Trace::X86NativeTrace(this);
+ return new Trace::X86NativeTrace(*this);
}
bool checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
public:
- X86NativeTrace(const Params *p);
+ X86NativeTrace(const Params &p);
void check(NativeTraceRecord *record);
};
/* end namespace X86ISA */ }
X86ISA::Walker *
-X86PagetableWalkerParams::create()
+X86PagetableWalkerParams::create() const
{
- return new X86ISA::Walker(this);
+ return new X86ISA::Walker(*this);
}
typedef X86PagetableWalkerParams Params;
- const Params *
+ const Params &
params() const
{
- return static_cast<const Params *>(_params);
+ return static_cast<const Params &>(_params);
}
- Walker(const Params *params) :
+ Walker(const Params ¶ms) :
ClockedObject(params), port(name() + ".port", this),
- funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
+ funcState(this, NULL, NULL, true), tlb(NULL), sys(params.system),
requestorId(sys->getRequestorId(this)),
- numSquashable(params->num_squash_per_cycle),
+ numSquashable(params.num_squash_per_cycle),
startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
{
}
LongModePTE<29, 21>,
LongModePTE<20, 12> > ArchPageTable;
-X86Process::X86Process(ProcessParams *params, ::Loader::ObjectFile *objFile) :
- Process(params, params->useArchPT ?
+X86Process::X86Process(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile) :
+ Process(params, params.useArchPT ?
static_cast<EmulationPageTable *>(
- new ArchPageTable(params->name, params->pid,
- params->system, PageBytes)) :
- new EmulationPageTable(params->name, params->pid,
+ new ArchPageTable(params.name, params.pid,
+ params.system, PageBytes)) :
+ new EmulationPageTable(params.name, params.pid,
PageBytes),
objFile)
{
*process = *this;
}
-X86_64Process::X86_64Process(ProcessParams *params,
+X86_64Process::X86_64Process(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
X86Process(params, objFile)
{
}
-I386Process::I386Process(ProcessParams *params,
+I386Process::I386Process(const ProcessParams ¶ms,
::Loader::ObjectFile *objFile) :
X86Process(params, objFile)
{
Addr _gdtStart;
Addr _gdtSize;
- X86Process(ProcessParams *params, ::Loader::ObjectFile *objFile);
+ X86Process(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile);
template<class IntType>
void argsInit(int pageSize,
VSyscallPage vsyscallPage;
public:
- X86_64Process(ProcessParams *params, ::Loader::ObjectFile *objFile);
+ X86_64Process(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
void argsInit(int pageSize);
void initState() override;
VSyscallPage vsyscallPage;
public:
- I386Process(ProcessParams *params, ::Loader::ObjectFile *objFile);
+ I386Process(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *objFile);
void argsInit(int pageSize);
void initState() override;
namespace X86ISA {
-TLB::TLB(const Params *p)
- : BaseTLB(p), configAddress(0), size(p->size),
- tlb(size), lruSeq(0), m5opRange(p->system->m5opRange()), stats(this)
+TLB::TLB(const Params &p)
+ : BaseTLB(p), configAddress(0), size(p.size),
+ tlb(size), lruSeq(0), m5opRange(p.system->m5opRange()), stats(this)
{
if (!size)
fatal("TLBs must have a non-zero size.\n");
freeList.push_back(&tlb[x]);
}
- walker = p->walker;
+ walker = p.walker;
walker->setTLB(this);
}
} // namespace X86ISA
X86ISA::TLB *
-X86TLBParams::create()
+X86TLBParams::create() const
{
- return new X86ISA::TLB(this);
+ return new X86ISA::TLB(*this);
}
public:
typedef X86TLBParams Params;
- TLB(const Params *p);
+ TLB(const Params &p);
void takeOverFrom(BaseTLB *otlb) override {}
/**
* Create and clear the filter.
*/
- Base(const BloomFilterBaseParams* p)
- : SimObject(p), offsetBits(p->offset_bits),
- filter(p->size, SatCounter(p->num_bits)),
- sizeBits(floorLog2(p->size)), setThreshold(p->threshold)
+ Base(const BloomFilterBaseParams &p)
+ : SimObject(p), offsetBits(p.offset_bits),
+ filter(p.size, SatCounter(p.num_bits)),
+ sizeBits(floorLog2(p.size)), setThreshold(p.threshold)
{
clear();
}
namespace BloomFilter {
-Block::Block(const BloomFilterBlockParams* p)
- : Base(p), masksLSBs(p->masks_lsbs),
- masksSizes(p->masks_sizes)
+Block::Block(const BloomFilterBlockParams &p)
+ : Base(p), masksLSBs(p.masks_lsbs),
+ masksSizes(p.masks_sizes)
{
fatal_if(masksLSBs.size() != masksSizes.size(),
"Masks haven't been properly provided");
} // namespace BloomFilter
BloomFilter::Block*
-BloomFilterBlockParams::create()
+BloomFilterBlockParams::create() const
{
- return new BloomFilter::Block(this);
+ return new BloomFilter::Block(*this);
}
class Block : public Base
{
public:
- Block(const BloomFilterBlockParams* p);
+ Block(const BloomFilterBlockParams &p);
~Block();
void set(Addr addr) override;
namespace BloomFilter {
-Bulk::Bulk(const BloomFilterBulkParams* p)
+Bulk::Bulk(const BloomFilterBulkParams &p)
: MultiBitSel(p), sectorBits(floorLog2(parFilterSize))
{
fatal_if((numHashes * sectorBits) >
} // namespace BloomFilter
BloomFilter::Bulk*
-BloomFilterBulkParams::create()
+BloomFilterBulkParams::create() const
{
- return new BloomFilter::Bulk(this);
+ return new BloomFilter::Bulk(*this);
}
class Bulk : public MultiBitSel
{
public:
- Bulk(const BloomFilterBulkParams* p);
+ Bulk(const BloomFilterBulkParams &p);
~Bulk();
protected:
394261773, 848616745, 15446017, 517723271, },
};
-H3::H3(const BloomFilterH3Params* p)
+H3::H3(const BloomFilterH3Params &p)
: MultiBitSel(p)
{
fatal_if(numHashes > 16, "There are only 16 H3 functions implemented.");
} // namespace BloomFilter
BloomFilter::H3*
-BloomFilterH3Params::create()
+BloomFilterH3Params::create() const
{
- return new BloomFilter::H3(this);
+ return new BloomFilter::H3(*this);
}
class H3 : public MultiBitSel
{
public:
- H3(const BloomFilterH3Params* p);
+ H3(const BloomFilterH3Params &p);
~H3();
protected:
namespace BloomFilter {
-MultiBitSel::MultiBitSel(const BloomFilterMultiBitSelParams* p)
- : Base(p), numHashes(p->num_hashes),
- parFilterSize(p->size / numHashes),
- isParallel(p->is_parallel), skipBits(p->skip_bits)
+MultiBitSel::MultiBitSel(const BloomFilterMultiBitSelParams &p)
+ : Base(p), numHashes(p.num_hashes),
+ parFilterSize(p.size / numHashes),
+ isParallel(p.is_parallel), skipBits(p.skip_bits)
{
- if (p->size % numHashes) {
- fatal("Can't divide filter (%d) in %d equal portions", p->size,
+ if (p.size % numHashes) {
+ fatal("Can't divide filter (%d) in %d equal portions", p.size,
numHashes);
}
}
} // namespace BloomFilter
BloomFilter::MultiBitSel*
-BloomFilterMultiBitSelParams::create()
+BloomFilterMultiBitSelParams::create() const
{
- return new BloomFilter::MultiBitSel(this);
+ return new BloomFilter::MultiBitSel(*this);
}
class MultiBitSel : public Base
{
public:
- MultiBitSel(const BloomFilterMultiBitSelParams* p);
+ MultiBitSel(const BloomFilterMultiBitSelParams &p);
~MultiBitSel();
void set(Addr addr) override;
namespace BloomFilter {
-Multi::Multi(const BloomFilterMultiParams* p)
- : Base(p), filters(p->filters)
+Multi::Multi(const BloomFilterMultiParams &p)
+ : Base(p), filters(p.filters)
{
}
} // namespace BloomFilter
BloomFilter::Multi*
-BloomFilterMultiParams::create()
+BloomFilterMultiParams::create() const
{
- return new BloomFilter::Multi(this);
+ return new BloomFilter::Multi(*this);
}
class Multi : public Base
{
public:
- Multi(const BloomFilterMultiParams* p);
+ Multi(const BloomFilterMultiParams &p);
~Multi();
void clear() override;
namespace BloomFilter {
-Perfect::Perfect(const BloomFilterPerfectParams* p)
+Perfect::Perfect(const BloomFilterPerfectParams &p)
: Base(p)
{
}
} // namespace BloomFilter
BloomFilter::Perfect*
-BloomFilterPerfectParams::create()
+BloomFilterPerfectParams::create() const
{
- return new BloomFilter::Perfect(this);
+ return new BloomFilter::Perfect(*this);
}
class Perfect : public Base
{
public:
- Perfect(const BloomFilterPerfectParams* p);
+ Perfect(const BloomFilterPerfectParams &p);
~Perfect();
void clear() override;
using namespace std;
-VncInput::VncInput(const Params *p)
+VncInput::VncInput(const Params &p)
: SimObject(p), keyboard(NULL), mouse(NULL),
fb(&FrameBuffer::dummy),
_videoWidth(fb->width()), _videoHeight(fb->height()),
- captureEnabled(p->frame_capture),
+ captureEnabled(p.frame_capture),
captureCurrentFrame(0), captureLastHash(0),
- imgFormat(p->img_format)
+ imgFormat(p.img_format)
{
if (captureEnabled) {
// remove existing frame output directory if it exists, then create a
// create the VNC Replayer object
VncInput *
-VncInputParams::create()
+VncInputParams::create() const
{
- return new VncInput(this);
+ return new VncInput(*this);
}
};
typedef VncInputParams Params;
- VncInput(const Params *p);
+ VncInput(const Params &p);
/** Set the address of the frame buffer we are going to show.
* To avoid copying, just have the display controller
/**
* VncServer
*/
-VncServer::VncServer(const Params *p)
- : VncInput(p), listenEvent(NULL), dataEvent(NULL), number(p->number),
+VncServer::VncServer(const Params &p)
+ : VncInput(p), listenEvent(NULL), dataEvent(NULL), number(p.number),
dataFd(-1), sendUpdate(false),
supportsRawEnc(false), supportsResizeEnc(false)
{
- if (p->port)
- listen(p->port);
+ if (p.port)
+ listen(p.port);
curState = WaitForProtocolVersion;
pixelFormat.greenshift = pixelConverter.ch_g.offset;
pixelFormat.blueshift = pixelConverter.ch_b.offset;
- DPRINTF(VNC, "Vnc server created at port %d\n", p->port);
+ DPRINTF(VNC, "Vnc server created at port %d\n", p.port);
}
VncServer::~VncServer()
// create the VNC server object
VncServer *
-VncServerParams::create()
+VncServerParams::create() const
{
- return new VncServer(this);
+ return new VncServer(*this);
}
public:
typedef VncServerParams Params;
- VncServer(const Params *p);
+ VncServer(const Params &p);
~VncServer();
// RFB
return "CPU Progress";
}
-BaseCPU::BaseCPU(Params *p, bool is_checker)
- : ClockedObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
- _instRequestorId(p->system->getRequestorId(this, "inst")),
- _dataRequestorId(p->system->getRequestorId(this, "data")),
+BaseCPU::BaseCPU(const Params &p, bool is_checker)
+ : ClockedObject(p), instCnt(0), _cpuId(p.cpu_id), _socketId(p.socket_id),
+ _instRequestorId(p.system->getRequestorId(this, "inst")),
+ _dataRequestorId(p.system->getRequestorId(this, "data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
- _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
- interrupts(p->interrupts), numThreads(p->numThreads), system(p->system),
+ _switchedOut(p.switched_out), _cacheLineSize(p.system->cacheLineSize()),
+ interrupts(p.interrupts), numThreads(p.numThreads), system(p.system),
previousCycle(0), previousState(CPU_STATE_SLEEP),
functionTraceStream(nullptr), currentFunctionStart(0),
currentFunctionEnd(0), functionEntryTick(0),
- addressMonitor(p->numThreads),
- syscallRetryLatency(p->syscallRetryLatency),
- pwrGatingLatency(p->pwr_gating_latency),
- powerGatingOnIdle(p->power_gating_on_idle),
+ addressMonitor(p.numThreads),
+ syscallRetryLatency(p.syscallRetryLatency),
+ pwrGatingLatency(p.pwr_gating_latency),
+ powerGatingOnIdle(p.power_gating_on_idle),
enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
{
// if Python did not provide a valid ID, do it here
maxThreadsPerCPU = numThreads;
functionTracingEnabled = false;
- if (p->function_trace) {
+ if (p.function_trace) {
const string fname = csprintf("ftrace.%s", name());
functionTraceStream = simout.findOrCreate(fname)->stream();
currentFunctionStart = currentFunctionEnd = 0;
- functionEntryTick = p->function_trace_start;
+ functionEntryTick = p.function_trace_start;
- if (p->function_trace_start == 0) {
+ if (p.function_trace_start == 0) {
functionTracingEnabled = true;
} else {
Event *event = new EventFunctionWrapper(
[this]{ enableFunctionTrace(); }, name(), true);
- schedule(event, p->function_trace_start);
+ schedule(event, p.function_trace_start);
}
}
- tracer = params()->tracer;
+ tracer = params().tracer;
- if (params()->isa.size() != numThreads) {
+ if (params().isa.size() != numThreads) {
fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
- "of threads (%i).\n", params()->isa.size(), numThreads);
+ "of threads (%i).\n", params().isa.size(), numThreads);
}
}
{
// Set up instruction-count-based termination events, if any. This needs
// to happen after threadContexts has been constructed.
- if (params()->max_insts_any_thread != 0) {
+ if (params().max_insts_any_thread != 0) {
const char *cause = "a thread reached the max instruction count";
for (ThreadID tid = 0; tid < numThreads; ++tid)
- scheduleInstStop(tid, params()->max_insts_any_thread, cause);
+ scheduleInstStop(tid, params().max_insts_any_thread, cause);
}
// Set up instruction-count-based termination events for SimPoints
// Typically, there are more than one action points.
// Simulation.py is responsible to take the necessary actions upon
// exitting the simulation loop.
- if (!params()->simpoint_start_insts.empty()) {
+ if (!params().simpoint_start_insts.empty()) {
const char *cause = "simpoint starting point found";
- for (size_t i = 0; i < params()->simpoint_start_insts.size(); ++i)
- scheduleInstStop(0, params()->simpoint_start_insts[i], cause);
+ for (size_t i = 0; i < params().simpoint_start_insts.size(); ++i)
+ scheduleInstStop(0, params().simpoint_start_insts[i], cause);
}
- if (params()->max_insts_all_threads != 0) {
+ if (params().max_insts_all_threads != 0) {
const char *cause = "all threads reached the max instruction count";
// allocate & initialize shared downcounter: each event will
for (ThreadID tid = 0; tid < numThreads; ++tid) {
Event *event = new CountedExitEvent(cause, *counter);
threadContexts[tid]->scheduleInstCountEvent(
- event, params()->max_insts_all_threads);
+ event, params().max_insts_all_threads);
}
}
- if (!params()->switched_out) {
+ if (!params().switched_out) {
registerThreadContexts();
verifyMemoryMode();
void
BaseCPU::startup()
{
- if (params()->progress_interval) {
- new CPUProgressEvent(this, params()->progress_interval);
+ if (params().progress_interval) {
+ new CPUProgressEvent(this, params().progress_interval);
}
if (_switchedOut)
bool
BaseCPU::waitForRemoteGDB() const
{
- return params()->wait_for_remote_gdb;
+ return params().wait_for_remote_gdb;
}
public:
typedef BaseCPUParams Params;
- const Params *params() const
- { return reinterpret_cast<const Params *>(_params); }
- BaseCPU(Params *params, bool is_checker = false);
+ const Params &
+ params() const
+ {
+ return reinterpret_cast<const Params &>(_params);
+ }
+ BaseCPU(const Params ¶ms, bool is_checker = false);
virtual ~BaseCPU();
void init() override;
requestorId = systemPtr->getRequestorId(this);
}
-CheckerCPU::CheckerCPU(Params *p)
+CheckerCPU::CheckerCPU(const Params &p)
: BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
tc(NULL), thread(NULL),
unverifiedReq(nullptr),
changedPC = willChangePC = false;
- exitOnError = p->exitOnError;
- warnOnlyOnLoadError = p->warnOnlyOnLoadError;
- itb = p->itb;
- dtb = p->dtb;
- workload = p->workload;
+ exitOnError = p.exitOnError;
+ warnOnlyOnLoadError = p.warnOnlyOnLoadError;
+ itb = p.itb;
+ dtb = p.dtb;
+ workload = p.workload;
updateOnError = true;
}
void
CheckerCPU::setSystem(System *system)
{
- const Params *p(dynamic_cast<const Params *>(_params));
+ const Params &p = dynamic_cast<const Params &>(_params);
systemPtr = system;
if (FullSystem) {
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, p->isa[0]);
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, p.isa[0]);
} else {
thread = new SimpleThread(this, 0, systemPtr,
workload.size() ? workload[0] : NULL,
- itb, dtb, p->isa[0]);
+ itb, dtb, p.isa[0]);
}
tc = thread->getTC();
void init() override;
typedef CheckerCPUParams Params;
- CheckerCPU(Params *p);
+ CheckerCPU(const Params &p);
virtual ~CheckerCPU();
void setSystem(System *system);
typedef typename Impl::DynInstPtr DynInstPtr;
public:
- Checker(Params *p)
+ Checker(const Params &p)
: CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
{ }
#include "params/DummyChecker.hh"
DummyChecker *
-DummyCheckerParams::create()
+DummyCheckerParams::create() const
{
// The checker should check all instructions executed by the main
// cpu and therefore any parameters for early exit don't make much
fatal_if(max_insts_any_thread || max_insts_all_threads ||
progress_interval, "Invalid checker parameters");
- return new DummyChecker(this);
+ return new DummyChecker(*this);
}
class DummyChecker : public CheckerCPU
{
public:
- DummyChecker(Params *p)
+ DummyChecker(const Params &p)
: CheckerCPU(p)
{ }
};
// ExeTracer Simulation Object
//
Trace::ExeTracer *
-ExeTracerParams::create()
+ExeTracerParams::create() const
{
- return new Trace::ExeTracer(this);
+ return new Trace::ExeTracer(*this);
}
{
public:
typedef ExeTracerParams Params;
- ExeTracer(const Params *params) : InstTracer(params)
+ ExeTracer(const Params ¶ms) : InstTracer(params)
{}
InstRecord *
// The operation-class description object
//
OpDesc *
-OpDescParams::create()
+OpDescParams::create() const
{
- return new OpDesc(this);
+ return new OpDesc(*this);
}
//
// The FuDesc object
//
FUDesc *
-FUDescParams::create()
+FUDescParams::create() const
{
- return new FUDesc(this);
+ return new FUDesc(*this);
}
Cycles opLat;
bool pipelined;
- OpDesc(const OpDescParams *p)
- : SimObject(p), opClass(p->opClass), opLat(p->opLat),
- pipelined(p->pipelined) {};
+ OpDesc(const OpDescParams &p)
+ : SimObject(p), opClass(p.opClass), opLat(p.opLat),
+ pipelined(p.pipelined) {};
};
class FUDesc : public SimObject
std::vector<OpDesc *> opDescList;
unsigned number;
- FUDesc(const FUDescParams *p)
- : SimObject(p), opDescList(p->opList), number(p->count) {};
+ FUDesc(const FUDescParams &p)
+ : SimObject(p), opDescList(p.opList), number(p.count) {};
};
typedef std::vector<OpDesc *>::const_iterator OPDDiterator;
tracer.traceMem(staticInst, getAddr(), getSize(), getFlags());
}
-InstPBTrace::InstPBTrace(const InstPBTraceParams *p)
+InstPBTrace::InstPBTrace(const InstPBTraceParams &p)
: InstTracer(p), buf(nullptr), bufSize(0), curMsg(nullptr)
{
// Create our output file
- createTraceFile(p->file_name);
+ createTraceFile(p.file_name);
}
void
Trace::InstPBTrace*
-InstPBTraceParams::create()
+InstPBTraceParams::create() const
{
- return new Trace::InstPBTrace(this);
+ return new Trace::InstPBTrace(*this);
}
class InstPBTrace : public InstTracer
{
public:
- InstPBTrace(const InstPBTraceParams *p);
+ InstPBTrace(const InstPBTraceParams &p);
virtual ~InstPBTrace();
InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
// ExeTracer Simulation Object
//
Trace::IntelTrace *
-IntelTraceParams::create()
+IntelTraceParams::create() const
{
- return new Trace::IntelTrace(this);
+ return new Trace::IntelTrace(*this);
}
{
public:
- IntelTrace(const IntelTraceParams *p) : InstTracer(p)
+ IntelTrace(const IntelTraceParams &p) : InstTracer(p)
{}
IntelTraceRecord *
using namespace std;
-IntrControl::IntrControl(const Params *p)
- : SimObject(p), sys(p->sys)
+IntrControl::IntrControl(const Params &p)
+ : SimObject(p), sys(p.sys)
{}
void
}
IntrControl *
-IntrControlParams::create()
+IntrControlParams::create() const
{
- return new IntrControl(this);
+ return new IntrControl(*this);
}
public:
System *sys;
typedef IntrControlParams Params;
- IntrControl(const Params *p);
+ IntrControl(const Params &p);
void clear(int cpu_id, int int_num, int index);
void post(int cpu_id, int int_num, int index);
using namespace std;
-IntrControl::IntrControl(const Params *p)
- : SimObject(p), sys(p->sys)
+IntrControl::IntrControl(const Params &p)
+ : SimObject(p), sys(p.sys)
{}
void
}
IntrControl *
-IntrControlParams::create()
+IntrControlParams::create() const
{
- return new IntrControl(this);
+ return new IntrControl(*this);
}
/* Used by some KVM macros */
#define PAGE_SIZE pageSize
-BaseKvmCPU::BaseKvmCPU(BaseKvmCPUParams *params)
+BaseKvmCPU::BaseKvmCPU(const BaseKvmCPUParams ¶ms)
: BaseCPU(params),
- vm(*params->system->getKvmVM()),
+ vm(*params.system->getKvmVM()),
_status(Idle),
dataPort(name() + ".dcache_port", this),
instPort(name() + ".icache_port", this),
- alwaysSyncTC(params->alwaysSyncTC),
+ alwaysSyncTC(params.alwaysSyncTC),
threadContextDirty(true),
kvmStateDirty(false),
vcpuID(vm.allocVCPUID()), vcpuFD(-1), vcpuMMapSize(0),
tickEvent([this]{ tick(); }, "BaseKvmCPU tick",
false, Event::CPU_Tick_Pri),
activeInstPeriod(0),
- perfControlledByTimer(params->usePerfOverflow),
- hostFactor(params->hostFactor), stats(this),
+ perfControlledByTimer(params.usePerfOverflow),
+ hostFactor(params.hostFactor), stats(this),
ctrInsts(0)
{
if (pageSize == -1)
panic("KVM: Failed to determine host page size (%i)\n",
errno);
- if (FullSystem)
- thread = new SimpleThread(this, 0, params->system, params->itb, params->dtb,
- params->isa[0]);
- else
- thread = new SimpleThread(this, /* thread_num */ 0, params->system,
- params->workload[0], params->itb,
- params->dtb, params->isa[0]);
+ if (FullSystem) {
+ thread = new SimpleThread(this, 0, params.system, params.itb,
+ params.dtb, params.isa[0]);
+ } else {
+ thread = new SimpleThread(this, /* thread_num */ 0, params.system,
+ params.workload[0], params.itb,
+ params.dtb, params.isa[0]);
+ }
thread->setStatus(ThreadContext::Halted);
tc = thread->getTC();
void
BaseKvmCPU::startup()
{
- const BaseKvmCPUParams * const p(
- dynamic_cast<const BaseKvmCPUParams *>(params()));
+ const BaseKvmCPUParams &p =
+ dynamic_cast<const BaseKvmCPUParams &>(params());
Kvm &kvm(*vm.kvm);
// point. Initialize virtual CPUs here instead.
vcpuFD = vm.createVCPU(vcpuID);
- // Map the KVM run structure */
+ // Map the KVM run structure
vcpuMMapSize = kvm.getVCPUMMapSize();
_kvmRun = (struct kvm_run *)mmap(0, vcpuMMapSize,
PROT_READ | PROT_WRITE, MAP_SHARED,
// available. The offset into the KVM's communication page is
// provided by the coalesced MMIO capability.
int mmioOffset(kvm.capCoalescedMMIO());
- if (!p->useCoalescedMMIO) {
+ if (!p.useCoalescedMMIO) {
inform("KVM: Coalesced MMIO disabled by config.\n");
} else if (mmioOffset) {
inform("KVM: Coalesced IO available\n");
// delivery for counters and timers from within the thread that
// will execute the event queue to ensure that signals are
// delivered to the right threads.
- const BaseKvmCPUParams * const p(
- dynamic_cast<const BaseKvmCPUParams *>(params()));
+ const BaseKvmCPUParams &p =
+ dynamic_cast<const BaseKvmCPUParams &>(params());
vcpuThread = pthread_self();
setupCounters();
- if (p->usePerfOverflow)
+ if (p.usePerfOverflow) {
runTimer.reset(new PerfKvmTimer(hwCycles,
KVM_KICK_SIGNAL,
- p->hostFactor,
- p->hostFreq));
- else
+ p.hostFactor,
+ p.hostFreq));
+ } else {
runTimer.reset(new PosixKvmTimer(KVM_KICK_SIGNAL, CLOCK_MONOTONIC,
- p->hostFactor,
- p->hostFreq));
-
+ p.hostFactor,
+ p.hostFreq));
+ }
}
BaseKvmCPU::StatGroup::StatGroup(Stats::Group *parent)
class BaseKvmCPU : public BaseCPU
{
public:
- BaseKvmCPU(BaseKvmCPUParams *params);
+ BaseKvmCPU(const BaseKvmCPUParams ¶ms);
virtual ~BaseKvmCPU();
void init() override;
}
-KvmVM::KvmVM(KvmVMParams *params)
+KvmVM::KvmVM(const KvmVMParams ¶ms)
: SimObject(params),
kvm(new Kvm()), system(nullptr),
vmFD(kvm->createVM()),
if (!maxMemorySlot)
maxMemorySlot = 32;
/* Setup the coalesced MMIO regions */
- for (int i = 0; i < params->coalescedMMIO.size(); ++i)
- coalesceMMIO(params->coalescedMMIO[i]);
+ for (int i = 0; i < params.coalescedMMIO.size(); ++i)
+ coalesceMMIO(params.coalescedMMIO[i]);
}
KvmVM::~KvmVM()
KvmVM *
-KvmVMParams::create()
+KvmVMParams::create() const
{
static bool created = false;
if (created)
created = true;
- return new KvmVM(this);
+ return new KvmVM(*this);
}
friend class BaseKvmCPU;
public:
- KvmVM(KvmVMParams *params);
+ KvmVM(const KvmVMParams ¶ms);
virtual ~KvmVM();
void notifyFork();
// TODO: Check CS DB
}
-X86KvmCPU::X86KvmCPU(X86KvmCPUParams *params)
+X86KvmCPU::X86KvmCPU(const X86KvmCPUParams ¶ms)
: BaseKvmCPU(params),
- useXSave(params->useXSave)
+ useXSave(params.useXSave)
{
Kvm &kvm(*vm.kvm);
}
X86KvmCPU *
-X86KvmCPUParams::create()
+X86KvmCPUParams::create() const
{
- return new X86KvmCPU(this);
+ return new X86KvmCPU(*this);
}
class X86KvmCPU : public BaseKvmCPU
{
public:
- X86KvmCPU(X86KvmCPUParams *params);
+ X86KvmCPU(const X86KvmCPUParams ¶ms);
virtual ~X86KvmCPU();
void startup() override;
#include "debug/MinorCPU.hh"
#include "debug/Quiesce.hh"
-MinorCPU::MinorCPU(MinorCPUParams *params) :
+MinorCPU::MinorCPU(const MinorCPUParams ¶ms) :
BaseCPU(params),
- threadPolicy(params->threadPolicy)
+ threadPolicy(params.threadPolicy)
{
/* This is only written for one thread at the moment */
Minor::MinorThread *thread;
for (ThreadID i = 0; i < numThreads; i++) {
if (FullSystem) {
- thread = new Minor::MinorThread(this, i, params->system,
- params->itb, params->dtb, params->isa[i]);
+ thread = new Minor::MinorThread(this, i, params.system,
+ params.itb, params.dtb, params.isa[i]);
thread->setStatus(ThreadContext::Halted);
} else {
- thread = new Minor::MinorThread(this, i, params->system,
- params->workload[i], params->itb, params->dtb,
- params->isa[i]);
+ thread = new Minor::MinorThread(this, i, params.system,
+ params.workload[i], params.itb, params.dtb,
+ params.isa[i]);
}
threads.push_back(thread);
}
- if (params->checker) {
+ if (params.checker) {
fatal("The Minor model doesn't support checking (yet)\n");
}
Minor::MinorDynInst::init();
- pipeline = new Minor::Pipeline(*this, *params);
+ pipeline = new Minor::Pipeline(*this, params);
activityRecorder = pipeline->getActivityRecorder();
}
{
BaseCPU::init();
- if (!params()->switched_out &&
+ if (!params().switched_out &&
system->getMemoryMode() != Enums::timing)
{
fatal("The Minor CPU requires the memory system to be in "
}
MinorCPU *
-MinorCPUParams::create()
+MinorCPUParams::create() const
{
- return new MinorCPU(this);
+ return new MinorCPU(*this);
}
Port &
Port &getInstPort() override;
public:
- MinorCPU(MinorCPUParams *params);
+ MinorCPU(const MinorCPUParams ¶ms);
~MinorCPU();
Decode::Decode(const std::string &name,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardInstData>::Output inp_,
Latch<ForwardInstData>::Input out_,
std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer) :
public:
Decode(const std::string &name,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardInstData>::Output inp_,
Latch<ForwardInstData>::Input out_,
std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
Execute::Execute(const std::string &name_,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardInstData>::Output inp_,
Latch<BranchData>::Input out_) :
Named(name_),
public:
Execute(const std::string &name_,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardInstData>::Output inp_,
Latch<BranchData>::Input out_);
Fetch1::Fetch1(const std::string &name_,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<BranchData>::Output inp_,
Latch<ForwardLineData>::Input out_,
Latch<BranchData>::Output prediction_,
public:
Fetch1(const std::string &name_,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<BranchData>::Output inp_,
Latch<ForwardLineData>::Input out_,
Latch<BranchData>::Output prediction_,
Fetch2::Fetch2(const std::string &name,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardLineData>::Output inp_,
Latch<BranchData>::Output branchInp_,
Latch<BranchData>::Input predictionOut_,
public:
Fetch2(const std::string &name,
MinorCPU &cpu_,
- MinorCPUParams ¶ms,
+ const MinorCPUParams ¶ms,
Latch<ForwardLineData>::Output inp_,
Latch<BranchData>::Output branchInp_,
Latch<BranchData>::Input predictionOut_,
#include "enums/OpClass.hh"
MinorOpClass *
-MinorOpClassParams::create()
+MinorOpClassParams::create() const
{
- return new MinorOpClass(this);
+ return new MinorOpClass(*this);
}
MinorOpClassSet *
-MinorOpClassSetParams::create()
+MinorOpClassSetParams::create() const
{
- return new MinorOpClassSet(this);
+ return new MinorOpClassSet(*this);
}
MinorFUTiming *
-MinorFUTimingParams::create()
+MinorFUTimingParams::create() const
{
- return new MinorFUTiming(this);
+ return new MinorFUTiming(*this);
}
MinorFU *
-MinorFUParams::create()
+MinorFUParams::create() const
{
- return new MinorFU(this);
+ return new MinorFU(*this);
}
MinorFUPool *
-MinorFUPoolParams::create()
+MinorFUPoolParams::create() const
{
- return new MinorFUPool(this);
+ return new MinorFUPool(*this);
}
-MinorOpClassSet::MinorOpClassSet(const MinorOpClassSetParams *params) :
+MinorOpClassSet::MinorOpClassSet(const MinorOpClassSetParams ¶ms) :
SimObject(params),
- opClasses(params->opClasses),
+ opClasses(params.opClasses),
/* Initialise to true for an empty list so that 'fully capable' is
* the default */
capabilityList(Num_OpClasses, (opClasses.empty() ? true : false))
}
MinorFUTiming::MinorFUTiming(
- const MinorFUTimingParams *params) :
+ const MinorFUTimingParams ¶ms) :
SimObject(params),
- mask(params->mask),
- match(params->match),
- description(params->description),
- suppress(params->suppress),
- extraCommitLat(params->extraCommitLat),
- extraCommitLatExpr(params->extraCommitLatExpr),
- extraAssumedLat(params->extraAssumedLat),
- srcRegsRelativeLats(params->srcRegsRelativeLats),
- opClasses(params->opClasses)
+ mask(params.mask),
+ match(params.match),
+ description(params.description),
+ suppress(params.suppress),
+ extraCommitLat(params.extraCommitLat),
+ extraCommitLatExpr(params.extraCommitLatExpr),
+ extraAssumedLat(params.extraAssumedLat),
+ srcRegsRelativeLats(params.srcRegsRelativeLats),
+ opClasses(params.opClasses)
{ }
namespace Minor
OpClass opClass;
public:
- MinorOpClass(const MinorOpClassParams *params) :
+ MinorOpClass(const MinorOpClassParams ¶ms) :
SimObject(params),
- opClass(params->opClass)
+ opClass(params.opClass)
{ }
};
std::vector<bool> capabilityList;
public:
- MinorOpClassSet(const MinorOpClassSetParams *params);
+ MinorOpClassSet(const MinorOpClassSetParams ¶ms);
public:
/** Does this set support the given op class */
MinorOpClassSet *opClasses;
public:
- MinorFUTiming(const MinorFUTimingParams *params);
+ MinorFUTiming(const MinorFUTimingParams ¶ms);
public:
/** Does the extra decode in this object support the given op class */
std::vector<MinorFUTiming *> timings;
public:
- MinorFU(const MinorFUParams *params) :
+ MinorFU(const MinorFUParams ¶ms) :
SimObject(params),
- opClasses(params->opClasses),
- opLat(params->opLat),
- issueLat(params->issueLat),
- cantForwardFromFUIndices(params->cantForwardFromFUIndices),
- timings(params->timings)
+ opClasses(params.opClasses),
+ opLat(params.opLat),
+ issueLat(params.issueLat),
+ cantForwardFromFUIndices(params.cantForwardFromFUIndices),
+ timings(params.timings)
{ }
};
std::vector<MinorFU *> funcUnits;
public:
- MinorFUPool(const MinorFUPoolParams *params) :
+ MinorFUPool(const MinorFUPoolParams ¶ms) :
SimObject(params),
- funcUnits(params->funcUnits)
+ funcUnits(params.funcUnits)
{ }
};
namespace Minor
{
-Pipeline::Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms) :
+Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms) :
Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
cpu(cpu_),
allow_idling(params.enableIdling),
bool needToSignalDrained;
public:
- Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms);
+ Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms);
public:
/** Wake up the Fetch unit. This is needed on thread activation esp.
namespace Trace {
-NativeTrace::NativeTrace(const Params *p)
+NativeTrace::NativeTrace(const Params &p)
: ExeTracer(p)
{
if (ListenSocket::allDisabled())
public:
- NativeTrace(const Params *p);
+ NativeTrace(const Params &p);
virtual ~NativeTrace() {}
NativeTraceRecord *
class Checker<O3CPUImpl>;
O3Checker *
-O3CheckerParams::create()
+O3CheckerParams::create() const
{
// The checker should check all instructions executed by the main
// cpu and therefore any parameters for early exit don't make much
fatal_if(max_insts_any_thread || max_insts_all_threads ||
progress_interval, "Invalid checker parameters");
- return new O3Checker(this);
+ return new O3Checker(*this);
}
class O3Checker : public Checker<O3CPUImpl>
{
public:
- O3Checker(Params *p)
- : Checker<O3CPUImpl>(p)
- { }
+ O3Checker(const Params &p) : Checker<O3CPUImpl>(p) {}
};
#endif // __CPU_O3_CHECKER_HH__
public:
/** Construct a DefaultCommit with the given parameters. */
- DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
+ DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of the DefaultCommit. */
std::string name() const;
}
template <class Impl>
-DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
- : commitPolicy(params->smtCommitPolicy),
+DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+ : commitPolicy(params.smtCommitPolicy),
cpu(_cpu),
- iewToCommitDelay(params->iewToCommitDelay),
- commitToIEWDelay(params->commitToIEWDelay),
- renameToROBDelay(params->renameToROBDelay),
- fetchToCommitDelay(params->commitToFetchDelay),
- renameWidth(params->renameWidth),
- commitWidth(params->commitWidth),
- numThreads(params->numThreads),
+ iewToCommitDelay(params.iewToCommitDelay),
+ commitToIEWDelay(params.commitToIEWDelay),
+ renameToROBDelay(params.renameToROBDelay),
+ fetchToCommitDelay(params.commitToFetchDelay),
+ renameWidth(params.renameWidth),
+ commitWidth(params.commitWidth),
+ numThreads(params.numThreads),
drainPending(false),
drainImminent(false),
- trapLatency(params->trapLatency),
+ trapLatency(params.trapLatency),
canHandleInterrupts(true),
avoidQuiesceLiveLock(false),
stats(_cpu, this)
using namespace TheISA;
using namespace std;
-BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
+BaseO3CPU::BaseO3CPU(const BaseCPUParams ¶ms)
: BaseCPU(params)
{
}
}
template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
+FullO3CPU<Impl>::FullO3CPU(const DerivO3CPUParams ¶ms)
: BaseO3CPU(params),
- itb(params->itb),
- dtb(params->dtb),
+ itb(params.itb),
+ dtb(params.dtb),
tickEvent([this]{ tick(); }, "FullO3CPU tick",
false, Event::CPU_Tick_Pri),
threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads",
/* It is mandatory that all SMT threads use the same renaming mode as
* they are sharing registers and rename */
- vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
- regFile(params->numPhysIntRegs,
- params->numPhysFloatRegs,
- params->numPhysVecRegs,
- params->numPhysVecPredRegs,
- params->numPhysCCRegs,
+ vecMode(RenameMode<TheISA::ISA>::init(params.isa[0])),
+ regFile(params.numPhysIntRegs,
+ params.numPhysFloatRegs,
+ params.numPhysVecRegs,
+ params.numPhysVecPredRegs,
+ params.numPhysCCRegs,
vecMode),
freeList(name() + ".freelist", ®File),
isa(numThreads, NULL),
- timeBuffer(params->backComSize, params->forwardComSize),
- fetchQueue(params->backComSize, params->forwardComSize),
- decodeQueue(params->backComSize, params->forwardComSize),
- renameQueue(params->backComSize, params->forwardComSize),
- iewQueue(params->backComSize, params->forwardComSize),
+ timeBuffer(params.backComSize, params.forwardComSize),
+ fetchQueue(params.backComSize, params.forwardComSize),
+ decodeQueue(params.backComSize, params.forwardComSize),
+ renameQueue(params.backComSize, params.forwardComSize),
+ iewQueue(params.backComSize, params.forwardComSize),
activityRec(name(), NumStages,
- params->backComSize + params->forwardComSize,
- params->activity),
+ params.backComSize + params.forwardComSize,
+ params.activity),
globalSeqNum(1),
- system(params->system),
+ system(params.system),
lastRunningCycle(curCycle())
{
- fatal_if(FullSystem && params->numThreads > 1,
+ fatal_if(FullSystem && params.numThreads > 1,
"SMT is not supported in O3 in full system mode currently.");
- fatal_if(!FullSystem && params->numThreads < params->workload.size(),
+ fatal_if(!FullSystem && params.numThreads < params.workload.size(),
"More workload items (%d) than threads (%d) on CPU %s.",
- params->workload.size(), params->numThreads, name());
+ params.workload.size(), params.numThreads, name());
- if (!params->switched_out) {
+ if (!params.switched_out) {
_status = Running;
} else {
_status = SwitchedOut;
}
- if (params->checker) {
- BaseCPU *temp_checker = params->checker;
+ if (params.checker) {
+ BaseCPU *temp_checker = params.checker;
checker = dynamic_cast<Checker<Impl> *>(temp_checker);
checker->setIcachePort(&this->fetch.getInstPort());
- checker->setSystem(params->system);
+ checker->setSystem(params.system);
} else {
checker = NULL;
}
if (FullSystem) {
active_threads = 1;
} else {
- active_threads = params->workload.size();
+ active_threads = params.workload.size();
if (active_threads > Impl::MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads' "
}
//Make Sure That this a Valid Architeture
- assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
- assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
- assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
- assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
- assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
+ assert(params.numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
+ assert(params.numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
+ assert(params.numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
+ assert(params.numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
+ assert(params.numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
rename.setScoreboard(&scoreboard);
iew.setScoreboard(&scoreboard);
// Setup the rename map for whichever stages need it.
for (ThreadID tid = 0; tid < numThreads; tid++) {
- isa[tid] = dynamic_cast<TheISA::ISA *>(params->isa[tid]);
+ isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
assert(isa[tid]);
assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
assert(this->numThreads == 1);
this->thread[tid] = new Thread(this, 0, NULL);
} else {
- if (tid < params->workload.size()) {
+ if (tid < params.workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x",
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
- tid, params->workload[tid]);
+ tid, params.workload[tid]);
//usedTids[tid] = true;
//threadMap[tid] = tid;
// If we're using a checker, then the TC should be the
// CheckerThreadContext.
- if (params->checker) {
+ if (params.checker) {
tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
o3_tc, this->checker);
}
}
// FullO3CPU always requires an interrupt controller.
- if (!params->switched_out && interrupts.empty()) {
+ if (!params.switched_out && interrupts.empty()) {
fatal("FullO3CPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name());
}
{
//Stuff that's pretty ISA independent will go here.
public:
- BaseO3CPU(BaseCPUParams *params);
+ BaseO3CPU(const BaseCPUParams ¶ms);
void regStats();
};
public:
/** Constructs a CPU with the given parameters. */
- FullO3CPU(DerivO3CPUParams *params);
+ FullO3CPU(const DerivO3CPUParams ¶ms);
/** Destructor. */
~FullO3CPU();
public:
/** DefaultDecode constructor. */
- DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
+ DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
void startupStage();
using std::list;
template<class Impl>
-DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
+DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
: cpu(_cpu),
- renameToDecodeDelay(params->renameToDecodeDelay),
- iewToDecodeDelay(params->iewToDecodeDelay),
- commitToDecodeDelay(params->commitToDecodeDelay),
- fetchToDecodeDelay(params->fetchToDecodeDelay),
- decodeWidth(params->decodeWidth),
- numThreads(params->numThreads),
+ renameToDecodeDelay(params.renameToDecodeDelay),
+ iewToDecodeDelay(params.iewToDecodeDelay),
+ commitToDecodeDelay(params.commitToDecodeDelay),
+ fetchToDecodeDelay(params.fetchToDecodeDelay),
+ decodeWidth(params.decodeWidth),
+ numThreads(params.numThreads),
stats(_cpu)
{
if (decodeWidth > Impl::MaxWidth)
decodeWidth, static_cast<int>(Impl::MaxWidth));
// @todo: Make into a parameter
- skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
+ skidBufferMax = (fetchToDecodeDelay + 1) * params.fetchWidth;
for (int tid = 0; tid < Impl::MaxThreads; tid++) {
stalls[tid] = {false};
decodeStatus[tid] = Idle;
#include "params/DerivO3CPU.hh"
DerivO3CPU *
-DerivO3CPUParams::create()
+DerivO3CPUParams::create() const
{
- return new DerivO3CPU(this);
+ return new DerivO3CPU(*this);
}
class DerivO3CPU : public FullO3CPU<O3CPUImpl>
{
public:
- DerivO3CPU(DerivO3CPUParams *p)
- : FullO3CPU<O3CPUImpl>(p)
- { }
+ DerivO3CPU(const DerivO3CPUParams &p) : FullO3CPU<O3CPUImpl>(p) {}
};
#endif // __CPU_O3_DERIV_HH__
public:
/** DefaultFetch constructor. */
- DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
+ DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of fetch. */
std::string name() const;
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
-//#include "cpu/checker/cpu.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/exetrace.hh"
using namespace std;
template<class Impl>
-DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
- : fetchPolicy(params->smtFetchPolicy),
+DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+ : fetchPolicy(params.smtFetchPolicy),
cpu(_cpu),
branchPred(nullptr),
- decodeToFetchDelay(params->decodeToFetchDelay),
- renameToFetchDelay(params->renameToFetchDelay),
- iewToFetchDelay(params->iewToFetchDelay),
- commitToFetchDelay(params->commitToFetchDelay),
- fetchWidth(params->fetchWidth),
- decodeWidth(params->decodeWidth),
+ decodeToFetchDelay(params.decodeToFetchDelay),
+ renameToFetchDelay(params.renameToFetchDelay),
+ iewToFetchDelay(params.iewToFetchDelay),
+ commitToFetchDelay(params.commitToFetchDelay),
+ fetchWidth(params.fetchWidth),
+ decodeWidth(params.decodeWidth),
retryPkt(NULL),
retryTid(InvalidThreadID),
cacheBlkSize(cpu->cacheLineSize()),
- fetchBufferSize(params->fetchBufferSize),
+ fetchBufferSize(params.fetchBufferSize),
fetchBufferMask(fetchBufferSize - 1),
- fetchQueueSize(params->fetchQueueSize),
- numThreads(params->numThreads),
- numFetchingThreads(params->smtNumFetchingThreads),
+ fetchQueueSize(params.fetchQueueSize),
+ numThreads(params.numThreads),
+ numFetchingThreads(params.smtNumFetchingThreads),
icachePort(this, _cpu),
finishTranslationEvent(this), fetchStats(_cpu, this)
{
issuePipelinedIfetch[i] = false;
}
- branchPred = params->branchPred;
+ branchPred = params.branchPred;
for (ThreadID tid = 0; tid < numThreads; tid++) {
decoder[tid] = new TheISA::Decoder(
- dynamic_cast<TheISA::ISA *>(params->isa[tid]));
+ dynamic_cast<TheISA::ISA *>(params.isa[tid]));
// Create space to buffer the cache line data,
// which may not hold the entire cache line.
fetchBuffer[tid] = new uint8_t[fetchBufferSize];
// Constructor
-FUPool::FUPool(const Params *p)
+FUPool::FUPool(const Params &p)
: SimObject(p)
{
numFU = 0;
//
// Iterate through the list of FUDescData structures
//
- const vector<FUDesc *> ¶mList = p->FUList;
+ const vector<FUDesc *> ¶mList = p.FUList;
for (FUDDiterator i = paramList.begin(); i != paramList.end(); ++i) {
//
// The FuPool object
//
FUPool *
-FUPoolParams::create()
+FUPoolParams::create() const
{
- return new FUPool(this);
+ return new FUPool(*this);
}
public:
typedef FUPoolParams Params;
/** Constructs a FU pool. */
- FUPool(const Params *p);
+ FUPool(const Params &p);
~FUPool();
static constexpr auto NoCapableFU = -2;
public:
/** Constructs a DefaultIEW with the given parameters. */
- DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
+ DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of the DefaultIEW stage. */
std::string name() const;
using namespace std;
template<class Impl>
-DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
- : issueToExecQueue(params->backComSize, params->forwardComSize),
+DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+ : issueToExecQueue(params.backComSize, params.forwardComSize),
cpu(_cpu),
instQueue(_cpu, this, params),
ldstQueue(_cpu, this, params),
- fuPool(params->fuPool),
- commitToIEWDelay(params->commitToIEWDelay),
- renameToIEWDelay(params->renameToIEWDelay),
- issueToExecuteDelay(params->issueToExecuteDelay),
- dispatchWidth(params->dispatchWidth),
- issueWidth(params->issueWidth),
+ fuPool(params.fuPool),
+ commitToIEWDelay(params.commitToIEWDelay),
+ renameToIEWDelay(params.renameToIEWDelay),
+ issueToExecuteDelay(params.issueToExecuteDelay),
+ dispatchWidth(params.dispatchWidth),
+ issueWidth(params.issueWidth),
wbNumInst(0),
wbCycle(0),
- wbWidth(params->wbWidth),
- numThreads(params->numThreads)
+ wbWidth(params.wbWidth),
+ numThreads(params.numThreads)
{
if (dispatchWidth > Impl::MaxWidth)
fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
updateLSQNextCycle = false;
- skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
+ skidBufferMax = (renameToIEWDelay + 1) * params.renameWidth;
}
template <class Impl>
};
/** Constructs an IQ. */
- InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
+ InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
+ const DerivO3CPUParams ¶ms);
/** Destructs the IQ. */
~InstructionQueue();
template <class Impl>
InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
- DerivO3CPUParams *params)
+ const DerivO3CPUParams ¶ms)
: cpu(cpu_ptr),
iewStage(iew_ptr),
- fuPool(params->fuPool),
- iqPolicy(params->smtIQPolicy),
- numEntries(params->numIQEntries),
- totalWidth(params->issueWidth),
- commitToIEWDelay(params->commitToIEWDelay)
+ fuPool(params.fuPool),
+ iqPolicy(params.smtIQPolicy),
+ numEntries(params.numIQEntries),
+ totalWidth(params.issueWidth),
+ commitToIEWDelay(params.commitToIEWDelay)
{
assert(fuPool);
- numThreads = params->numThreads;
+ numThreads = params.numThreads;
// Set the number of total physical registers
// As the vector registers have two addressing modes, they are added twice
- numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
- params->numPhysVecRegs +
- params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
- params->numPhysVecPredRegs +
- params->numPhysCCRegs;
+ numPhysRegs = params.numPhysIntRegs + params.numPhysFloatRegs +
+ params.numPhysVecRegs +
+ params.numPhysVecRegs * TheISA::NumVecElemPerVecReg +
+ params.numPhysVecPredRegs +
+ params.numPhysCCRegs;
//Create an entry for each physical register within the
//dependency graph.
DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
"%i entries per thread.\n",part_amt);
} else if (iqPolicy == SMTQueuePolicy::Threshold) {
- double threshold = (double)params->smtIQThreshold / 100;
+ double threshold = (double)params.smtIQThreshold / 100;
int thresholdIQ = (int)((double)threshold * numEntries);
};
/** Constructs an LSQ with the given parameters. */
- LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
+ LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams ¶ms);
~LSQ() { }
/** Returns the name of the LSQ. */
using namespace std;
template <class Impl>
-LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
+LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams ¶ms)
: cpu(cpu_ptr), iewStage(iew_ptr),
_cacheBlocked(false),
- cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
- cacheLoadPorts(params->cacheLoadPorts), usedLoadPorts(0),
- lsqPolicy(params->smtLSQPolicy),
- LQEntries(params->LQEntries),
- SQEntries(params->SQEntries),
- maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
- params->smtLSQThreshold)),
- maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
- params->smtLSQThreshold)),
+ cacheStorePorts(params.cacheStorePorts), usedStorePorts(0),
+ cacheLoadPorts(params.cacheLoadPorts), usedLoadPorts(0),
+ lsqPolicy(params.smtLSQPolicy),
+ LQEntries(params.LQEntries),
+ SQEntries(params.SQEntries),
+ maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params.numThreads,
+ params.smtLSQThreshold)),
+ maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params.numThreads,
+ params.smtLSQThreshold)),
dcachePort(this, cpu_ptr),
- numThreads(params->numThreads)
+ numThreads(params.numThreads)
{
assert(numThreads > 0 && numThreads <= Impl::MaxThreads);
- //**********************************************/
- //************ Handle SMT Parameters ***********/
- //**********************************************/
+ //**********************************************
+ //************ Handle SMT Parameters ***********
+ //**********************************************
/* Run SMT olicy checks. */
if (lsqPolicy == SMTQueuePolicy::Dynamic) {
maxLQEntries,maxSQEntries);
} else if (lsqPolicy == SMTQueuePolicy::Threshold) {
- assert(params->smtLSQThreshold > params->LQEntries);
- assert(params->smtLSQThreshold > params->SQEntries);
+ assert(params.smtLSQThreshold > params.LQEntries);
+ assert(params.smtLSQThreshold > params.SQEntries);
DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
"%i entries per LQ | %i entries per SQ\n",
}
/** Initializes the LSQ unit with the specified number of entries. */
- void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
+ void init(O3CPU *cpu_ptr, IEW *iew_ptr, const DerivO3CPUParams ¶ms,
LSQ *lsq_ptr, unsigned id);
/** Returns the name of the LSQ unit. */
template<class Impl>
void
-LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
- LSQ *lsq_ptr, unsigned id)
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr,
+ const DerivO3CPUParams ¶ms, LSQ *lsq_ptr, unsigned id)
{
lsqID = id;
DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID);
- depCheckShift = params->LSQDepCheckShift;
- checkLoads = params->LSQCheckLoads;
- needsTSO = params->needsTSO;
+ depCheckShift = params.LSQDepCheckShift;
+ checkLoads = params.LSQCheckLoads;
+ needsTSO = params.needsTSO;
resetState();
}
MemDepUnit();
/** Constructs a MemDepUnit with given parameters. */
- MemDepUnit(DerivO3CPUParams *params);
+ MemDepUnit(const DerivO3CPUParams ¶ms);
/** Frees up any memory allocated. */
~MemDepUnit();
std::string name() const { return _name; }
/** Initializes the unit with parameters and a thread id. */
- void init(DerivO3CPUParams *params, ThreadID tid);
+ void init(const DerivO3CPUParams ¶ms, ThreadID tid);
/** Registers statistics. */
void regStats();
}
template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
- : _name(params->name + ".memdepunit"),
- depPred(params->store_set_clear_period, params->SSITSize,
- params->LFSTSize),
+MemDepUnit<MemDepPred, Impl>::MemDepUnit(const DerivO3CPUParams ¶ms)
+ : _name(params.name + ".memdepunit"),
+ depPred(params.store_set_clear_period, params.SSITSize,
+ params.LFSTSize),
iqPtr(NULL)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
+MemDepUnit<MemDepPred, Impl>::init(
+ const DerivO3CPUParams ¶ms, ThreadID tid)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
- _name = csprintf("%s.memDep%d", params->name, tid);
+ _name = csprintf("%s.memDep%d", params.name, tid);
id = tid;
- depPred.init(params->store_set_clear_period, params->SSITSize,
- params->LFSTSize);
+ depPred.init(params.store_set_clear_period, params.SSITSize,
+ params.LFSTSize);
}
template <class MemDepPred, class Impl>
#include "debug/ElasticTrace.hh"
#include "mem/packet.hh"
-ElasticTrace::ElasticTrace(const ElasticTraceParams* params)
+ElasticTrace::ElasticTrace(const ElasticTraceParams ¶ms)
: ProbeListenerObject(params),
regEtraceListenersEvent([this]{ regEtraceListeners(); }, name()),
firstWin(true),
lastClearedSeqNum(0),
- depWindowSize(params->depWindowSize),
+ depWindowSize(params.depWindowSize),
dataTraceStream(nullptr),
instTraceStream(nullptr),
- startTraceInst(params->startTraceInst),
+ startTraceInst(params.startTraceInst),
allProbesReg(false),
- traceVirtAddr(params->traceVirtAddr),
+ traceVirtAddr(params.traceVirtAddr),
stats(this)
{
- cpu = dynamic_cast<FullO3CPU<O3CPUImpl>*>(params->manager);
+ cpu = dynamic_cast<FullO3CPU<O3CPUImpl>*>(params.manager);
fatal_if(!cpu, "Manager of %s is not of type O3CPU and thus does not "\
"support dependency tracing.\n", name());
fatal_if(cpu->numThreads > 1, "numThreads = %i, %s supports tracing for"\
"single-threaded workload only", cpu->numThreads, name());
// Initialize the protobuf output stream
- fatal_if(params->instFetchTraceFile == "", "Assign instruction fetch "\
+ fatal_if(params.instFetchTraceFile == "", "Assign instruction fetch "\
"trace file path to instFetchTraceFile");
- fatal_if(params->dataDepTraceFile == "", "Assign data dependency "\
+ fatal_if(params.dataDepTraceFile == "", "Assign data dependency "\
"trace file path to dataDepTraceFile");
std::string filename = simout.resolve(name() + "." +
- params->instFetchTraceFile);
+ params.instFetchTraceFile);
instTraceStream = new ProtoOutputStream(filename);
- filename = simout.resolve(name() + "." + params->dataDepTraceFile);
+ filename = simout.resolve(name() + "." + params.dataDepTraceFile);
dataTraceStream = new ProtoOutputStream(filename);
// Create a protobuf message for the header and write it to the stream
ProtoMessage::PacketHeader inst_pkt_header;
}
ElasticTrace*
-ElasticTraceParams::create()
+ElasticTraceParams::create() const
{
- return new ElasticTrace(this);
+ return new ElasticTrace(*this);
}
typedef ProtoMessage::InstDepRecord Record;
/** Constructor */
- ElasticTrace(const ElasticTraceParams *params);
+ ElasticTrace(const ElasticTraceParams ¶ms);
/**
* Register the probe listeners that is the methods called on a probe point
}
SimpleTrace*
-SimpleTraceParams::create()
+SimpleTraceParams::create() const
{
- return new SimpleTrace(this);
+ return new SimpleTrace(*this);
}
class SimpleTrace : public ProbeListenerObject {
public:
- SimpleTrace(const SimpleTraceParams *params):
+ SimpleTrace(const SimpleTraceParams ¶ms):
ProbeListenerObject(params)
{
}
public:
/** DefaultRename constructor. */
- DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
+ DefaultRename(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
/** Returns the name of rename. */
std::string name() const;
using namespace std;
template <class Impl>
-DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
+DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
: cpu(_cpu),
- iewToRenameDelay(params->iewToRenameDelay),
- decodeToRenameDelay(params->decodeToRenameDelay),
- commitToRenameDelay(params->commitToRenameDelay),
- renameWidth(params->renameWidth),
- commitWidth(params->commitWidth),
- numThreads(params->numThreads),
+ iewToRenameDelay(params.iewToRenameDelay),
+ decodeToRenameDelay(params.decodeToRenameDelay),
+ commitToRenameDelay(params.commitToRenameDelay),
+ renameWidth(params.renameWidth),
+ commitWidth(params.commitWidth),
+ numThreads(params.numThreads),
stats(_cpu)
{
if (renameWidth > Impl::MaxWidth)
renameWidth, static_cast<int>(Impl::MaxWidth));
// @todo: Make into a parameter.
- skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
+ skidBufferMax = (decodeToRenameDelay + 1) * params.decodeWidth;
for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
renameStatus[tid] = Idle;
renameMap[tid] = nullptr;
* @param _cpu The cpu object pointer.
* @param params The cpu params including several ROB-specific parameters.
*/
- ROB(O3CPU *_cpu, DerivO3CPUParams *params);
+ ROB(O3CPU *_cpu, const DerivO3CPUParams ¶ms);
std::string name() const;
using namespace std;
template <class Impl>
-ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
- : robPolicy(params->smtROBPolicy),
+ROB<Impl>::ROB(O3CPU *_cpu, const DerivO3CPUParams ¶ms)
+ : robPolicy(params.smtROBPolicy),
cpu(_cpu),
- numEntries(params->numROBEntries),
- squashWidth(params->squashWidth),
+ numEntries(params.numROBEntries),
+ squashWidth(params.squashWidth),
numInstsInROB(0),
- numThreads(params->numThreads),
+ numThreads(params.numThreads),
stats(_cpu)
{
//Figure out rob policy
} else if (robPolicy == SMTQueuePolicy::Threshold) {
DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
- int threshold = params->smtROBThreshold;;
+ int threshold = params.smtROBThreshold;;
//Divide up by threshold amount
for (ThreadID tid = 0; tid < numThreads; tid++) {
#include "base/trace.hh"
#include "debug/Fetch.hh"
-LocalBP::LocalBP(const LocalBPParams *params)
+LocalBP::LocalBP(const LocalBPParams ¶ms)
: BPredUnit(params),
- localPredictorSize(params->localPredictorSize),
- localCtrBits(params->localCtrBits),
+ localPredictorSize(params.localPredictorSize),
+ localCtrBits(params.localCtrBits),
localPredictorSets(localPredictorSize / localCtrBits),
localCtrs(localPredictorSets, SatCounter(localCtrBits)),
indexMask(localPredictorSets - 1)
}
LocalBP*
-LocalBPParams::create()
+LocalBPParams::create() const
{
- return new LocalBP(this);
+ return new LocalBP(*this);
}
/**
* Default branch predictor constructor.
*/
- LocalBP(const LocalBPParams *params);
+ LocalBP(const LocalBPParams ¶ms);
virtual void uncondBranch(ThreadID tid, Addr pc, void * &bp_history);
#include "base/bitfield.hh"
#include "base/intmath.hh"
-BiModeBP::BiModeBP(const BiModeBPParams *params)
+BiModeBP::BiModeBP(const BiModeBPParams ¶ms)
: BPredUnit(params),
- globalHistoryReg(params->numThreads, 0),
- globalHistoryBits(ceilLog2(params->globalPredictorSize)),
- choicePredictorSize(params->choicePredictorSize),
- choiceCtrBits(params->choiceCtrBits),
- globalPredictorSize(params->globalPredictorSize),
- globalCtrBits(params->globalCtrBits),
+ globalHistoryReg(params.numThreads, 0),
+ globalHistoryBits(ceilLog2(params.globalPredictorSize)),
+ choicePredictorSize(params.choicePredictorSize),
+ choiceCtrBits(params.choiceCtrBits),
+ globalPredictorSize(params.globalPredictorSize),
+ globalCtrBits(params.globalCtrBits),
choiceCounters(choicePredictorSize, SatCounter(choiceCtrBits)),
takenCounters(globalPredictorSize, SatCounter(globalCtrBits)),
notTakenCounters(globalPredictorSize, SatCounter(globalCtrBits))
}
BiModeBP*
-BiModeBPParams::create()
+BiModeBPParams::create() const
{
- return new BiModeBP(this);
+ return new BiModeBP(*this);
}
class BiModeBP : public BPredUnit
{
public:
- BiModeBP(const BiModeBPParams *params);
+ BiModeBP(const BiModeBPParams ¶ms);
void uncondBranch(ThreadID tid, Addr pc, void * &bp_history);
void squash(ThreadID tid, void *bp_history);
bool lookup(ThreadID tid, Addr branch_addr, void * &bp_history);
#include "config/the_isa.hh"
#include "debug/Branch.hh"
-BPredUnit::BPredUnit(const Params *params)
+BPredUnit::BPredUnit(const Params ¶ms)
: SimObject(params),
- numThreads(params->numThreads),
+ numThreads(params.numThreads),
predHist(numThreads),
- BTB(params->BTBEntries,
- params->BTBTagSize,
- params->instShiftAmt,
- params->numThreads),
+ BTB(params.BTBEntries,
+ params.BTBTagSize,
+ params.instShiftAmt,
+ params.numThreads),
RAS(numThreads),
- iPred(params->indirectBranchPred),
+ iPred(params.indirectBranchPred),
stats(this),
- instShiftAmt(params->instShiftAmt)
+ instShiftAmt(params.instShiftAmt)
{
for (auto& r : RAS)
- r.init(params->RASSize);
+ r.init(params.RASSize);
}
BPredUnit::BPredUnitStats::BPredUnitStats(Stats::Group *parent)
/**
* @param params The params object, that has the size of the BP and BTB.
*/
- BPredUnit(const Params *p);
+ BPredUnit(const Params &p);
void regProbePoints() override;
typedef IndirectPredictorParams Params;
- IndirectPredictor(const Params *params)
+ IndirectPredictor(const Params ¶ms)
: SimObject(params)
{
}
#include "debug/LTage.hh"
#include "params/LoopPredictor.hh"
-LoopPredictor::LoopPredictor(LoopPredictorParams *p)
- : SimObject(p), logSizeLoopPred(p->logSizeLoopPred),
- loopTableAgeBits(p->loopTableAgeBits),
- loopTableConfidenceBits(p->loopTableConfidenceBits),
- loopTableTagBits(p->loopTableTagBits),
- loopTableIterBits(p->loopTableIterBits),
- logLoopTableAssoc(p->logLoopTableAssoc),
+LoopPredictor::LoopPredictor(const LoopPredictorParams &p)
+ : SimObject(p), logSizeLoopPred(p.logSizeLoopPred),
+ loopTableAgeBits(p.loopTableAgeBits),
+ loopTableConfidenceBits(p.loopTableConfidenceBits),
+ loopTableTagBits(p.loopTableTagBits),
+ loopTableIterBits(p.loopTableIterBits),
+ logLoopTableAssoc(p.logLoopTableAssoc),
confidenceThreshold((1 << loopTableConfidenceBits) - 1),
loopTagMask((1 << loopTableTagBits) - 1),
loopNumIterMask((1 << loopTableIterBits) - 1),
loopSetMask((1 << (logSizeLoopPred - logLoopTableAssoc)) - 1),
loopUseCounter(-1),
- withLoopBits(p->withLoopBits),
- useDirectionBit(p->useDirectionBit),
- useSpeculation(p->useSpeculation),
- useHashing(p->useHashing),
- restrictAllocation(p->restrictAllocation),
- initialLoopIter(p->initialLoopIter),
- initialLoopAge(p->initialLoopAge),
- optionalAgeReset(p->optionalAgeReset),
+ withLoopBits(p.withLoopBits),
+ useDirectionBit(p.useDirectionBit),
+ useSpeculation(p.useSpeculation),
+ useHashing(p.useHashing),
+ restrictAllocation(p.restrictAllocation),
+ initialLoopIter(p.initialLoopIter),
+ initialLoopAge(p.initialLoopAge),
+ optionalAgeReset(p.optionalAgeReset),
stats(this)
{
assert(initialLoopAge <= ((1 << loopTableAgeBits) - 1));
}
LoopPredictor *
-LoopPredictorParams::create()
+LoopPredictorParams::create() const
{
- return new LoopPredictor(this);
+ return new LoopPredictor(*this);
}
*/
void init() override;
- LoopPredictor(LoopPredictorParams *p);
+ LoopPredictor(const LoopPredictorParams &p);
size_t getSizeInBits() const;
};
#include "debug/Fetch.hh"
#include "debug/LTage.hh"
-LTAGE::LTAGE(const LTAGEParams *params)
- : TAGE(params), loopPredictor(params->loop_predictor)
+LTAGE::LTAGE(const LTAGEParams ¶ms)
+ : TAGE(params), loopPredictor(params.loop_predictor)
{
}
}
LTAGE*
-LTAGEParams::create()
+LTAGEParams::create() const
{
- return new LTAGE(this);
+ return new LTAGE(*this);
}
class LTAGE : public TAGE
{
public:
- LTAGE(const LTAGEParams *params);
+ LTAGE(const LTAGEParams ¶ms);
// Base class methods.
void squash(ThreadID tid, void *bp_history) override;
}
MultiperspectivePerceptron::MultiperspectivePerceptron(
- const MultiperspectivePerceptronParams *p) : BPredUnit(p),
- blockSize(p->block_size), pcshift(p->pcshift), threshold(p->threshold),
- bias0(p->bias0), bias1(p->bias1), biasmostly0(p->biasmostly0),
- biasmostly1(p->biasmostly1), nbest(p->nbest), tunebits(p->tunebits),
- hshift(p->hshift), imli_mask1(p->imli_mask1), imli_mask4(p->imli_mask4),
- recencypos_mask(p->recencypos_mask), fudge(p->fudge),
- n_sign_bits(p->n_sign_bits), pcbit(p->pcbit), decay(p->decay),
- record_mask(p->record_mask), hash_taken(p->hash_taken),
- tuneonly(p->tuneonly), extra_rounds(p->extra_rounds), speed(p->speed),
- budgetbits(p->budgetbits), speculative_update(p->speculative_update),
- threadData(p->numThreads, nullptr), doing_local(false),
- doing_recency(false), assoc(0), ghist_length(p->initial_ghist_length),
+ const MultiperspectivePerceptronParams &p) : BPredUnit(p),
+ blockSize(p.block_size), pcshift(p.pcshift), threshold(p.threshold),
+ bias0(p.bias0), bias1(p.bias1), biasmostly0(p.biasmostly0),
+ biasmostly1(p.biasmostly1), nbest(p.nbest), tunebits(p.tunebits),
+ hshift(p.hshift), imli_mask1(p.imli_mask1), imli_mask4(p.imli_mask4),
+ recencypos_mask(p.recencypos_mask), fudge(p.fudge),
+ n_sign_bits(p.n_sign_bits), pcbit(p.pcbit), decay(p.decay),
+ record_mask(p.record_mask), hash_taken(p.hash_taken),
+ tuneonly(p.tuneonly), extra_rounds(p.extra_rounds), speed(p.speed),
+ budgetbits(p.budgetbits), speculative_update(p.speculative_update),
+ threadData(p.numThreads, nullptr), doing_local(false),
+ doing_recency(false), assoc(0), ghist_length(p.initial_ghist_length),
modghist_length(1), path_length(1), thresholdCounter(0),
- theta(p->initial_theta), extrabits(0), imli_counter_bits(4),
+ theta(p.initial_theta), extrabits(0), imli_counter_bits(4),
modhist_indices(), modhist_lengths(), modpath_indices(), modpath_lengths()
{
fatal_if(speculative_update, "Speculative update not implemented");
for (auto &spec : specs) {
spec->setBitRequirements();
}
- const MultiperspectivePerceptronParams *p =
- static_cast<const MultiperspectivePerceptronParams *>(params());
+ const MultiperspectivePerceptronParams &p =
+ static_cast<const MultiperspectivePerceptronParams &>(params());
- computeBits(p->num_filter_entries, p->num_local_histories,
- p->local_history_length, p->ignore_path_size);
+ computeBits(p.num_filter_entries, p.num_local_histories,
+ p.local_history_length, p.ignore_path_size);
for (int i = 0; i < threadData.size(); i += 1) {
- threadData[i] = new ThreadData(p->num_filter_entries,
- p->num_local_histories,
- p->local_history_length, assoc,
+ threadData[i] = new ThreadData(p.num_filter_entries,
+ p.num_local_histories,
+ p.local_history_length, assoc,
blurrypath_bits, path_length,
ghist_length, blockSize, acyclic_bits,
modhist_indices, modhist_lengths,
};
public:
- MultiperspectivePerceptron(const MultiperspectivePerceptronParams *params);
+ MultiperspectivePerceptron(const MultiperspectivePerceptronParams ¶ms);
/**
* Sets the starting number of storage bits to compute the number of
#include "cpu/pred/multiperspective_perceptron_64KB.hh"
MultiperspectivePerceptron64KB::MultiperspectivePerceptron64KB(
- const MultiperspectivePerceptron64KBParams *p)
+ const MultiperspectivePerceptron64KBParams &p)
: MultiperspectivePerceptron(p)
{
}
addSpec(new SGHISTPATH(1, 5, 2, 1.3125, 972, 6, *this));
}
- MultiperspectivePerceptron64KB*
-MultiperspectivePerceptron64KBParams::create()
+MultiperspectivePerceptron64KB*
+MultiperspectivePerceptron64KBParams::create() const
{
- return new MultiperspectivePerceptron64KB(this);
+ return new MultiperspectivePerceptron64KB(*this);
}
void createSpecs() override;
public:
MultiperspectivePerceptron64KB(
- const MultiperspectivePerceptron64KBParams *p);
+ const MultiperspectivePerceptron64KBParams &p);
};
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_64KB_HH__
#include "cpu/pred/multiperspective_perceptron_8KB.hh"
MultiperspectivePerceptron8KB::MultiperspectivePerceptron8KB(
- const MultiperspectivePerceptron8KBParams *p)
+ const MultiperspectivePerceptron8KBParams &p)
: MultiperspectivePerceptron(p)
{
}
}
MultiperspectivePerceptron8KB*
-MultiperspectivePerceptron8KBParams::create()
+MultiperspectivePerceptron8KBParams::create() const
{
- return new MultiperspectivePerceptron8KB(this);
+ return new MultiperspectivePerceptron8KB(*this);
}
void createSpecs() override;
public:
MultiperspectivePerceptron8KB(
- const MultiperspectivePerceptron8KBParams *p);
+ const MultiperspectivePerceptron8KBParams &p);
};
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_8KB_HH__
}
MPP_TAGE*
-MPP_TAGEParams::create()
+MPP_TAGEParams::create() const
{
- return new MPP_TAGE(this);
+ return new MPP_TAGE(*this);
}
bool
}
MPP_LoopPredictor*
-MPP_LoopPredictorParams::create()
+MPP_LoopPredictorParams::create() const
{
- return new MPP_LoopPredictor(this);
+ return new MPP_LoopPredictor(*this);
}
MPP_StatisticalCorrector::MPP_StatisticalCorrector(
- const MPP_StatisticalCorrectorParams *p) : StatisticalCorrector(p),
- thirdH(0), pnb(p->pnb), logPnb(p->logPnb), pm(p->pm), gnb(p->gnb),
- logGnb(p->logGnb), gm(p->gm)
+ const MPP_StatisticalCorrectorParams &p) : StatisticalCorrector(p),
+ thirdH(0), pnb(p.pnb), logPnb(p.logPnb), pm(p.pm), gnb(p.gnb),
+ logGnb(p.logGnb), gm(p.gm)
{
initGEHLTable(pnb, pm, pgehl, logPnb, wp, -1);
initGEHLTable(gnb, gm, ggehl, logGnb, wg, -1);
}
MultiperspectivePerceptronTAGE::MultiperspectivePerceptronTAGE(
- const MultiperspectivePerceptronTAGEParams *p)
- : MultiperspectivePerceptron(p), tage(p->tage),
- loopPredictor(p->loop_predictor),
- statisticalCorrector(p->statistical_corrector)
+ const MultiperspectivePerceptronTAGEParams &p)
+ : MultiperspectivePerceptron(p), tage(p.tage),
+ loopPredictor(p.loop_predictor),
+ statisticalCorrector(p.statistical_corrector)
{
fatal_if(tage->isSpeculativeUpdateEnabled(),
"Speculative updates support is not implemented");
{}
};
- MPP_TAGE(const MPP_TAGEParams *p) : TAGEBase(p),
- tunedHistoryLengths(p->tunedHistoryLengths)
+ MPP_TAGE(const MPP_TAGEParams &p) : TAGEBase(p),
+ tunedHistoryLengths(p.tunedHistoryLengths)
{}
void calculateParameters() override;
class MPP_LoopPredictor : public LoopPredictor {
public:
- MPP_LoopPredictor(MPP_LoopPredictorParams *p) : LoopPredictor(p)
+ MPP_LoopPredictor(const MPP_LoopPredictorParams &p) : LoopPredictor(p)
{}
bool calcConf(int index) const override;
virtual ~BranchInfo()
{}
};
- MPP_StatisticalCorrector(const MPP_StatisticalCorrectorParams *p);
+ MPP_StatisticalCorrector(const MPP_StatisticalCorrectorParams &p);
void initBias() override;
unsigned getIndBias(Addr branch_pc, StatisticalCorrector::BranchInfo* bi,
public:
MultiperspectivePerceptronTAGE(
- const MultiperspectivePerceptronTAGEParams *p);
+ const MultiperspectivePerceptronTAGEParams &p);
void init() override;
#include "cpu/pred/multiperspective_perceptron_tage_64KB.hh"
MPP_StatisticalCorrector_64KB::MPP_StatisticalCorrector_64KB(
- const MPP_StatisticalCorrector_64KBParams *p)
+ const MPP_StatisticalCorrector_64KBParams &p)
: MPP_StatisticalCorrector(p),
- numEntriesSecondLocalHistories(p->numEntriesSecondLocalHistories),
- numEntriesThirdLocalHistories(p->numEntriesThirdLocalHistories),
- snb(p->snb),
- logSnb(p->logSnb),
- sm(p->sm),
- tnb(p->tnb),
- logTnb(p->logTnb),
- tm(p->tm)
+ numEntriesSecondLocalHistories(p.numEntriesSecondLocalHistories),
+ numEntriesThirdLocalHistories(p.numEntriesThirdLocalHistories),
+ snb(p.snb),
+ logSnb(p.logSnb),
+ sm(p.sm),
+ tnb(p.tnb),
+ logTnb(p.logTnb),
+ tm(p.tm)
{
initGEHLTable(snb, sm, sgehl, logSnb, ws, -1);
initGEHLTable(tnb, tm, tgehl, logTnb, wt, -1);
}
MPP_StatisticalCorrector_64KB*
-MPP_StatisticalCorrector_64KBParams::create()
+MPP_StatisticalCorrector_64KBParams::create() const
{
- return new MPP_StatisticalCorrector_64KB(this);
+ return new MPP_StatisticalCorrector_64KB(*this);
}
MultiperspectivePerceptronTAGE64KB::MultiperspectivePerceptronTAGE64KB(
- const MultiperspectivePerceptronTAGE64KBParams *p)
+ const MultiperspectivePerceptronTAGE64KBParams &p)
: MultiperspectivePerceptronTAGE(p)
{
}
}
MultiperspectivePerceptronTAGE64KB*
-MultiperspectivePerceptronTAGE64KBParams::create()
+MultiperspectivePerceptronTAGE64KBParams::create() const
{
- return new MultiperspectivePerceptronTAGE64KB(this);
+ return new MultiperspectivePerceptronTAGE64KB(*this);
}
StatisticalCorrector::BranchInfo *bi, Addr corrTarget) override;
public:
MPP_StatisticalCorrector_64KB(
- const MPP_StatisticalCorrector_64KBParams *p);
+ const MPP_StatisticalCorrector_64KBParams &p);
size_t getSizeInBits() const override;
};
void createSpecs() override;
public:
MultiperspectivePerceptronTAGE64KB(
- const MultiperspectivePerceptronTAGE64KBParams *p);
+ const MultiperspectivePerceptronTAGE64KBParams &p);
};
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_64KB_HH__
#include "cpu/pred/multiperspective_perceptron_tage_8KB.hh"
MPP_TAGE_8KB*
-MPP_TAGE_8KBParams::create()
+MPP_TAGE_8KBParams::create() const
{
- return new MPP_TAGE_8KB(this);
+ return new MPP_TAGE_8KB(*this);
}
MPP_LoopPredictor_8KB*
-MPP_LoopPredictor_8KBParams::create()
+MPP_LoopPredictor_8KBParams::create() const
{
- return new MPP_LoopPredictor_8KB(this);
+ return new MPP_LoopPredictor_8KB(*this);
}
MPP_StatisticalCorrector_8KB::MPP_StatisticalCorrector_8KB(
- const MPP_StatisticalCorrector_8KBParams *p)
+ const MPP_StatisticalCorrector_8KBParams &p)
: MPP_StatisticalCorrector(p)
{
}
}
MPP_StatisticalCorrector_8KB*
-MPP_StatisticalCorrector_8KBParams::create()
+MPP_StatisticalCorrector_8KBParams::create() const
{
- return new MPP_StatisticalCorrector_8KB(this);
+ return new MPP_StatisticalCorrector_8KB(*this);
}
MultiperspectivePerceptronTAGE8KB::MultiperspectivePerceptronTAGE8KB(
- const MultiperspectivePerceptronTAGE8KBParams *p)
+ const MultiperspectivePerceptronTAGE8KBParams &p)
: MultiperspectivePerceptronTAGE(p)
{
}
}
MultiperspectivePerceptronTAGE8KB*
-MultiperspectivePerceptronTAGE8KBParams::create()
+MultiperspectivePerceptronTAGE8KBParams::create() const
{
- return new MultiperspectivePerceptronTAGE8KB(this);
+ return new MultiperspectivePerceptronTAGE8KB(*this);
}
#include "params/MPP_TAGE_8KB.hh"
#include "params/MultiperspectivePerceptronTAGE8KB.hh"
-class MPP_TAGE_8KB : public MPP_TAGE {
+class MPP_TAGE_8KB : public MPP_TAGE
+{
public:
- MPP_TAGE_8KB(const MPP_TAGE_8KBParams *p) : MPP_TAGE(p) {}
+ MPP_TAGE_8KB(const MPP_TAGE_8KBParams &p) : MPP_TAGE(p) {}
};
-class MPP_LoopPredictor_8KB : public MPP_LoopPredictor {
+class MPP_LoopPredictor_8KB : public MPP_LoopPredictor
+{
public:
- MPP_LoopPredictor_8KB(MPP_LoopPredictor_8KBParams *p) :
+ MPP_LoopPredictor_8KB(const MPP_LoopPredictor_8KBParams &p) :
MPP_LoopPredictor(p) {}
};
-class MPP_StatisticalCorrector_8KB : public MPP_StatisticalCorrector {
+class MPP_StatisticalCorrector_8KB : public MPP_StatisticalCorrector
+{
StatisticalCorrector::SCThreadHistory *makeThreadHistory() override;
int gPredictions(ThreadID tid, Addr branch_pc,
StatisticalCorrector::BranchInfo* bi, int &lsum, int64_t phist)
void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken,
StatisticalCorrector::BranchInfo *bi, Addr corrTarget) override;
public:
- MPP_StatisticalCorrector_8KB(const MPP_StatisticalCorrector_8KBParams *p);
+ MPP_StatisticalCorrector_8KB(const MPP_StatisticalCorrector_8KBParams &p);
size_t getSizeInBits() const override;
};
class MultiperspectivePerceptronTAGE8KB :
- public MultiperspectivePerceptronTAGE {
+ public MultiperspectivePerceptronTAGE
+{
void createSpecs() override;
public:
MultiperspectivePerceptronTAGE8KB(
- const MultiperspectivePerceptronTAGE8KBParams *p);
+ const MultiperspectivePerceptronTAGE8KBParams &p);
};
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_8KB_HH__
#include "debug/Indirect.hh"
SimpleIndirectPredictor::SimpleIndirectPredictor(
- const SimpleIndirectPredictorParams * params)
+ const SimpleIndirectPredictorParams ¶ms)
: IndirectPredictor(params),
- hashGHR(params->indirectHashGHR),
- hashTargets(params->indirectHashTargets),
- numSets(params->indirectSets),
- numWays(params->indirectWays),
- tagBits(params->indirectTagSize),
- pathLength(params->indirectPathLength),
- instShift(params->instShiftAmt),
- ghrNumBits(params->indirectGHRBits),
- ghrMask((1 << params->indirectGHRBits)-1)
+ hashGHR(params.indirectHashGHR),
+ hashTargets(params.indirectHashTargets),
+ numSets(params.indirectSets),
+ numWays(params.indirectWays),
+ tagBits(params.indirectTagSize),
+ pathLength(params.indirectPathLength),
+ instShift(params.instShiftAmt),
+ ghrNumBits(params.indirectGHRBits),
+ ghrMask((1 << params.indirectGHRBits)-1)
{
if (!isPowerOf2(numSets)) {
- panic("Indirect predictor requires power of 2 number of sets");
+ panic("Indirect predictor requires power of 2 number of sets");
}
- threadInfo.resize(params->numThreads);
+ threadInfo.resize(params.numThreads);
targetCache.resize(numSets);
for (unsigned i = 0; i < numSets; i++) {
}
SimpleIndirectPredictor *
-SimpleIndirectPredictorParams::create()
+SimpleIndirectPredictorParams::create() const
{
- return new SimpleIndirectPredictor(this);
+ return new SimpleIndirectPredictor(*this);
}
class SimpleIndirectPredictor : public IndirectPredictor
{
public:
- SimpleIndirectPredictor(const SimpleIndirectPredictorParams * params);
+ SimpleIndirectPredictor(const SimpleIndirectPredictorParams ¶ms);
bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
#include "params/StatisticalCorrector.hh"
StatisticalCorrector::StatisticalCorrector(
- const StatisticalCorrectorParams *p)
+ const StatisticalCorrectorParams &p)
: SimObject(p),
- logBias(p->logBias),
- logSizeUp(p->logSizeUp),
+ logBias(p.logBias),
+ logSizeUp(p.logSizeUp),
logSizeUps(logSizeUp / 2),
- numEntriesFirstLocalHistories(p->numEntriesFirstLocalHistories),
- bwnb(p->bwnb),
- logBwnb(p->logBwnb),
- bwm(p->bwm),
- lnb(p->lnb),
- logLnb(p->logLnb),
- lm(p->lm),
- inb(p->inb),
- logInb(p->logInb),
- im(p->im),
- chooserConfWidth(p->chooserConfWidth),
- updateThresholdWidth(p->updateThresholdWidth),
- pUpdateThresholdWidth(p->pUpdateThresholdWidth),
- extraWeightsWidth(p->extraWeightsWidth),
- scCountersWidth(p->scCountersWidth),
+ numEntriesFirstLocalHistories(p.numEntriesFirstLocalHistories),
+ bwnb(p.bwnb),
+ logBwnb(p.logBwnb),
+ bwm(p.bwm),
+ lnb(p.lnb),
+ logLnb(p.logLnb),
+ lm(p.lm),
+ inb(p.inb),
+ logInb(p.logInb),
+ im(p.im),
+ chooserConfWidth(p.chooserConfWidth),
+ updateThresholdWidth(p.updateThresholdWidth),
+ pUpdateThresholdWidth(p.pUpdateThresholdWidth),
+ extraWeightsWidth(p.extraWeightsWidth),
+ scCountersWidth(p.scCountersWidth),
firstH(0),
secondH(0),
stats(this)
{
wb.resize(1 << logSizeUps, 4);
- initGEHLTable(lnb, lm, lgehl, logLnb, wl, p->lWeightInitValue);
- initGEHLTable(bwnb, bwm, bwgehl, logBwnb, wbw, p->bwWeightInitValue);
- initGEHLTable(inb, im, igehl, logInb, wi, p->iWeightInitValue);
+ initGEHLTable(lnb, lm, lgehl, logLnb, wl, p.lWeightInitValue);
+ initGEHLTable(bwnb, bwm, bwgehl, logBwnb, wbw, p.bwWeightInitValue);
+ initGEHLTable(inb, im, igehl, logInb, wi, p.iWeightInitValue);
updateThreshold = 35 << 3;
- pUpdateThreshold.resize(1 << logSizeUp, p->initialUpdateThresholdValue);
+ pUpdateThreshold.resize(1 << logSizeUp, p.initialUpdateThresholdValue);
bias.resize(1 << logBias);
biasSK.resize(1 << logBias);
bool usedScPred;
};
- StatisticalCorrector(const StatisticalCorrectorParams *p);
+ StatisticalCorrector(const StatisticalCorrectorParams &p);
virtual BranchInfo *makeBranchInfo();
virtual SCThreadHistory *makeThreadHistory();
#include "debug/Fetch.hh"
#include "debug/Tage.hh"
-TAGE::TAGE(const TAGEParams *params) : BPredUnit(params), tage(params->tage)
+TAGE::TAGE(const TAGEParams ¶ms) : BPredUnit(params), tage(params.tage)
{
}
}
TAGE*
-TAGEParams::create()
+TAGEParams::create() const
{
- return new TAGE(this);
+ return new TAGE(*this);
}
public:
- TAGE(const TAGEParams *params);
+ TAGE(const TAGEParams ¶ms);
// Base class methods.
void uncondBranch(ThreadID tid, Addr br_pc, void* &bp_history) override;
#include "debug/Fetch.hh"
#include "debug/Tage.hh"
-TAGEBase::TAGEBase(const TAGEBaseParams *p)
+TAGEBase::TAGEBase(const TAGEBaseParams &p)
: SimObject(p),
- logRatioBiModalHystEntries(p->logRatioBiModalHystEntries),
- nHistoryTables(p->nHistoryTables),
- tagTableCounterBits(p->tagTableCounterBits),
- tagTableUBits(p->tagTableUBits),
- histBufferSize(p->histBufferSize),
- minHist(p->minHist),
- maxHist(p->maxHist),
- pathHistBits(p->pathHistBits),
- tagTableTagWidths(p->tagTableTagWidths),
- logTagTableSizes(p->logTagTableSizes),
- threadHistory(p->numThreads),
- logUResetPeriod(p->logUResetPeriod),
- initialTCounterValue(p->initialTCounterValue),
- numUseAltOnNa(p->numUseAltOnNa),
- useAltOnNaBits(p->useAltOnNaBits),
- maxNumAlloc(p->maxNumAlloc),
- noSkip(p->noSkip),
- speculativeHistUpdate(p->speculativeHistUpdate),
- instShiftAmt(p->instShiftAmt),
+ logRatioBiModalHystEntries(p.logRatioBiModalHystEntries),
+ nHistoryTables(p.nHistoryTables),
+ tagTableCounterBits(p.tagTableCounterBits),
+ tagTableUBits(p.tagTableUBits),
+ histBufferSize(p.histBufferSize),
+ minHist(p.minHist),
+ maxHist(p.maxHist),
+ pathHistBits(p.pathHistBits),
+ tagTableTagWidths(p.tagTableTagWidths),
+ logTagTableSizes(p.logTagTableSizes),
+ threadHistory(p.numThreads),
+ logUResetPeriod(p.logUResetPeriod),
+ initialTCounterValue(p.initialTCounterValue),
+ numUseAltOnNa(p.numUseAltOnNa),
+ useAltOnNaBits(p.useAltOnNaBits),
+ maxNumAlloc(p.maxNumAlloc),
+ noSkip(p.noSkip),
+ speculativeHistUpdate(p.speculativeHistUpdate),
+ instShiftAmt(p.instShiftAmt),
initialized(false),
stats(this, nHistoryTables)
{
}
TAGEBase*
-TAGEBaseParams::create()
+TAGEBaseParams::create() const
{
- return new TAGEBase(this);
+ return new TAGEBase(*this);
}
class TAGEBase : public SimObject
{
public:
- TAGEBase(const TAGEBaseParams *p);
+ TAGEBase(const TAGEBaseParams &p);
void init() override;
protected:
}
TAGE_SC_L_LoopPredictor *
-TAGE_SC_L_LoopPredictorParams::create()
+TAGE_SC_L_LoopPredictorParams::create() const
{
- return new TAGE_SC_L_LoopPredictor(this);
+ return new TAGE_SC_L_LoopPredictor(*this);
}
-TAGE_SC_L::TAGE_SC_L(const TAGE_SC_LParams *p)
- : LTAGE(p), statisticalCorrector(p->statistical_corrector)
+TAGE_SC_L::TAGE_SC_L(const TAGE_SC_LParams &p)
+ : LTAGE(p), statisticalCorrector(p.statistical_corrector)
{
}
virtual TAGEBase::BranchInfo *makeBranchInfo() override;
- TAGE_SC_L_TAGE(const TAGE_SC_L_TAGEParams *p)
+ TAGE_SC_L_TAGE(const TAGE_SC_L_TAGEParams &p)
: TAGEBase(p),
- firstLongTagTable(p->firstLongTagTable),
- longTagsSize(p->longTagsSize),
- shortTagsSize(p->shortTagsSize),
- logTagTableSize(p->logTagTableSize),
- shortTagsTageFactor(p->shortTagsTageFactor),
- longTagsTageFactor(p->longTagsTageFactor),
- truncatePathHist(p->truncatePathHist)
+ firstLongTagTable(p.firstLongTagTable),
+ longTagsSize(p.longTagsSize),
+ shortTagsSize(p.shortTagsSize),
+ logTagTableSize(p.logTagTableSize),
+ shortTagsTageFactor(p.shortTagsTageFactor),
+ longTagsTageFactor(p.longTagsTageFactor),
+ truncatePathHist(p.truncatePathHist)
{}
void calculateParameters() override;
class TAGE_SC_L_LoopPredictor : public LoopPredictor
{
public:
- TAGE_SC_L_LoopPredictor(TAGE_SC_L_LoopPredictorParams *p)
+ TAGE_SC_L_LoopPredictor(const TAGE_SC_L_LoopPredictorParams &p)
: LoopPredictor(p)
{}
{
StatisticalCorrector *statisticalCorrector;
public:
- TAGE_SC_L(const TAGE_SC_LParams *params);
+ TAGE_SC_L(const TAGE_SC_LParams ¶ms);
bool predict(
ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override;
#include "cpu/pred/tage_sc_l_64KB.hh"
TAGE_SC_L_64KB_StatisticalCorrector::TAGE_SC_L_64KB_StatisticalCorrector(
- TAGE_SC_L_64KB_StatisticalCorrectorParams *p)
+ const TAGE_SC_L_64KB_StatisticalCorrectorParams &p)
: StatisticalCorrector(p),
- numEntriesSecondLocalHistories(p->numEntriesSecondLocalHistories),
- numEntriesThirdLocalHistories(p->numEntriesThirdLocalHistories),
- pnb(p->pnb),
- logPnb(p->logPnb),
- pm(p->pm),
- snb(p->snb),
- logSnb(p->logSnb),
- sm(p->sm),
- tnb(p->tnb),
- logTnb(p->logTnb),
- tm(p->tm),
- imnb(p->imnb),
- logImnb(p->logImnb),
- imm(p->imm)
+ numEntriesSecondLocalHistories(p.numEntriesSecondLocalHistories),
+ numEntriesThirdLocalHistories(p.numEntriesThirdLocalHistories),
+ pnb(p.pnb),
+ logPnb(p.logPnb),
+ pm(p.pm),
+ snb(p.snb),
+ logSnb(p.logSnb),
+ sm(p.sm),
+ tnb(p.tnb),
+ logTnb(p.logTnb),
+ tm(p.tm),
+ imnb(p.imnb),
+ logImnb(p.logImnb),
+ imm(p.imm)
{
initGEHLTable(pnb, pm, pgehl, logPnb, wp, 7);
initGEHLTable(snb, sm, sgehl, logSnb, ws, 7);
}
TAGE_SC_L_64KB_StatisticalCorrector*
-TAGE_SC_L_64KB_StatisticalCorrectorParams::create()
+TAGE_SC_L_64KB_StatisticalCorrectorParams::create() const
{
- return new TAGE_SC_L_64KB_StatisticalCorrector(this);
+ return new TAGE_SC_L_64KB_StatisticalCorrector(*this);
}
int
}
TAGE_SC_L_TAGE_64KB*
-TAGE_SC_L_TAGE_64KBParams::create()
+TAGE_SC_L_TAGE_64KBParams::create() const
{
- return new TAGE_SC_L_TAGE_64KB(this);
+ return new TAGE_SC_L_TAGE_64KB(*this);
}
-TAGE_SC_L_64KB::TAGE_SC_L_64KB(const TAGE_SC_L_64KBParams *params)
+TAGE_SC_L_64KB::TAGE_SC_L_64KB(const TAGE_SC_L_64KBParams ¶ms)
: TAGE_SC_L(params)
{
}
TAGE_SC_L_64KB*
-TAGE_SC_L_64KBParams::create()
+TAGE_SC_L_64KBParams::create() const
{
- return new TAGE_SC_L_64KB(this);
+ return new TAGE_SC_L_64KB(*this);
}
class TAGE_SC_L_TAGE_64KB : public TAGE_SC_L_TAGE {
public:
- TAGE_SC_L_TAGE_64KB(const TAGE_SC_L_TAGE_64KBParams *p) : TAGE_SC_L_TAGE(p)
+ TAGE_SC_L_TAGE_64KB(const TAGE_SC_L_TAGE_64KBParams &p) : TAGE_SC_L_TAGE(p)
{}
int gindex_ext(int index, int bank) const override;
public:
TAGE_SC_L_64KB_StatisticalCorrector(
- TAGE_SC_L_64KB_StatisticalCorrectorParams *p);
+ const TAGE_SC_L_64KB_StatisticalCorrectorParams &p);
unsigned getIndBiasBank(Addr branch_pc, BranchInfo* bi, int hitBank,
int altBank) const override;
class TAGE_SC_L_64KB : public TAGE_SC_L
{
public:
- TAGE_SC_L_64KB(const TAGE_SC_L_64KBParams *params);
+ TAGE_SC_L_64KB(const TAGE_SC_L_64KBParams ¶ms);
};
#endif // __CPU_PRED_TAGE_SC_L_64KB
#include "debug/TageSCL.hh"
TAGE_SC_L_8KB_StatisticalCorrector::TAGE_SC_L_8KB_StatisticalCorrector(
- TAGE_SC_L_8KB_StatisticalCorrectorParams *p)
+ const TAGE_SC_L_8KB_StatisticalCorrectorParams &p)
: StatisticalCorrector(p),
- gnb(p->gnb),
- logGnb(p->logGnb),
- gm(p->gm)
+ gnb(p.gnb),
+ logGnb(p.logGnb),
+ gm(p.gm)
{
initGEHLTable(gnb, gm, ggehl, logGnb, wg, 7);
}
}
TAGE_SC_L_8KB_StatisticalCorrector*
-TAGE_SC_L_8KB_StatisticalCorrectorParams::create()
+TAGE_SC_L_8KB_StatisticalCorrectorParams::create() const
{
- return new TAGE_SC_L_8KB_StatisticalCorrector(this);
+ return new TAGE_SC_L_8KB_StatisticalCorrector(*this);
}
-TAGE_SC_L_8KB::TAGE_SC_L_8KB(const TAGE_SC_L_8KBParams *params)
+TAGE_SC_L_8KB::TAGE_SC_L_8KB(const TAGE_SC_L_8KBParams ¶ms)
: TAGE_SC_L(params)
{
}
}
TAGE_SC_L_TAGE_8KB*
-TAGE_SC_L_TAGE_8KBParams::create()
+TAGE_SC_L_TAGE_8KBParams::create() const
{
- return new TAGE_SC_L_TAGE_8KB(this);
+ return new TAGE_SC_L_TAGE_8KB(*this);
}
TAGE_SC_L_8KB*
-TAGE_SC_L_8KBParams::create()
+TAGE_SC_L_8KBParams::create() const
{
- return new TAGE_SC_L_8KB(this);
+ return new TAGE_SC_L_8KB(*this);
}
class TAGE_SC_L_TAGE_8KB : public TAGE_SC_L_TAGE
{
public:
- TAGE_SC_L_TAGE_8KB(const TAGE_SC_L_TAGE_8KBParams *p) : TAGE_SC_L_TAGE(p)
+ TAGE_SC_L_TAGE_8KB(const TAGE_SC_L_TAGE_8KBParams &p) : TAGE_SC_L_TAGE(p)
{}
void initFoldedHistories(ThreadHistory & history) override;
public:
TAGE_SC_L_8KB_StatisticalCorrector(
- TAGE_SC_L_8KB_StatisticalCorrectorParams *p);
+ const TAGE_SC_L_8KB_StatisticalCorrectorParams &p);
unsigned getIndBiasBank( Addr branch_pc, BranchInfo* bi, int hitBank,
int altBank) const override;
class TAGE_SC_L_8KB : public TAGE_SC_L
{
public:
- TAGE_SC_L_8KB(const TAGE_SC_L_8KBParams *params);
+ TAGE_SC_L_8KB(const TAGE_SC_L_8KBParams ¶ms);
};
#endif // __CPU_PRED_TAGE_SC_L_8KB
#include "base/bitfield.hh"
#include "base/intmath.hh"
-TournamentBP::TournamentBP(const TournamentBPParams *params)
+TournamentBP::TournamentBP(const TournamentBPParams ¶ms)
: BPredUnit(params),
- localPredictorSize(params->localPredictorSize),
- localCtrBits(params->localCtrBits),
+ localPredictorSize(params.localPredictorSize),
+ localCtrBits(params.localCtrBits),
localCtrs(localPredictorSize, SatCounter(localCtrBits)),
- localHistoryTableSize(params->localHistoryTableSize),
- localHistoryBits(ceilLog2(params->localPredictorSize)),
- globalPredictorSize(params->globalPredictorSize),
- globalCtrBits(params->globalCtrBits),
+ localHistoryTableSize(params.localHistoryTableSize),
+ localHistoryBits(ceilLog2(params.localPredictorSize)),
+ globalPredictorSize(params.globalPredictorSize),
+ globalCtrBits(params.globalCtrBits),
globalCtrs(globalPredictorSize, SatCounter(globalCtrBits)),
- globalHistory(params->numThreads, 0),
+ globalHistory(params.numThreads, 0),
globalHistoryBits(
- ceilLog2(params->globalPredictorSize) >
- ceilLog2(params->choicePredictorSize) ?
- ceilLog2(params->globalPredictorSize) :
- ceilLog2(params->choicePredictorSize)),
- choicePredictorSize(params->choicePredictorSize),
- choiceCtrBits(params->choiceCtrBits),
+ ceilLog2(params.globalPredictorSize) >
+ ceilLog2(params.choicePredictorSize) ?
+ ceilLog2(params.globalPredictorSize) :
+ ceilLog2(params.choicePredictorSize)),
+ choicePredictorSize(params.choicePredictorSize),
+ choiceCtrBits(params.choiceCtrBits),
choiceCtrs(choicePredictorSize, SatCounter(choiceCtrBits))
{
if (!isPowerOf2(localPredictorSize)) {
}
TournamentBP*
-TournamentBPParams::create()
+TournamentBPParams::create() const
{
- return new TournamentBP(this);
+ return new TournamentBP(*this);
}
#ifdef DEBUG
/**
* Default branch predictor constructor.
*/
- TournamentBP(const TournamentBPParams *params);
+ TournamentBP(const TournamentBPParams ¶ms);
/**
* Looks up the given address in the branch predictor and returns
type = 'NonCachingSimpleCPU'
cxx_header = "cpu/simple/noncaching.hh"
+ numThreads = 1
+
@classmethod
def memory_mode(cls):
return 'atomic_noncaching'
@classmethod
def support_take_over(cls):
return True
-
data_amo_req->setContext(cid);
}
-AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
+AtomicSimpleCPU::AtomicSimpleCPU(const AtomicSimpleCPUParams &p)
: BaseSimpleCPU(p),
tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
false, Event::CPU_Tick_Pri),
- width(p->width), locked(false),
- simulate_data_stalls(p->simulate_data_stalls),
- simulate_inst_stalls(p->simulate_inst_stalls),
+ width(p.width), locked(false),
+ simulate_data_stalls(p.simulate_data_stalls),
+ simulate_inst_stalls(p.simulate_inst_stalls),
icachePort(name() + ".icache_port", this),
dcachePort(name() + ".dcache_port", this),
dcache_access(false), dcache_latency(0),
// AtomicSimpleCPU Simulation Object
//
AtomicSimpleCPU *
-AtomicSimpleCPUParams::create()
+AtomicSimpleCPUParams::create() const
{
- return new AtomicSimpleCPU(this);
+ return new AtomicSimpleCPU(*this);
}
{
public:
- AtomicSimpleCPU(AtomicSimpleCPUParams *params);
+ AtomicSimpleCPU(const AtomicSimpleCPUParams ¶ms);
virtual ~AtomicSimpleCPU();
void init() override;
using namespace std;
using namespace TheISA;
-BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
+BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
: BaseCPU(p),
curThread(0),
- branchPred(p->branchPred),
+ branchPred(p.branchPred),
traceData(NULL),
inst(),
_status(Idle)
for (unsigned i = 0; i < numThreads; i++) {
if (FullSystem) {
- thread = new SimpleThread(this, i, p->system,
- p->itb, p->dtb, p->isa[i]);
+ thread = new SimpleThread(this, i, p.system,
+ p.itb, p.dtb, p.isa[i]);
} else {
- thread = new SimpleThread(this, i, p->system, p->workload[i],
- p->itb, p->dtb, p->isa[i]);
+ thread = new SimpleThread(this, i, p.system, p.workload[i],
+ p.itb, p.dtb, p.isa[i]);
}
threadInfo.push_back(new SimpleExecContext(this, thread));
ThreadContext *tc = thread->getTC();
threadContexts.push_back(tc);
}
- if (p->checker) {
+ if (p.checker) {
if (numThreads != 1)
fatal("Checker currently does not support SMT");
- BaseCPU *temp_checker = p->checker;
+ BaseCPU *temp_checker = p.checker;
checker = dynamic_cast<CheckerCPU *>(temp_checker);
- checker->setSystem(p->system);
+ checker->setSystem(p.system);
// Manipulate thread context
ThreadContext *cpu_tc = threadContexts[0];
threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
void swapActiveThread();
public:
- BaseSimpleCPU(BaseSimpleCPUParams *params);
+ BaseSimpleCPU(const BaseSimpleCPUParams ¶ms);
virtual ~BaseSimpleCPU();
void wakeup(ThreadID tid) override;
void init() override;
#include "cpu/simple/noncaching.hh"
-NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
+#include <cassert>
+
+NonCachingSimpleCPU::NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)
: AtomicSimpleCPU(p)
{
}
}
NonCachingSimpleCPU *
-NonCachingSimpleCPUParams::create()
+NonCachingSimpleCPUParams::create() const
{
- numThreads = 1;
+ assert(numThreads == 1);
if (!FullSystem && workload.size() != 1)
fatal("only one workload allowed");
- return new NonCachingSimpleCPU(this);
+ return new NonCachingSimpleCPU(*this);
}
class NonCachingSimpleCPU : public AtomicSimpleCPU
{
public:
- NonCachingSimpleCPU(NonCachingSimpleCPUParams *p);
+ NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p);
void verifyMemoryMode() const override;
#include "base/output.hh"
-SimPoint::SimPoint(const SimPointParams *p)
+SimPoint::SimPoint(const SimPointParams &p)
: ProbeListenerObject(p),
- intervalSize(p->interval),
+ intervalSize(p.interval),
intervalCount(0),
intervalDrift(0),
simpointStream(NULL),
currentBBV(0, 0),
currentBBVInstCount(0)
{
- simpointStream = simout.create(p->profile_file, false);
+ simpointStream = simout.create(p.profile_file, false);
if (!simpointStream)
fatal("unable to open SimPoint profile_file");
}
/** SimPoint SimObject */
SimPoint*
-SimPointParams::create()
+SimPointParams::create() const
{
- return new SimPoint(this);
+ return new SimPoint(*this);
}
class SimPoint : public ProbeListenerObject
{
public:
- SimPoint(const SimPointParams *params);
+ SimPoint(const SimPointParams ¶ms);
virtual ~SimPoint();
virtual void init();
cpu->schedule(this, t);
}
-TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
+TimingSimpleCPU::TimingSimpleCPU(const TimingSimpleCPUParams &p)
: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
fetchEvent([this]{ fetch(); }, name())
// TimingSimpleCPU Simulation Object
//
TimingSimpleCPU *
-TimingSimpleCPUParams::create()
+TimingSimpleCPUParams::create() const
{
- return new TimingSimpleCPU(this);
+ return new TimingSimpleCPU(*this);
}
{
public:
- TimingSimpleCPU(TimingSimpleCPUParams * params);
+ TimingSimpleCPU(const TimingSimpleCPUParams ¶ms);
virtual ~TimingSimpleCPU();
void init() override;
#include "sim/system.hh"
-DirectedGenerator::DirectedGenerator(const Params *p)
+DirectedGenerator::DirectedGenerator(const Params &p)
: SimObject(p),
- requestorId(p->system->getRequestorId(this))
+ requestorId(p.system->getRequestorId(this))
{
- m_num_cpus = p->num_cpus;
+ m_num_cpus = p.num_cpus;
m_directed_tester = NULL;
}
{
public:
typedef DirectedGeneratorParams Params;
- DirectedGenerator(const Params *p);
+ DirectedGenerator(const Params &p);
virtual ~DirectedGenerator() {}
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
-InvalidateGenerator::InvalidateGenerator(const Params *p)
+InvalidateGenerator::InvalidateGenerator(const Params &p)
: DirectedGenerator(p)
{
//
m_active_read_node = 0;
m_active_inv_node = 0;
m_address = 0x0;
- m_addr_increment_size = p->addr_increment_size;
+ m_addr_increment_size = p.addr_increment_size;
}
InvalidateGenerator::~InvalidateGenerator()
}
InvalidateGenerator *
-InvalidateGeneratorParams::create()
+InvalidateGeneratorParams::create() const
{
- return new InvalidateGenerator(this);
+ return new InvalidateGenerator(*this);
}
{
public:
typedef InvalidateGeneratorParams Params;
- InvalidateGenerator(const Params *p);
+ InvalidateGenerator(const Params &p);
~InvalidateGenerator();
#include "debug/DirectedTest.hh"
#include "sim/sim_exit.hh"
-RubyDirectedTester::RubyDirectedTester(const Params *p)
+RubyDirectedTester::RubyDirectedTester(const Params &p)
: ClockedObject(p),
directedStartEvent([this]{ wakeup(); }, "Directed tick",
false, Event::CPU_Tick_Pri),
- m_requests_to_complete(p->requests_to_complete),
- generator(p->generator)
+ m_requests_to_complete(p.requests_to_complete),
+ generator(p.generator)
{
m_requests_completed = 0;
// create the ports
- for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpuPort_connection_count; ++i) {
ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
this, i));
}
}
RubyDirectedTester *
-RubyDirectedTesterParams::create()
+RubyDirectedTesterParams::create() const
{
- return new RubyDirectedTester(this);
+ return new RubyDirectedTester(*this);
}
};
typedef RubyDirectedTesterParams Params;
- RubyDirectedTester(const Params *p);
+ RubyDirectedTester(const Params &p);
~RubyDirectedTester();
Port &getPort(const std::string &if_name,
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
-SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
+SeriesRequestGenerator::SeriesRequestGenerator(const Params &p)
: DirectedGenerator(p),
- m_addr_increment_size(p->addr_increment_size),
- m_percent_writes(p->percent_writes)
+ m_addr_increment_size(p.addr_increment_size),
+ m_percent_writes(p.percent_writes)
{
m_status = SeriesRequestGeneratorStatus_Thinking;
m_active_node = 0;
}
SeriesRequestGenerator *
-SeriesRequestGeneratorParams::create()
+SeriesRequestGeneratorParams::create() const
{
- return new SeriesRequestGenerator(this);
+ return new SeriesRequestGenerator(*this);
}
{
public:
typedef SeriesRequestGeneratorParams Params;
- SeriesRequestGenerator(const Params *p);
+ SeriesRequestGenerator(const Params &p);
~SeriesRequestGenerator();
numPacketsSent++;
}
-GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p)
+GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params &p)
: ClockedObject(p),
tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick",
false, Event::CPU_Tick_Pri),
cachePort("GarnetSyntheticTraffic", this),
retryPkt(NULL),
- size(p->memory_size),
- blockSizeBits(p->block_offset),
- numDestinations(p->num_dest),
- simCycles(p->sim_cycles),
- numPacketsMax(p->num_packets_max),
+ size(p.memory_size),
+ blockSizeBits(p.block_offset),
+ numDestinations(p.num_dest),
+ simCycles(p.sim_cycles),
+ numPacketsMax(p.num_packets_max),
numPacketsSent(0),
- singleSender(p->single_sender),
- singleDest(p->single_dest),
- trafficType(p->traffic_type),
- injRate(p->inj_rate),
- injVnet(p->inj_vnet),
- precision(p->precision),
- responseLimit(p->response_limit),
- requestorId(p->system->getRequestorId(this))
+ singleSender(p.single_sender),
+ singleDest(p.single_dest),
+ trafficType(p.traffic_type),
+ injRate(p.inj_rate),
+ injVnet(p.inj_vnet),
+ precision(p.precision),
+ responseLimit(p.response_limit),
+ requestorId(p.system->getRequestorId(this))
{
// set up counters
noResponseCycles = 0;
GarnetSyntheticTraffic *
-GarnetSyntheticTrafficParams::create()
+GarnetSyntheticTrafficParams::create() const
{
- return new GarnetSyntheticTraffic(this);
+ return new GarnetSyntheticTraffic(*this);
}
{
public:
typedef GarnetSyntheticTrafficParams Params;
- GarnetSyntheticTraffic(const Params *p);
+ GarnetSyntheticTraffic(const Params &p);
void init() override;
return true;
}
-MemTest::MemTest(const Params *p)
+MemTest::MemTest(const Params &p)
: ClockedObject(p),
tickEvent([this]{ tick(); }, name()),
noRequestEvent([this]{ noRequest(); }, name()),
noResponseEvent([this]{ noResponse(); }, name()),
port("port", *this),
retryPkt(nullptr),
- size(p->size),
- interval(p->interval),
- percentReads(p->percent_reads),
- percentFunctional(p->percent_functional),
- percentUncacheable(p->percent_uncacheable),
- requestorId(p->system->getRequestorId(this)),
- blockSize(p->system->cacheLineSize()),
+ size(p.size),
+ interval(p.interval),
+ percentReads(p.percent_reads),
+ percentFunctional(p.percent_functional),
+ percentUncacheable(p.percent_uncacheable),
+ requestorId(p.system->getRequestorId(this)),
+ blockSize(p.system->cacheLineSize()),
blockAddrMask(blockSize - 1),
- progressInterval(p->progress_interval),
- progressCheck(p->progress_check),
- nextProgressMessage(p->progress_interval),
- maxLoads(p->max_loads),
- atomic(p->system->isAtomicMode()),
- suppressFuncErrors(p->suppress_func_errors), stats(this)
+ progressInterval(p.progress_interval),
+ progressCheck(p.progress_check),
+ nextProgressMessage(p.progress_interval),
+ maxLoads(p.max_loads),
+ atomic(p.system->isAtomicMode()),
+ suppressFuncErrors(p.suppress_func_errors), stats(this)
{
id = TESTER_ALLOCATOR++;
fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
}
MemTest *
-MemTestParams::create()
+MemTestParams::create() const
{
- return new MemTest(this);
+ return new MemTest(*this);
}
public:
typedef MemTestParams Params;
- MemTest(const Params *p);
+ MemTest(const Params &p);
Port &getPort(const std::string &if_name,
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-RubyTester::RubyTester(const Params *p)
+RubyTester::RubyTester(const Params &p)
: ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
false, Event::CPU_Tick_Pri),
- _requestorId(p->system->getRequestorId(this)),
+ _requestorId(p.system->getRequestorId(this)),
m_checkTable_ptr(nullptr),
- m_num_cpus(p->num_cpus),
- m_checks_to_complete(p->checks_to_complete),
- m_deadlock_threshold(p->deadlock_threshold),
+ m_num_cpus(p.num_cpus),
+ m_checks_to_complete(p.checks_to_complete),
+ m_deadlock_threshold(p.deadlock_threshold),
m_num_writers(0),
m_num_readers(0),
- m_wakeup_frequency(p->wakeup_frequency),
- m_check_flush(p->check_flush),
- m_num_inst_only_ports(p->port_cpuInstPort_connection_count),
- m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count)
+ m_wakeup_frequency(p.wakeup_frequency),
+ m_check_flush(p.check_flush),
+ m_num_inst_only_ports(p.port_cpuInstPort_connection_count),
+ m_num_inst_data_ports(p.port_cpuInstDataPort_connection_count)
{
m_checks_completed = 0;
// then the data ports are added to the readPort vector
//
int idx = 0;
- for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpuInstPort_connection_count; ++i) {
readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
this, i, idx));
idx++;
}
- for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpuInstDataPort_connection_count; ++i) {
CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i),
this, i, idx);
readPorts.push_back(port);
writePorts.push_back(port);
idx++;
}
- for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpuDataPort_connection_count; ++i) {
CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
this, i, idx);
readPorts.push_back(port);
}
RubyTester *
-RubyTesterParams::create()
+RubyTesterParams::create() const
{
- return new RubyTester(this);
+ return new RubyTester(*this);
}
};
typedef RubyTesterParams Params;
- RubyTester(const Params *p);
+ RubyTester(const Params &p);
~RubyTester();
Port &getPort(const std::string &if_name,
using namespace std;
-BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams* p)
+BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams &p)
: ClockedObject(p),
- system(p->system),
- elasticReq(p->elastic_req),
- progressCheck(p->progress_check),
+ system(p.system),
+ elasticReq(p.elastic_req),
+ progressCheck(p.progress_check),
noProgressEvent([this]{ noProgress(); }, name()),
nextTransitionTick(0),
nextPacketTick(0),
- maxOutstandingReqs(p->max_outstanding_reqs),
+ maxOutstandingReqs(p.max_outstanding_reqs),
port(name() + ".port", *this),
retryPkt(NULL),
retryPktTick(0), blockedWaitingResp(false),
} stats;
public:
- BaseTrafficGen(const BaseTrafficGenParams* p);
+ BaseTrafficGen(const BaseTrafficGenParams &p);
~BaseTrafficGen();
namespace py = pybind11;
-PyTrafficGen::PyTrafficGen(const PyTrafficGenParams *p)
+PyTrafficGen::PyTrafficGen(const PyTrafficGenParams &p)
: BaseTrafficGen(p)
{
}
static EmbeddedPyBind _py_tracers("trace", pybind_init_tracers);
PyTrafficGen*
-PyTrafficGenParams::create()
+PyTrafficGenParams::create() const
{
- return new PyTrafficGen(this);
+ return new PyTrafficGen(*this);
}
class M5_LOCAL PyTrafficGen : public BaseTrafficGen
{
public:
- PyTrafficGen(const PyTrafficGenParams* p);
+ PyTrafficGen(const PyTrafficGenParams &p);
~PyTrafficGen() {}
public: // Python API
#include "base/random.hh"
StreamGen*
-StreamGen::create(const BaseTrafficGenParams *p)
+StreamGen::create(const BaseTrafficGenParams &p)
{
- switch (p->stream_gen) {
+ switch (p.stream_gen) {
case StreamGenType::fixed:
return new FixedStreamGen(p);
case StreamGenType::random:
class StreamGen
{
protected:
- StreamGen(const BaseTrafficGenParams *p)
- : streamIds(p->sids), substreamIds(p->ssids)
+ StreamGen(const BaseTrafficGenParams &p)
+ : streamIds(p.sids), substreamIds(p.ssids)
{
// A non empty vector of StreamIDs must be provided.
// SubstreamIDs are not mandatory hence having an empty
* the stream generator type is stored.
* @return a pointer to the newly alocated StremGen
*/
- static StreamGen* create(const BaseTrafficGenParams *p);
+ static StreamGen* create(const BaseTrafficGenParams &p);
/**
* Returns true if the substreamID generation is valid
class FixedStreamGen : public StreamGen
{
public:
- FixedStreamGen(const BaseTrafficGenParams *p)
+ FixedStreamGen(const BaseTrafficGenParams &p)
: StreamGen(p)
{
// For a fixed stream generator only one sid must be provided. The
class RandomStreamGen : public StreamGen
{
public:
- RandomStreamGen(const BaseTrafficGenParams *p)
+ RandomStreamGen(const BaseTrafficGenParams &p)
: StreamGen(p)
{}
using namespace std;
-TrafficGen::TrafficGen(const TrafficGenParams* p)
+TrafficGen::TrafficGen(const TrafficGenParams &p)
: BaseTrafficGen(p),
- configFile(p->config_file),
+ configFile(p.config_file),
currState(0)
{
}
TrafficGen*
-TrafficGenParams::create()
+TrafficGenParams::create() const
{
- return new TrafficGen(this);
+ return new TrafficGen(*this);
}
void
public:
- TrafficGen(const TrafficGenParams* p);
+ TrafficGen(const TrafficGenParams &p);
~TrafficGen() {}
}
TimingExprLiteral *
-TimingExprLiteralParams::create()
+TimingExprLiteralParams::create() const
{
- return new TimingExprLiteral(this);
+ return new TimingExprLiteral(*this);
}
TimingExprSrcReg *
-TimingExprSrcRegParams::create()
+TimingExprSrcRegParams::create() const
{
- return new TimingExprSrcReg(this);
+ return new TimingExprSrcReg(*this);
}
TimingExprReadIntReg *
-TimingExprReadIntRegParams::create()
+TimingExprReadIntRegParams::create() const
{
- return new TimingExprReadIntReg(this);
+ return new TimingExprReadIntReg(*this);
}
TimingExprLet *
-TimingExprLetParams::create()
+TimingExprLetParams::create() const
{
- return new TimingExprLet(this);
+ return new TimingExprLet(*this);
}
TimingExprRef *
-TimingExprRefParams::create()
+TimingExprRefParams::create() const
{
- return new TimingExprRef(this);
+ return new TimingExprRef(*this);
}
TimingExprUn *
-TimingExprUnParams::create()
+TimingExprUnParams::create() const
{
- return new TimingExprUn(this);
+ return new TimingExprUn(*this);
}
TimingExprBin *
-TimingExprBinParams::create()
+TimingExprBinParams::create() const
{
- return new TimingExprBin(this);
+ return new TimingExprBin(*this);
}
TimingExprIf *
-TimingExprIfParams::create()
+TimingExprIfParams::create() const
{
- return new TimingExprIf(this);
+ return new TimingExprIf(*this);
}
class TimingExpr : public SimObject
{
public:
- TimingExpr(const TimingExprParams *params) :
+ TimingExpr(const TimingExprParams ¶ms) :
SimObject(params)
{ }
public:
uint64_t value;
- TimingExprLiteral(const TimingExprLiteralParams *params) :
+ TimingExprLiteral(const TimingExprLiteralParams ¶ms) :
TimingExpr(params),
- value(params->value)
+ value(params.value)
{ }
uint64_t eval(TimingExprEvalContext &context) { return value; }
public:
unsigned int index;
- TimingExprSrcReg(const TimingExprSrcRegParams *params) :
+ TimingExprSrcReg(const TimingExprSrcRegParams ¶ms) :
TimingExpr(params),
- index(params->index)
+ index(params.index)
{ }
uint64_t eval(TimingExprEvalContext &context);
public:
TimingExpr *reg;
- TimingExprReadIntReg(const TimingExprReadIntRegParams *params) :
+ TimingExprReadIntReg(const TimingExprReadIntRegParams ¶ms) :
TimingExpr(params),
- reg(params->reg)
+ reg(params.reg)
{ }
uint64_t eval(TimingExprEvalContext &context);
std::vector<TimingExpr *> defns;
TimingExpr *expr;
- TimingExprLet(const TimingExprLetParams *params) :
+ TimingExprLet(const TimingExprLetParams ¶ms) :
TimingExpr(params),
- defns(params->defns),
- expr(params->expr)
+ defns(params.defns),
+ expr(params.expr)
{ }
uint64_t eval(TimingExprEvalContext &context);
public:
unsigned int index;
- TimingExprRef(const TimingExprRefParams *params) :
+ TimingExprRef(const TimingExprRefParams ¶ms) :
TimingExpr(params),
- index(params->index)
+ index(params.index)
{ }
uint64_t eval(TimingExprEvalContext &context);
Enums::TimingExprOp op;
TimingExpr *arg;
- TimingExprUn(const TimingExprUnParams *params) :
+ TimingExprUn(const TimingExprUnParams ¶ms) :
TimingExpr(params),
- op(params->op),
- arg(params->arg)
+ op(params.op),
+ arg(params.arg)
{ }
uint64_t eval(TimingExprEvalContext &context);
TimingExpr *left;
TimingExpr *right;
- TimingExprBin(const TimingExprBinParams *params) :
+ TimingExprBin(const TimingExprBinParams ¶ms) :
TimingExpr(params),
- op(params->op),
- left(params->left),
- right(params->right)
+ op(params.op),
+ left(params.left),
+ right(params.right)
{ }
uint64_t eval(TimingExprEvalContext &context);
TimingExpr *trueExpr;
TimingExpr *falseExpr;
- TimingExprIf(const TimingExprIfParams *params) :
+ TimingExprIf(const TimingExprIfParams ¶ms) :
TimingExpr(params),
- cond(params->cond),
- trueExpr(params->trueExpr),
- falseExpr(params->falseExpr)
+ cond(params.cond),
+ trueExpr(params.trueExpr),
+ falseExpr(params.falseExpr)
{ }
uint64_t eval(TimingExprEvalContext &context);
// Declare and initialize the static counter for number of trace CPUs.
int TraceCPU::numTraceCPUs = 0;
-TraceCPU::TraceCPU(TraceCPUParams *params)
+TraceCPU::TraceCPU(const TraceCPUParams ¶ms)
: BaseCPU(params),
icachePort(this),
dcachePort(this),
- instRequestorID(params->system->getRequestorId(this, "inst")),
- dataRequestorID(params->system->getRequestorId(this, "data")),
- instTraceFile(params->instTraceFile),
- dataTraceFile(params->dataTraceFile),
+ instRequestorID(params.system->getRequestorId(this, "inst")),
+ dataRequestorID(params.system->getRequestorId(this, "data")),
+ instTraceFile(params.instTraceFile),
+ dataTraceFile(params.dataTraceFile),
icacheGen(*this, ".iside", icachePort, instRequestorID, instTraceFile),
dcacheGen(*this, ".dside", dcachePort, dataRequestorID, dataTraceFile,
params),
oneTraceComplete(false),
traceOffset(0),
execCompleteEvent(nullptr),
- enableEarlyExit(params->enableEarlyExit),
- progressMsgInterval(params->progressMsgInterval),
- progressMsgThreshold(params->progressMsgInterval), traceStats(this)
+ enableEarlyExit(params.enableEarlyExit),
+ progressMsgInterval(params.progressMsgInterval),
+ progressMsgThreshold(params.progressMsgInterval), traceStats(this)
{
// Increment static counter for number of Trace CPUs.
++TraceCPU::numTraceCPUs;
// Check that the python parameters for sizes of ROB, store buffer and
// load buffer do not overflow the corresponding C++ variables.
- fatal_if(params->sizeROB > UINT16_MAX, "ROB size set to %d exceeds the "
- "max. value of %d.\n", params->sizeROB, UINT16_MAX);
- fatal_if(params->sizeStoreBuffer > UINT16_MAX, "ROB size set to %d "
- "exceeds the max. value of %d.\n", params->sizeROB,
+ fatal_if(params.sizeROB > UINT16_MAX, "ROB size set to %d exceeds the "
+ "max. value of %d.\n", params.sizeROB, UINT16_MAX);
+ fatal_if(params.sizeStoreBuffer > UINT16_MAX, "ROB size set to %d "
+ "exceeds the max. value of %d.\n", params.sizeROB,
UINT16_MAX);
- fatal_if(params->sizeLoadBuffer > UINT16_MAX, "Load buffer size set to"
+ fatal_if(params.sizeLoadBuffer > UINT16_MAX, "Load buffer size set to"
" %d exceeds the max. value of %d.\n",
- params->sizeLoadBuffer, UINT16_MAX);
+ params.sizeLoadBuffer, UINT16_MAX);
}
TraceCPU::~TraceCPU()
}
TraceCPU*
-TraceCPUParams::create()
+TraceCPUParams::create() const
{
- return new TraceCPU(this);
+ return new TraceCPU(*this);
}
void
{
public:
- TraceCPU(TraceCPUParams *params);
+ TraceCPU(const TraceCPUParams ¶ms);
~TraceCPU();
void init();
/* Constructor */
ElasticDataGen(TraceCPU& _owner, const std::string& _name,
RequestPort& _port, RequestorID requestor_id,
- const std::string& trace_file, TraceCPUParams *params)
+ const std::string& trace_file, const TraceCPUParams ¶ms)
: owner(_owner),
port(_port),
requestorId(requestor_id),
- trace(trace_file, 1.0 / params->freqMultiplier),
+ trace(trace_file, 1.0 / params.freqMultiplier),
genName(owner.name() + ".elastic." + _name),
retryPkt(nullptr),
traceComplete(false),
nextRead(false),
execComplete(false),
windowSize(trace.getWindowSize()),
- hwResource(params->sizeROB, params->sizeStoreBuffer,
- params->sizeLoadBuffer), elasticStats(&_owner, _name)
+ hwResource(params.sizeROB, params.sizeStoreBuffer,
+ params.sizeLoadBuffer), elasticStats(&_owner, _name)
{
DPRINTF(TraceCPUData, "Window size in the trace is %d.\n",
windowSize);
#include "mem/packet_access.hh"
#include "sim/system.hh"
-A9SCU::A9SCU(Params *p)
+A9SCU::A9SCU(const Params &p)
: BasicPioDevice(p, 0x60)
{
}
}
A9SCU *
-A9SCUParams::create()
+A9SCUParams::create() const
{
- return new A9SCU(this);
+ return new A9SCU(*this);
}
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- A9SCU(Params *p);
+ A9SCU(const Params &p);
/**
* Handle a read to the device
{
public:
- AbstractNVM(const AbstractNVMParams* p): SimObject(p) {};
+ AbstractNVM(const AbstractNVMParams &p): SimObject(p) {};
virtual ~AbstractNVM() {};
/**
const uint64_t AmbaVendor = ULL(0xb105f00d00000000);
-AmbaPioDevice::AmbaPioDevice(const Params *p, Addr pio_size)
- : BasicPioDevice(p, pio_size), ambaId(AmbaVendor | p->amba_id)
+AmbaPioDevice::AmbaPioDevice(const Params &p, Addr pio_size)
+ : BasicPioDevice(p, pio_size), ambaId(AmbaVendor | p.amba_id)
{
}
-AmbaIntDevice::AmbaIntDevice(const Params *p, Addr pio_size)
+AmbaIntDevice::AmbaIntDevice(const Params &p, Addr pio_size)
: AmbaPioDevice(p, pio_size),
- interrupt(p->interrupt->get()), intDelay(p->int_delay)
+ interrupt(p.interrupt->get()), intDelay(p.int_delay)
{
}
-AmbaDmaDevice::AmbaDmaDevice(const Params *p, Addr pio_size)
- : DmaDevice(p), ambaId(AmbaVendor | p->amba_id),
- pioAddr(p->pio_addr), pioSize(pio_size),
- pioDelay(p->pio_latency), interrupt(p->interrupt->get())
+AmbaDmaDevice::AmbaDmaDevice(const Params &p, Addr pio_size)
+ : DmaDevice(p), ambaId(AmbaVendor | p.amba_id),
+ pioAddr(p.pio_addr), pioSize(pio_size),
+ pioDelay(p.pio_latency), interrupt(p.interrupt->get())
{
}
public:
typedef AmbaPioDeviceParams Params;
- AmbaPioDevice(const Params *p, Addr pio_size);
+ AmbaPioDevice(const Params &p, Addr pio_size);
};
class AmbaIntDevice : public AmbaPioDevice
public:
typedef AmbaIntDeviceParams Params;
- AmbaIntDevice(const Params *p, Addr pio_size);
+ AmbaIntDevice(const Params &p, Addr pio_size);
};
class AmbaDmaDevice : public DmaDevice, public AmbaDevice
public:
typedef AmbaDmaDeviceParams Params;
- AmbaDmaDevice(const Params *p, Addr pio_size = 0);
+ AmbaDmaDevice(const Params &p, Addr pio_size = 0);
};
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-AmbaFake::AmbaFake(const Params *p)
+AmbaFake::AmbaFake(const Params &p)
: AmbaPioDevice(p, 0x1000)
{
}
DPRINTF(AMBA, " read register %#x\n", daddr);
pkt->setLE<uint32_t>(0);
- if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
+ if (!readId(pkt, ambaId, pioAddr) && !params().ignore_access)
panic("Tried to read AmbaFake %s at offset %#x that doesn't exist\n",
name(), daddr);
Addr daddr = pkt->getAddr() - pioAddr;
- if (!params()->ignore_access)
+ if (!params().ignore_access)
panic("Tried to write AmbaFake %s at offset %#x that doesn't exist\n",
name(), daddr);
AmbaFake *
-AmbaFakeParams::create()
+AmbaFakeParams::create() const
{
- return new AmbaFake(this);
+ return new AmbaFake(*this);
}
class AmbaFake : public AmbaPioDevice
{
public:
- typedef AmbaFakeParams Params;
- const Params *
+ typedef AmbaFakeParams Params;
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- AmbaFake(const Params *p);
+ AmbaFake(const Params &p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
#include "params/ArmSPI.hh"
#include "params/BaseGic.hh"
-BaseGic::BaseGic(const Params *p)
+BaseGic::BaseGic(const Params &p)
: PioDevice(p),
- platform(p->platform)
+ platform(p.platform)
{
- RealView *const rv(dynamic_cast<RealView*>(p->platform));
+ RealView *const rv = dynamic_cast<RealView*>(p.platform);
// The platform keeps track of the GIC that is hooked up to the
// system. Due to quirks in gem5's configuration system, the
// platform can't take a GIC as parameter. Instead, we need to
getSystem()->setGIC(this);
}
-const BaseGic::Params *
+const BaseGic::Params &
BaseGic::params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
-ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams *p)
+ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams &p)
: SimObject(p)
{
}
-ArmSPIGen::ArmSPIGen(const ArmSPIParams *p)
- : ArmInterruptPinGen(p), pin(new ArmSPI(p->platform, p->num))
+ArmSPIGen::ArmSPIGen(const ArmSPIParams &p)
+ : ArmInterruptPinGen(p), pin(new ArmSPI(p.platform, p.num))
{
}
return pin;
}
-ArmPPIGen::ArmPPIGen(const ArmPPIParams *p)
+ArmPPIGen::ArmPPIGen(const ArmPPIParams &p)
: ArmInterruptPinGen(p)
{
}
return pin_it->second;
} else {
// Generate PPI Pin
- auto p = static_cast<const ArmPPIParams *>(_params);
- ArmPPI *pin = new ArmPPI(p->platform, tc, p->num);
+ auto &p = static_cast<const ArmPPIParams &>(_params);
+ ArmPPI *pin = new ArmPPI(p.platform, tc, p.num);
pins.insert({cid, pin});
}
ArmSPIGen *
-ArmSPIParams::create()
+ArmSPIParams::create() const
{
- return new ArmSPIGen(this);
+ return new ArmSPIGen(*this);
}
ArmPPIGen *
-ArmPPIParams::create()
+ArmPPIParams::create() const
{
- return new ArmPPIGen(this);
+ return new ArmPPIGen(*this);
}
typedef BaseGicParams Params;
enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
- BaseGic(const Params *p);
+ BaseGic(const Params &p);
virtual ~BaseGic();
void init() override;
- const Params * params() const;
+ const Params ¶ms() const;
/**
* Post an interrupt from a device that is connected to the GIC.
class ArmInterruptPinGen : public SimObject
{
public:
- ArmInterruptPinGen(const ArmInterruptPinParams *p);
+ ArmInterruptPinGen(const ArmInterruptPinParams &p);
virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
};
class ArmSPIGen : public ArmInterruptPinGen
{
public:
- ArmSPIGen(const ArmSPIParams *p);
+ ArmSPIGen(const ArmSPIParams &p);
ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
protected:
class ArmPPIGen : public ArmInterruptPinGen
{
public:
- ArmPPIGen(const ArmPPIParams *p);
+ ArmPPIGen(const ArmPPIParams &p);
ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
protected:
#include "params/Display.hh"
-Display::Display(const DisplayParams *p)
+Display::Display(const DisplayParams &p)
: SimObject(p)
{}
Display *
-DisplayParams::create()
+DisplayParams::create() const
{
- return new Display(this);
+ return new Display(*this);
}
class Display : public SimObject
{
public:
- Display(const DisplayParams *p);
+ Display(const DisplayParams &p);
};
#endif // __DEV_ARM_DISPLAY_H__
#include "params/EnergyCtrl.hh"
#include "sim/dvfs_handler.hh"
-EnergyCtrl::EnergyCtrl(const Params *p)
+EnergyCtrl::EnergyCtrl(const Params &p)
: BasicPioDevice(p, PIO_NUM_FIELDS * 4), // each field is 32 bit
- dvfsHandler(p->dvfs_handler),
+ dvfsHandler(p.dvfs_handler),
domainID(0),
domainIDIndexToRead(0),
perfLevelAck(0),
perfLevelToRead(0),
updateAckEvent([this]{ updatePLAck(); }, name())
{
- fatal_if(!p->dvfs_handler, "EnergyCtrl: Needs a DVFSHandler for a "
+ fatal_if(!p.dvfs_handler, "EnergyCtrl: Needs a DVFSHandler for a "
"functioning system.\n");
}
}
}
-EnergyCtrl * EnergyCtrlParams::create()
+EnergyCtrl *
+EnergyCtrlParams::create() const
{
- return new EnergyCtrl(this);
+ return new EnergyCtrl(*this);
}
void
};
typedef EnergyCtrlParams Params;
- EnergyCtrl(const Params *p);
+ EnergyCtrl(const Params &p);
/**
* Read command sent to the device
*/
FlashDevice*
-FlashDeviceParams::create()
+FlashDeviceParams::create() const
{
- return new FlashDevice(this);
+ return new FlashDevice(*this);
}
* Flash Device constructor and destructor
*/
-FlashDevice::FlashDevice(const FlashDeviceParams* p):
+FlashDevice::FlashDevice(const FlashDeviceParams &p):
AbstractNVM(p),
diskSize(0),
- blockSize(p->blk_size),
- pageSize(p->page_size),
- GCActivePercentage(p->GC_active),
- readLatency(p->read_lat),
- writeLatency(p->write_lat),
- eraseLatency(p->erase_lat),
- dataDistribution(p->data_distribution),
- numPlanes(p->num_planes),
+ blockSize(p.blk_size),
+ pageSize(p.page_size),
+ GCActivePercentage(p.GC_active),
+ readLatency(p.read_lat),
+ writeLatency(p.write_lat),
+ eraseLatency(p.erase_lat),
+ dataDistribution(p.data_distribution),
+ numPlanes(p.num_planes),
pagesPerBlock(0),
pagesPerDisk(0),
blocksPerDisk(0),
public:
/** Initialize functions*/
- FlashDevice(const FlashDeviceParams*);
+ FlashDevice(const FlashDeviceParams &);
~FlashDevice();
/** Checkpoint functions*/
#include "params/FVPBasePwrCtrl.hh"
#include "sim/system.hh"
-FVPBasePwrCtrl::FVPBasePwrCtrl(FVPBasePwrCtrlParams *const params)
+FVPBasePwrCtrl::FVPBasePwrCtrl(const FVPBasePwrCtrlParams ¶ms)
: BasicPioDevice(params, 0x1000),
regs(),
system(*static_cast<ArmSystem *>(sys))
}
FVPBasePwrCtrl *
-FVPBasePwrCtrlParams::create()
+FVPBasePwrCtrlParams::create() const
{
- return new FVPBasePwrCtrl(this);
+ return new FVPBasePwrCtrl(*this);
}
class FVPBasePwrCtrl : public BasicPioDevice
{
public:
- FVPBasePwrCtrl(FVPBasePwrCtrlParams *const params);
+ FVPBasePwrCtrl(const FVPBasePwrCtrlParams ¶ms);
/**
* Triggered by the ISA when a WFI instruction is executed and (1) there
using namespace ArmISA;
-SystemCounter::SystemCounter(SystemCounterParams *const p)
+SystemCounter::SystemCounter(const SystemCounterParams &p)
: SimObject(p),
_enabled(true),
_value(0),
_increment(1),
- _freqTable(p->freqs),
+ _freqTable(p.freqs),
_activeFreqEntry(0),
_updateTick(0),
_freqUpdateEvent([this]{ freqUpdateCallback(); }, name()),
updateCounter();
}
-GenericTimer::GenericTimer(GenericTimerParams *const p)
+GenericTimer::GenericTimer(const GenericTimerParams &p)
: SimObject(p),
- systemCounter(*p->counter),
- system(*p->system)
+ systemCounter(*p.counter),
+ system(*p.system)
{
- SystemCounter::validateCounterRef(p->counter);
- fatal_if(!p->system, "GenericTimer::GenericTimer: No system specified, "
+ SystemCounter::validateCounterRef(p.counter);
+ fatal_if(!p.system, "GenericTimer::GenericTimer: No system specified, "
"can't instantiate architected timers\n");
system.setGenericTimer(this);
}
-const GenericTimerParams *
+const GenericTimerParams &
GenericTimer::params() const
{
- return dynamic_cast<const GenericTimerParams *>(_params);
+ return dynamic_cast<const GenericTimerParams &>(_params);
}
void
GenericTimer::createTimers(unsigned cpus)
{
assert(timers.size() < cpus);
- auto p = static_cast<const GenericTimerParams *>(_params);
+ auto &p = static_cast<const GenericTimerParams &>(_params);
const unsigned old_cpu_count(timers.size());
timers.resize(cpus);
timers[i].reset(
new CoreTimers(*this, system, i,
- p->int_phys_s->get(tc),
- p->int_phys_ns->get(tc),
- p->int_virt->get(tc),
- p->int_hyp->get(tc)));
+ p.int_phys_s->get(tc),
+ p.int_phys_ns->get(tc),
+ p.int_virt->get(tc),
+ p.int_hyp->get(tc)));
}
}
ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
: parent(_parent),
- cntfrq(parent.params()->cntfrq),
+ cntfrq(parent.params().cntfrq),
threadContext(system.threads[cpu]),
irqPhysS(_irqPhysS),
irqPhysNS(_irqPhysNS),
return value;
}
-GenericTimerFrame::GenericTimerFrame(GenericTimerFrameParams *const p)
+GenericTimerFrame::GenericTimerFrame(const GenericTimerFrameParams &p)
: PioDevice(p),
- timerRange(RangeSize(p->cnt_base, ArmSystem::PageBytes)),
+ timerRange(RangeSize(p.cnt_base, ArmSystem::PageBytes)),
addrRanges({timerRange}),
- systemCounter(*p->counter),
+ systemCounter(*p.counter),
physTimer(csprintf("%s.phys_timer", name()),
- *this, systemCounter, p->int_phys->get()),
+ *this, systemCounter, p.int_phys->get()),
virtTimer(csprintf("%s.virt_timer", name()),
*this, systemCounter,
- p->int_virt->get()),
+ p.int_virt->get()),
accessBits(0x3f),
system(*dynamic_cast<ArmSystem *>(sys))
{
- SystemCounter::validateCounterRef(p->counter);
+ SystemCounter::validateCounterRef(p.counter);
// Expose optional CNTEL0Base register frame
- if (p->cnt_el0_base != MaxAddr) {
- timerEl0Range = RangeSize(p->cnt_el0_base, ArmSystem::PageBytes);
+ if (p.cnt_el0_base != MaxAddr) {
+ timerEl0Range = RangeSize(p.cnt_el0_base, ArmSystem::PageBytes);
accessBitsEl0 = 0x303;
addrRanges.push_back(timerEl0Range);
}
}
}
-GenericTimerMem::GenericTimerMem(GenericTimerMemParams *const p)
+GenericTimerMem::GenericTimerMem(const GenericTimerMemParams &p)
: PioDevice(p),
- counterCtrlRange(RangeSize(p->cnt_control_base, ArmSystem::PageBytes)),
- counterStatusRange(RangeSize(p->cnt_read_base, ArmSystem::PageBytes)),
- timerCtrlRange(RangeSize(p->cnt_ctl_base, ArmSystem::PageBytes)),
+ counterCtrlRange(RangeSize(p.cnt_control_base, ArmSystem::PageBytes)),
+ counterStatusRange(RangeSize(p.cnt_read_base, ArmSystem::PageBytes)),
+ timerCtrlRange(RangeSize(p.cnt_ctl_base, ArmSystem::PageBytes)),
cnttidr(0x0),
addrRanges{counterCtrlRange, counterStatusRange, timerCtrlRange},
- systemCounter(*p->counter),
- frames(p->frames),
+ systemCounter(*p.counter),
+ frames(p.frames),
system(*dynamic_cast<ArmSystem *>(sys))
{
- SystemCounter::validateCounterRef(p->counter);
+ SystemCounter::validateCounterRef(p.counter);
for (auto &range : addrRanges)
GenericTimerMem::validateFrameRange(range);
fatal_if(frames.size() > MAX_TIMER_FRAMES,
}
SystemCounter *
-SystemCounterParams::create()
+SystemCounterParams::create() const
{
- return new SystemCounter(this);
+ return new SystemCounter(*this);
}
GenericTimer *
-GenericTimerParams::create()
+GenericTimerParams::create() const
{
- return new GenericTimer(this);
+ return new GenericTimer(*this);
}
GenericTimerFrame *
-GenericTimerFrameParams::create()
+GenericTimerFrameParams::create() const
{
- return new GenericTimerFrame(this);
+ return new GenericTimerFrame(*this);
}
GenericTimerMem *
-GenericTimerMemParams::create()
+GenericTimerMemParams::create() const
{
- return new GenericTimerMem(this);
+ return new GenericTimerMem(*this);
}
static constexpr size_t MAX_FREQ_ENTRIES = 1004;
public:
- SystemCounter(SystemCounterParams *const p);
+ SystemCounter(const SystemCounterParams &p);
/// Validates a System Counter reference
/// @param sys_cnt System counter reference to validate
class GenericTimer : public SimObject
{
public:
- const GenericTimerParams * params() const;
+ const GenericTimerParams ¶ms() const;
- GenericTimer(GenericTimerParams *const p);
+ GenericTimer(const GenericTimerParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
class GenericTimerFrame : public PioDevice
{
public:
- GenericTimerFrame(GenericTimerFrameParams *const p);
+ GenericTimerFrame(const GenericTimerFrameParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
class GenericTimerMem : public PioDevice
{
public:
- GenericTimerMem(GenericTimerMemParams *const p);
+ GenericTimerMem(const GenericTimerMemParams &p);
/// Validates a Generic Timer register frame address range
/// @param base_addr Range of the register frame
const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xc00);
const AddrRange GicV2::GICD_ICFGR (0xc00, 0xd00);
-GicV2::GicV2(const Params *p)
+GicV2::GicV2(const Params &p)
: BaseGic(p),
- gicdPIDR(p->gicd_pidr),
- gicdIIDR(p->gicd_iidr),
- giccIIDR(p->gicc_iidr),
- distRange(RangeSize(p->dist_addr, DIST_SIZE)),
- cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
+ gicdPIDR(p.gicd_pidr),
+ gicdIIDR(p.gicd_iidr),
+ giccIIDR(p.gicc_iidr),
+ distRange(RangeSize(p.dist_addr, DIST_SIZE)),
+ cpuRange(RangeSize(p.cpu_addr, p.cpu_size)),
addrRanges{distRange, cpuRange},
- distPioDelay(p->dist_pio_delay),
- cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
- enabled(false), haveGem5Extensions(p->gem5_extensions),
- itLines(p->it_lines),
+ distPioDelay(p.dist_pio_delay),
+ cpuPioDelay(p.cpu_pio_delay), intLatency(p.int_latency),
+ enabled(false), haveGem5Extensions(p.gem5_extensions),
+ itLines(p.it_lines),
intEnabled {}, pendingInt {}, activeInt {},
intPriority {}, intConfig {}, cpuTarget {},
cpuSgiPending {}, cpuSgiActive {},
}
GicV2 *
-GicV2Params::create()
+GicV2Params::create() const
{
- return new GicV2(this);
+ return new GicV2(*this);
}
public:
typedef GicV2Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- GicV2(const Params *p);
+ GicV2(const Params &p);
~GicV2();
DrainState drain() override;
#include "mem/packet_access.hh"
Gicv2m *
-Gicv2mParams::create()
+Gicv2mParams::create() const
{
- return new Gicv2m(this);
+ return new Gicv2m(*this);
}
Gicv2mFrame *
-Gicv2mFrameParams::create()
+Gicv2mFrameParams::create() const
{
- return new Gicv2mFrame(this);
+ return new Gicv2mFrame(*this);
}
-Gicv2m::Gicv2m(const Params *p)
- : PioDevice(p), pioDelay(p->pio_delay), frames(p->frames), gic(p->gic)
+Gicv2m::Gicv2m(const Params &p)
+ : PioDevice(p), pioDelay(p.pio_delay), frames(p.frames), gic(p.gic)
{
// Assert SPI ranges start at 32
for (int i = 0; i < frames.size(); i++) {
const unsigned int spi_len;
typedef Gicv2mFrameParams Params;
- Gicv2mFrame(const Params *p) :
- SimObject(p), addr(p->addr), spi_base(p->spi_base), spi_len(p->spi_len)
+ Gicv2mFrame(const Params &p) :
+ SimObject(p), addr(p.addr), spi_base(p.spi_base), spi_len(p.spi_len)
{}
};
public:
typedef Gicv2mParams Params;
- Gicv2m(const Params *p);
+ Gicv2m(const Params &p);
/** @{ */
/** Return the address ranges used by the Gicv2m
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-Gicv3::Gicv3(const Params * p)
+Gicv3::Gicv3(const Params &p)
: BaseGic(p)
{
}
void
Gicv3::init()
{
- distributor = new Gicv3Distributor(this, params()->it_lines);
+ distributor = new Gicv3Distributor(this, params().it_lines);
int threads = sys->threads.size();
redistributors.resize(threads, nullptr);
cpuInterfaces.resize(threads, nullptr);
- panic_if(threads > params()->cpu_max,
+ panic_if(threads > params().cpu_max,
"Exceeding maximum number of PEs supported by GICv3: "
- "using %u while maximum is %u.", threads, params()->cpu_max);
+ "using %u while maximum is %u.", threads, params().cpu_max);
for (int i = 0; i < threads; i++) {
redistributors[i] = new Gicv3Redistributor(this, i);
cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
}
- distRange = RangeSize(params()->dist_addr,
+ distRange = RangeSize(params().dist_addr,
Gicv3Distributor::ADDR_RANGE_SIZE - 1);
redistSize = redistributors[0]->addrRangeSize;
- redistRange = RangeSize(params()->redist_addr, redistSize * threads - 1);
+ redistRange = RangeSize(params().redist_addr, redistSize * threads - 1);
addrRanges = {distRange, redistRange};
cpuInterfaces[i]->init();
}
- Gicv3Its *its = params()->its;
+ Gicv3Its *its = params().its;
if (its)
its->setGIC(this);
const Addr daddr = addr - distRange.start();
panic_if(!distributor, "Distributor is null!");
resp = distributor->read(daddr, size, is_secure_access);
- delay = params()->dist_pio_delay;
+ delay = params().dist_pio_delay;
DPRINTF(GIC, "Gicv3::read(): (distributor) context_id %d register %#x "
"size %d is_secure_access %d (value %#x)\n",
pkt->req->contextId(), daddr, size, is_secure_access, resp);
Gicv3Redistributor *redist = getRedistributorByAddr(addr);
resp = redist->read(daddr, size, is_secure_access);
- delay = params()->redist_pio_delay;
+ delay = params().redist_pio_delay;
DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
"register %#x size %d is_secure_access %d (value %#x)\n",
redist->processorNumber(), pkt->req->contextId(), daddr, size,
"register %#x size %d is_secure_access %d value %#x\n",
pkt->req->contextId(), daddr, size, is_secure_access, data);
distributor->write(daddr, data, size, is_secure_access);
- delay = params()->dist_pio_delay;
+ delay = params().dist_pio_delay;
} else if (redistRange.contains(addr)) {
Addr daddr = (addr - redistRange.start()) % redistSize;
redist->write(daddr, data, size, is_secure_access);
- delay = params()->redist_pio_delay;
+ delay = params().redist_pio_delay;
} else {
panic("Gicv3::write(): unknown address %#x\n", addr);
}
Gicv3::supportsVersion(GicVersion version)
{
return (version == GicVersion::GIC_V3) ||
- (version == GicVersion::GIC_V4 && params()->gicv4);
+ (version == GicVersion::GIC_V4 && params().gicv4);
}
void
}
Gicv3 *
-Gicv3Params::create()
+Gicv3Params::create() const
{
- return new Gicv3(this);
+ return new Gicv3(*this);
}
void init() override;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Tick read(PacketPtr pkt) override;
public:
- Gicv3(const Params * p);
+ Gicv3(const Params &p);
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
void deassertAll(uint32_t cpu);
bool haveAsserted(uint32_t cpu) const;
void
Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
{
- maintenanceInterrupt = gic->params()->maint_int->get(tc);
+ maintenanceInterrupt = gic->params().maint_int->get(tc);
fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
"Invalid maintenance interrupt number\n");
}
panic("ITS %s command unimplemented", __func__);
}
-Gicv3Its::Gicv3Its(const Gicv3ItsParams *params)
- : BasicPioDevice(params, params->pio_size),
+Gicv3Its::Gicv3Its(const Gicv3ItsParams ¶ms)
+ : BasicPioDevice(params, params.pio_size),
dmaPort(name() + ".dma", *this),
gitsControl(CTLR_QUIESCENT),
- gitsTyper(params->gits_typer),
+ gitsTyper(params.gits_typer),
gitsCbaser(0), gitsCreadr(0),
gitsCwriter(0), gitsIidr(0),
tableBases(NUM_BASER_REGS, 0),
- requestorId(params->system->getRequestorId(this)),
+ requestorId(params.system->getRequestorId(this)),
gic(nullptr),
commandEvent([this] { checkCommandQueue(); }, name()),
pendingCommands(false),
}
Gicv3Its *
-Gicv3ItsParams::create()
+Gicv3ItsParams::create() const
{
- return new Gicv3Its(this);
+ return new Gicv3Its(*this);
}
bool recvTimingResp(PacketPtr pkt);
void recvReqRetry();
- Gicv3Its(const Gicv3ItsParams *params);
+ Gicv3Its(const Gicv3ItsParams ¶ms);
void setGIC(Gicv3 *_gic);
lpiConfigurationTablePtr(0),
lpiIDBits(0),
lpiPendingTablePtr(0),
- addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000)
+ addrRangeSize(gic->params().gicv4 ? 0x40000 : 0x20000)
{
}
{ Enums::T760, NOMALI_GPU_T760 },
};
-NoMaliGpu::NoMaliGpu(const NoMaliGpuParams *p)
+NoMaliGpu::NoMaliGpu(const NoMaliGpuParams &p)
: PioDevice(p),
- pioAddr(p->pio_addr),
- platform(p->platform),
+ pioAddr(p.pio_addr),
+ platform(p.platform),
interruptMap{
- { NOMALI_INT_GPU, p->int_gpu },
- { NOMALI_INT_JOB, p->int_job },
- { NOMALI_INT_MMU, p->int_mmu },
+ { NOMALI_INT_GPU, p.int_gpu },
+ { NOMALI_INT_JOB, p.int_job },
+ { NOMALI_INT_MMU, p.int_mmu },
}
{
if (nomali_api_version() != NOMALI_API_VERSION)
nomali_config_t cfg;
memset(&cfg, 0, sizeof(cfg));
- const auto it_gpu(gpuTypeMap.find(p->gpu_type));
+ const auto it_gpu(gpuTypeMap.find(p.gpu_type));
if (it_gpu == gpuTypeMap.end()) {
fatal("Unrecognized GPU type: %s (%i)\n",
- Enums::NoMaliGpuTypeStrings[p->gpu_type], p->gpu_type);
+ Enums::NoMaliGpuTypeStrings[p.gpu_type], p.gpu_type);
}
cfg.type = it_gpu->second;
- cfg.ver_maj = p->ver_maj;
- cfg.ver_min = p->ver_min;
- cfg.ver_status = p->ver_status;
+ cfg.ver_maj = p.ver_maj;
+ cfg.ver_min = p.ver_min;
+ cfg.ver_status = p.ver_status;
panicOnErr(
nomali_create(&nomali, &cfg),
}
-CustomNoMaliGpu::CustomNoMaliGpu(const CustomNoMaliGpuParams *p)
+CustomNoMaliGpu::CustomNoMaliGpu(const CustomNoMaliGpuParams &p)
: NoMaliGpu(p),
idRegs{
- { GPU_CONTROL_REG(GPU_ID), p->gpu_id },
- { GPU_CONTROL_REG(L2_FEATURES), p->l2_features },
- { GPU_CONTROL_REG(TILER_FEATURES), p->tiler_features },
- { GPU_CONTROL_REG(MEM_FEATURES), p->mem_features },
- { GPU_CONTROL_REG(MMU_FEATURES), p->mmu_features },
- { GPU_CONTROL_REG(AS_PRESENT), p->as_present },
- { GPU_CONTROL_REG(JS_PRESENT), p->js_present },
-
- { GPU_CONTROL_REG(THREAD_MAX_THREADS), p->thread_max_threads },
+ { GPU_CONTROL_REG(GPU_ID), p.gpu_id },
+ { GPU_CONTROL_REG(L2_FEATURES), p.l2_features },
+ { GPU_CONTROL_REG(TILER_FEATURES), p.tiler_features },
+ { GPU_CONTROL_REG(MEM_FEATURES), p.mem_features },
+ { GPU_CONTROL_REG(MMU_FEATURES), p.mmu_features },
+ { GPU_CONTROL_REG(AS_PRESENT), p.as_present },
+ { GPU_CONTROL_REG(JS_PRESENT), p.js_present },
+
+ { GPU_CONTROL_REG(THREAD_MAX_THREADS), p.thread_max_threads },
{ GPU_CONTROL_REG(THREAD_MAX_WORKGROUP_SIZE),
- p->thread_max_workgroup_size },
+ p.thread_max_workgroup_size },
{ GPU_CONTROL_REG(THREAD_MAX_BARRIER_SIZE),
- p->thread_max_barrier_size },
- { GPU_CONTROL_REG(THREAD_FEATURES), p->thread_features },
-
- { GPU_CONTROL_REG(SHADER_PRESENT_LO), bits(p->shader_present, 31, 0) },
- { GPU_CONTROL_REG(SHADER_PRESENT_HI), bits(p->shader_present, 63, 32) },
- { GPU_CONTROL_REG(TILER_PRESENT_LO), bits(p->tiler_present, 31, 0) },
- { GPU_CONTROL_REG(TILER_PRESENT_HI), bits(p->tiler_present, 63, 32) },
- { GPU_CONTROL_REG(L2_PRESENT_LO), bits(p->l2_present, 31, 0) },
- { GPU_CONTROL_REG(L2_PRESENT_HI), bits(p->l2_present, 63, 32) },
+ p.thread_max_barrier_size },
+ { GPU_CONTROL_REG(THREAD_FEATURES), p.thread_features },
+
+ { GPU_CONTROL_REG(SHADER_PRESENT_LO), bits(p.shader_present, 31, 0) },
+ { GPU_CONTROL_REG(SHADER_PRESENT_HI), bits(p.shader_present, 63, 32) },
+ { GPU_CONTROL_REG(TILER_PRESENT_LO), bits(p.tiler_present, 31, 0) },
+ { GPU_CONTROL_REG(TILER_PRESENT_HI), bits(p.tiler_present, 63, 32) },
+ { GPU_CONTROL_REG(L2_PRESENT_LO), bits(p.l2_present, 31, 0) },
+ { GPU_CONTROL_REG(L2_PRESENT_HI), bits(p.l2_present, 63, 32) },
}
{
- fatal_if(p->texture_features.size() > 3,
+ fatal_if(p.texture_features.size() > 3,
"Too many texture feature registers specified (%i)\n",
- p->texture_features.size());
+ p.texture_features.size());
- fatal_if(p->js_features.size() > 16,
+ fatal_if(p.js_features.size() > 16,
"Too many job slot feature registers specified (%i)\n",
- p->js_features.size());
+ p.js_features.size());
- for (int i = 0; i < p->texture_features.size(); i++)
- idRegs[TEXTURE_FEATURES_REG(i)] = p->texture_features[i];
+ for (int i = 0; i < p.texture_features.size(); i++)
+ idRegs[TEXTURE_FEATURES_REG(i)] = p.texture_features[i];
- for (int i = 0; i < p->js_features.size(); i++)
- idRegs[JS_FEATURES_REG(i)] = p->js_features[i];
+ for (int i = 0; i < p.js_features.size(); i++)
+ idRegs[JS_FEATURES_REG(i)] = p.js_features[i];
}
CustomNoMaliGpu::~CustomNoMaliGpu()
NoMaliGpu *
-NoMaliGpuParams::create()
+NoMaliGpuParams::create() const
{
- return new NoMaliGpu(this);
+ return new NoMaliGpu(*this);
}
CustomNoMaliGpu *
-CustomNoMaliGpuParams::create()
+CustomNoMaliGpuParams::create() const
{
- return new CustomNoMaliGpu(this);
+ return new CustomNoMaliGpu(*this);
}
class NoMaliGpu : public PioDevice
{
public:
- NoMaliGpu(const NoMaliGpuParams *p);
+ NoMaliGpu(const NoMaliGpuParams &p);
virtual ~NoMaliGpu();
void init() override;
class CustomNoMaliGpu : public NoMaliGpu
{
public:
- CustomNoMaliGpu(const CustomNoMaliGpuParams *p);
+ CustomNoMaliGpu(const CustomNoMaliGpuParams &p);
virtual ~CustomNoMaliGpu();
protected:
// initialize hdlcd registers
-HDLcd::HDLcd(const HDLcdParams *p)
+HDLcd::HDLcd(const HDLcdParams &p)
: AmbaDmaDevice(p, 0xFFFF),
// Parameters
- vnc(p->vnc),
- workaroundSwapRB(p->workaround_swap_rb),
- workaroundDmaLineCount(p->workaround_dma_line_count),
+ vnc(p.vnc),
+ workaroundSwapRB(p.workaround_swap_rb),
+ workaroundDmaLineCount(p.workaround_dma_line_count),
addrRanges{RangeSize(pioAddr, pioSize)},
- enableCapture(p->enable_capture),
- pixelBufferSize(p->pixel_buffer_size),
- virtRefreshRate(p->virt_refresh_rate),
+ enableCapture(p.enable_capture),
+ pixelBufferSize(p.pixel_buffer_size),
+ virtRefreshRate(p.virt_refresh_rate),
// Registers
version(VERSION_RESETV),
virtRefreshEvent([this]{ virtRefresh(); }, name()),
// Other
- imgFormat(p->frame_format), pic(NULL), conv(PixelConverter::rgba8888_le),
- pixelPump(*this, *p->pxl_clk, p->pixel_chunk)
+ imgFormat(p.frame_format), pic(NULL), conv(PixelConverter::rgba8888_le),
+ pixelPump(*this, *p.pxl_clk, p.pixel_chunk)
{
if (vnc)
vnc->setFrameBuffer(&pixelPump.fb);
HDLcd *
-HDLcdParams::create()
+HDLcdParams::create() const
{
- return new HDLcd(this);
+ return new HDLcd(*this);
}
class HDLcd: public AmbaDmaDevice
{
public:
- HDLcd(const HDLcdParams *p);
+ HDLcd(const HDLcdParams &p);
~HDLcd();
void regStats() override;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-Pl050::Pl050(const Pl050Params *p)
+Pl050::Pl050(const Pl050Params &p)
: AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
rawInterrupts(0),
- ps2(p->ps2)
+ ps2(p.ps2)
{
ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
}
}
Pl050 *
-Pl050Params::create()
+Pl050Params::create() const
{
- return new Pl050(this);
+ return new Pl050(*this);
}
PS2Device *ps2;
public:
- Pl050(const Pl050Params *p);
+ Pl050(const Pl050Params &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
#include "params/GenericArmPciHost.hh"
-GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams *p)
+GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams &p)
: GenericPciHost(p),
- intPolicy(p->int_policy), intBase(p->int_base),
- intCount(p->int_count)
+ intPolicy(p.int_policy), intBase(p.int_base),
+ intCount(p.int_count)
{
}
GenericArmPciHost *
-GenericArmPciHostParams::create()
+GenericArmPciHostParams::create() const
{
- return new GenericArmPciHost(this);
+ return new GenericArmPciHost(*this);
}
: public GenericPciHost
{
public:
- GenericArmPciHost(const GenericArmPciHostParams *p);
+ GenericArmPciHost(const GenericArmPciHostParams &p);
virtual ~GenericArmPciHost() {}
protected:
#include "params/Pl011.hh"
#include "sim/sim_exit.hh"
-Pl011::Pl011(const Pl011Params *p)
+Pl011::Pl011(const Pl011Params &p)
: Uart(p, 0x1000),
intEvent([this]{ generateInterrupt(); }, name()),
control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
imsc(0), rawInt(0),
- endOnEOT(p->end_on_eot), interrupt(p->interrupt->get()),
- intDelay(p->int_delay)
+ endOnEOT(p.end_on_eot), interrupt(p.interrupt->get()),
+ intDelay(p.int_delay)
{
}
}
Pl011 *
-Pl011Params::create()
+Pl011Params::create() const
{
- return new Pl011(this);
+ return new Pl011(*this);
}
class Pl011 : public Uart, public AmbaDevice
{
public:
- Pl011(const Pl011Params *p);
+ Pl011(const Pl011Params &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
using std::vector;
// initialize clcd registers
-Pl111::Pl111(const Params *p)
+Pl111::Pl111(const Params &p)
: AmbaDmaDevice(p), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0),
lcdRis(0), lcdMis(0),
clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
- pixelClock(p->pixel_clock),
+ pixelClock(p.pixel_clock),
converter(PixelConverter::rgba8888_le), fb(LcdMaxWidth, LcdMaxHeight),
- vnc(p->vnc), bmp(&fb), pic(NULL),
+ vnc(p.vnc), bmp(&fb), pic(NULL),
width(LcdMaxWidth), height(LcdMaxHeight),
bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
waterMark(0), dmaPendingNum(0),
dmaDoneEventAll(maxOutstandingDma, this),
dmaDoneEventFree(maxOutstandingDma),
intEvent([this]{ generateInterrupt(); }, name()),
- enableCapture(p->enable_capture)
+ enableCapture(p.enable_capture)
{
pioSize = 0xFFFF;
}
Pl111 *
-Pl111Params::create()
+Pl111Params::create() const
{
- return new Pl111(this);
+ return new Pl111(*this);
}
public:
typedef Pl111Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Pl111(const Params *p);
+ Pl111(const Params &p);
~Pl111();
Tick read(PacketPtr pkt) override;
#include "sim/system.hh"
-RealView::RealView(const Params *p)
- : Platform(p), system(p->system), gic(nullptr)
+RealView::RealView(const Params &p)
+ : Platform(p), system(p.system), gic(nullptr)
{}
void
}
RealView *
-RealViewParams::create()
+RealViewParams::create() const
{
- return new RealView(this);
+ return new RealView(*this);
}
public:
typedef RealViewParams Params;
- const Params *
+ const Params &
params() const {
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
- RealView(const Params *p);
+ RealView(const Params &p);
/** Give platform a pointer to interrupt controller */
void setGic(BaseGic *_gic) { gic = _gic; }
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-PL031::PL031(Params *p)
- : AmbaIntDevice(p, 0x1000), timeVal(mkutctime(&p->time)),
- lastWrittenTick(0), loadVal(0), matchVal(0),
+PL031::PL031(const Params &p)
+ : AmbaIntDevice(p, 0x1000), lastWrittenTick(0), loadVal(0), matchVal(0),
rawInt(false), maskInt(false), pendingInt(false),
matchEvent([this]{ counterMatch(); }, name())
{
+ // Make a temporary copy so mkutctime can modify it.
+ struct tm local_time = p.time;
+ timeVal = mkutctime(&local_time);
}
PL031 *
-PL031Params::create()
+PL031Params::create() const
{
- return new PL031(this);
+ return new PL031(*this);
}
public:
typedef PL031Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- PL031(Params *p);
+ PL031(const Params &p);
/**
* Handle a read to the device
#include "sim/system.hh"
#include "sim/voltage_domain.hh"
-RealViewCtrl::RealViewCtrl(Params *p)
+RealViewCtrl::RealViewCtrl(const Params &p)
: BasicPioDevice(p, 0xD4), flags(0), scData(0)
{
}
switch(daddr) {
case ProcId0:
- pkt->setLE(params()->proc_id0);
+ pkt->setLE(params().proc_id0);
break;
case ProcId1:
- pkt->setLE(params()->proc_id1);
+ pkt->setLE(params().proc_id1);
break;
case Clock24:
Tick clk;
pkt->setLE<uint32_t>(flags);
break;
case IdReg:
- pkt->setLE<uint32_t>(params()->idreg);
+ pkt->setLE<uint32_t>(params().idreg);
break;
case CfgStat:
pkt->setLE<uint32_t>(1);
}
-RealViewOsc::RealViewOsc(RealViewOscParams *p)
- : ClockDomain(p, p->voltage_domain),
- RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_OSC,
- p->site, p->position, p->dcc, p->device)
+RealViewOsc::RealViewOsc(const RealViewOscParams &p)
+ : ClockDomain(p, p.voltage_domain),
+ RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
+ p.site, p.position, p.dcc, p.device)
{
- if (SimClock::Float::s / p->freq > UINT32_MAX) {
+ if (SimClock::Float::s / p.freq > UINT32_MAX) {
fatal("Oscillator frequency out of range: %f\n",
- SimClock::Float::s / p->freq / 1E6);
+ SimClock::Float::s / p.freq / 1E6);
}
- _clockPeriod = p->freq;
+ _clockPeriod = p.freq;
}
void
}
RealViewCtrl *
-RealViewCtrlParams::create()
+RealViewCtrlParams::create() const
{
- return new RealViewCtrl(this);
+ return new RealViewCtrl(*this);
}
RealViewOsc *
-RealViewOscParams::create()
+RealViewOscParams::create() const
{
- return new RealViewOsc(this);
+ return new RealViewOsc(*this);
}
RealViewTemperatureSensor *
-RealViewTemperatureSensorParams::create()
+RealViewTemperatureSensorParams::create() const
{
- return new RealViewTemperatureSensor(this);
+ return new RealViewTemperatureSensor(*this);
}
public:
typedef RealViewCtrlParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- RealViewCtrl(Params *p);
+ RealViewCtrl(const Params &p);
/**
* Handle a read to the device
: public ClockDomain, RealViewCtrl::Device
{
public:
- RealViewOsc(RealViewOscParams *p);
+ RealViewOsc(const RealViewOscParams &p);
virtual ~RealViewOsc() {};
void startup() override;
: public SimObject, RealViewCtrl::Device
{
public:
- RealViewTemperatureSensor(RealViewTemperatureSensorParams *p)
+ RealViewTemperatureSensor(const RealViewTemperatureSensorParams &p)
: SimObject(p),
- RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_TEMP,
- p->site, p->position, p->dcc, p->device),
- system(p->system)
+ RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_TEMP,
+ p.site, p.position, p.dcc, p.device),
+ system(p.system)
{}
virtual ~RealViewTemperatureSensor() {};
#include "mem/packet_access.hh"
#include "sim/system.hh"
-SMMUv3::SMMUv3(SMMUv3Params *params) :
+SMMUv3::SMMUv3(const SMMUv3Params ¶ms) :
ClockedObject(params),
- system(*params->system),
- requestorId(params->system->getRequestorId(this)),
+ system(*params.system),
+ requestorId(params.system->getRequestorId(this)),
requestPort(name() + ".request", *this),
tableWalkPort(name() + ".walker", *this),
- controlPort(name() + ".control", *this, params->reg_map),
- tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy),
- configCache(params->cfg_entries, params->cfg_assoc, params->cfg_policy),
- ipaCache(params->ipa_entries, params->ipa_assoc, params->ipa_policy),
- walkCache({ { params->walk_S1L0, params->walk_S1L1,
- params->walk_S1L2, params->walk_S1L3,
- params->walk_S2L0, params->walk_S2L1,
- params->walk_S2L2, params->walk_S2L3 } },
- params->walk_assoc, params->walk_policy),
- tlbEnable(params->tlb_enable),
- configCacheEnable(params->cfg_enable),
- ipaCacheEnable(params->ipa_enable),
- walkCacheEnable(params->walk_enable),
+ controlPort(name() + ".control", *this, params.reg_map),
+ tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy),
+ configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy),
+ ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy),
+ walkCache({ { params.walk_S1L0, params.walk_S1L1,
+ params.walk_S1L2, params.walk_S1L3,
+ params.walk_S2L0, params.walk_S2L1,
+ params.walk_S2L2, params.walk_S2L3 } },
+ params.walk_assoc, params.walk_policy),
+ tlbEnable(params.tlb_enable),
+ configCacheEnable(params.cfg_enable),
+ ipaCacheEnable(params.ipa_enable),
+ walkCacheEnable(params.walk_enable),
tableWalkPortEnable(false),
- walkCacheNonfinalEnable(params->wc_nonfinal_enable),
- walkCacheS1Levels(params->wc_s1_levels),
- walkCacheS2Levels(params->wc_s2_levels),
- requestPortWidth(params->request_port_width),
- tlbSem(params->tlb_slots),
+ walkCacheNonfinalEnable(params.wc_nonfinal_enable),
+ walkCacheS1Levels(params.wc_s1_levels),
+ walkCacheS2Levels(params.wc_s2_levels),
+ requestPortWidth(params.request_port_width),
+ tlbSem(params.tlb_slots),
ifcSmmuSem(1),
smmuIfcSem(1),
- configSem(params->cfg_slots),
- ipaSem(params->ipa_slots),
- walkSem(params->walk_slots),
+ configSem(params.cfg_slots),
+ ipaSem(params.ipa_slots),
+ walkSem(params.walk_slots),
requestPortSem(1),
- transSem(params->xlate_slots),
- ptwSem(params->ptw_slots),
+ transSem(params.xlate_slots),
+ ptwSem(params.ptw_slots),
cycleSem(1),
- tlbLat(params->tlb_lat),
- ifcSmmuLat(params->ifc_smmu_lat),
- smmuIfcLat(params->smmu_ifc_lat),
- configLat(params->cfg_lat),
- ipaLat(params->ipa_lat),
- walkLat(params->walk_lat),
- deviceInterfaces(params->device_interfaces),
+ tlbLat(params.tlb_lat),
+ ifcSmmuLat(params.ifc_smmu_lat),
+ smmuIfcLat(params.smmu_ifc_lat),
+ configLat(params.cfg_lat),
+ ipaLat(params.ipa_lat),
+ walkLat(params.walk_lat),
+ deviceInterfaces(params.device_interfaces),
commandExecutor(name() + ".cmd_exec", *this),
- regsMap(params->reg_map),
+ regsMap(params.reg_map),
processCommandsEvent(this)
{
fatal_if(regsMap.size() != SMMU_REG_SIZE,
memset(®s, 0, sizeof(regs));
// Setup RO ID registers
- regs.idr0 = params->smmu_idr0;
- regs.idr1 = params->smmu_idr1;
- regs.idr2 = params->smmu_idr2;
- regs.idr3 = params->smmu_idr3;
- regs.idr4 = params->smmu_idr4;
- regs.idr5 = params->smmu_idr5;
- regs.iidr = params->smmu_iidr;
- regs.aidr = params->smmu_aidr;
+ regs.idr0 = params.smmu_idr0;
+ regs.idr1 = params.smmu_idr1;
+ regs.idr2 = params.smmu_idr2;
+ regs.idr3 = params.smmu_idr3;
+ regs.idr4 = params.smmu_idr4;
+ regs.idr5 = params.smmu_idr5;
+ regs.iidr = params.smmu_iidr;
+ regs.aidr = params.smmu_aidr;
// TODO: At the moment it possible to set the ID registers to hold
// any possible value. It would be nice to have a sanity check here
}
SMMUv3*
-SMMUv3Params::create()
+SMMUv3Params::create() const
{
- return new SMMUv3(this);
+ return new SMMUv3(*this);
}
const PageTableOps *getPageTableOps(uint8_t trans_granule);
public:
- SMMUv3(SMMUv3Params *p);
+ SMMUv3(const SMMUv3Params &p);
virtual ~SMMUv3() {}
virtual void init() override;
#include "dev/arm/smmu_v3_transl.hh"
SMMUv3DeviceInterface::SMMUv3DeviceInterface(
- const SMMUv3DeviceInterfaceParams *p) :
+ const SMMUv3DeviceInterfaceParams &p) :
ClockedObject(p),
smmu(nullptr),
- microTLB(new SMMUTLB(p->utlb_entries,
- p->utlb_assoc,
- p->utlb_policy)),
- mainTLB(new SMMUTLB(p->tlb_entries,
- p->tlb_assoc,
- p->tlb_policy)),
- microTLBEnable(p->utlb_enable),
- mainTLBEnable(p->tlb_enable),
+ microTLB(new SMMUTLB(p.utlb_entries,
+ p.utlb_assoc,
+ p.utlb_policy)),
+ mainTLB(new SMMUTLB(p.tlb_entries,
+ p.tlb_assoc,
+ p.tlb_policy)),
+ microTLBEnable(p.utlb_enable),
+ mainTLBEnable(p.tlb_enable),
devicePortSem(1),
- microTLBSem(p->utlb_slots),
- mainTLBSem(p->tlb_slots),
- microTLBLat(p->utlb_lat),
- mainTLBLat(p->tlb_lat),
+ microTLBSem(p.utlb_slots),
+ mainTLBSem(p.tlb_slots),
+ microTLBLat(p.utlb_lat),
+ mainTLBLat(p.tlb_lat),
devicePort(new SMMUDevicePort(csprintf("%s.device_port",
name()), *this)),
atsDevicePort(name() + ".atsDevicePort", *this),
atsMemPort(name() + ".atsMemPort", *this),
- portWidth(p->port_width),
- wrBufSlotsRemaining(p->wrbuf_slots),
- xlateSlotsRemaining(p->xlate_slots),
+ portWidth(p.port_width),
+ wrBufSlotsRemaining(p.wrbuf_slots),
+ xlateSlotsRemaining(p.xlate_slots),
pendingMemAccesses(0),
- prefetchEnable(p->prefetch_enable),
+ prefetchEnable(p.prefetch_enable),
prefetchReserveLastWay(
- p->prefetch_reserve_last_way),
+ p.prefetch_reserve_last_way),
deviceNeedsRetry(false),
atsDeviceNeedsRetry(false),
sendDeviceRetryEvent(*this),
SMMUv3DeviceInterface::drain()
{
// Wait until all SMMU translations are completed
- if (xlateSlotsRemaining < params()->xlate_slots) {
+ if (xlateSlotsRemaining < params().xlate_slots) {
return DrainState::Draining;
}
return DrainState::Drained;
}
SMMUv3DeviceInterface*
-SMMUv3DeviceInterfaceParams::create()
+SMMUv3DeviceInterfaceParams::create() const
{
- return new SMMUv3DeviceInterface(this);
+ return new SMMUv3DeviceInterface(*this);
}
Port& getPort(const std::string &name, PortID id) override;
public:
- SMMUv3DeviceInterface(const SMMUv3DeviceInterfaceParams *p);
+ SMMUv3DeviceInterface(const SMMUv3DeviceInterfaceParams &p);
~SMMUv3DeviceInterface()
{
delete mainTLB;
}
- const SMMUv3DeviceInterfaceParams *
+ const SMMUv3DeviceInterfaceParams &
params() const
{
- return static_cast<const SMMUv3DeviceInterfaceParams *>(_params);
+ return static_cast<const SMMUv3DeviceInterfaceParams &>(_params);
}
DrainState drain() override;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-A9GlobalTimer::A9GlobalTimer(Params *p)
- : BasicPioDevice(p, 0x1C), gic(p->gic),
- global_timer(name() + ".globaltimer", this, p->int_num)
+A9GlobalTimer::A9GlobalTimer(const Params &p)
+ : BasicPioDevice(p, 0x1C), gic(p.gic),
+ global_timer(name() + ".globaltimer", this, p.int_num)
{
}
}
A9GlobalTimer *
-A9GlobalTimerParams::create()
+A9GlobalTimerParams::create() const
{
- return new A9GlobalTimer(this);
+ return new A9GlobalTimer(*this);
}
public:
typedef A9GlobalTimerParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- A9GlobalTimer(Params *p);
+ A9GlobalTimer(const Params &p);
/**
* Handle a read to the device
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-CpuLocalTimer::CpuLocalTimer(Params *p)
+CpuLocalTimer::CpuLocalTimer(const Params &p)
: BasicPioDevice(p, 0x38)
{
}
void
CpuLocalTimer::init()
{
- auto p = params();
+ const auto &p = params();
// Initialize the timer registers for each per cpu timer
for (int i = 0; i < sys->threads.size(); i++) {
ThreadContext* tc = sys->threads[i];
localTimer.emplace_back(
new Timer(oss.str(), this,
- p->int_timer->get(tc),
- p->int_watchdog->get(tc)));
+ p.int_timer->get(tc),
+ p.int_watchdog->get(tc)));
}
BasicPioDevice::init();
}
CpuLocalTimer *
-CpuLocalTimerParams::create()
+CpuLocalTimerParams::create() const
{
- return new CpuLocalTimer(this);
+ return new CpuLocalTimer(*this);
}
public:
typedef CpuLocalTimerParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- CpuLocalTimer(Params *p);
+ CpuLocalTimer(const Params &p);
/** Inits the local timers */
void init() override;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-Sp804::Sp804(Params *p)
+Sp804::Sp804(const Params &p)
: AmbaPioDevice(p, 0x1000),
- timer0(name() + ".timer0", this, p->int0->get(), p->clock0),
- timer1(name() + ".timer1", this, p->int1->get(), p->clock1)
+ timer0(name() + ".timer0", this, p.int0->get(), p.clock0),
+ timer1(name() + ".timer1", this, p.int1->get(), p.clock1)
{
}
}
Sp804 *
-Sp804Params::create()
+Sp804Params::create() const
{
- return new Sp804(this);
+ return new Sp804(*this);
}
public:
typedef Sp804Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
- Sp804(Params *p);
+ Sp804(const Params &p);
/**
* Handle a read to the device
/**
* Constructor and destructor functions of UFSHCM device
*/
-UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams* p,
+UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams &p,
uint32_t lun_id, const Callback &transfer_cb,
const Callback &read_cb):
SimObject(p),
- flashDisk(p->image[lun_id]),
- flashDevice(p->internalflash[lun_id]),
- blkSize(p->img_blk_size),
- lunAvail(p->image.size()),
+ flashDisk(p.image[lun_id]),
+ flashDevice(p.internalflash[lun_id]),
+ blkSize(p.img_blk_size),
+ lunAvail(p.image.size()),
diskSize(flashDisk->size()),
capacityLower((diskSize - 1) & 0xffffffff),
capacityUpper((diskSize - SectorSize) >> 32),
* Constructor for the UFS Host device
*/
-UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams* p) :
+UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams &p) :
DmaDevice(p),
- pioAddr(p->pio_addr),
+ pioAddr(p.pio_addr),
pioSize(0x0FFF),
- pioDelay(p->pio_latency),
- intNum(p->int_num),
- gic(p->gic),
- lunAvail(p->image.size()),
- UFSSlots(p->ufs_slots - 1),
+ pioDelay(p.pio_latency),
+ intNum(p.int_num),
+ gic(p.gic),
+ lunAvail(p.image.size()),
+ UFSSlots(p.ufs_slots - 1),
readPendingNum(0),
writePendingNum(0),
activeDoorbells(0),
*/
UFSHostDevice*
-UFSHostDeviceParams::create()
+UFSHostDeviceParams::create() const
{
- return new UFSHostDevice(this);
+ return new UFSHostDevice(*this);
}
{
public:
- UFSHostDevice(const UFSHostDeviceParams* p);
+ UFSHostDevice(const UFSHostDeviceParams &p);
DrainState drain() override;
void checkDrain();
/**
* Constructor and destructor
*/
- UFSSCSIDevice(const UFSHostDeviceParams* p, uint32_t lun_id,
+ UFSSCSIDevice(const UFSHostDeviceParams &p, uint32_t lun_id,
const Callback &transfer_cb, const Callback &read_cb);
~UFSSCSIDevice();
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-VGic::VGic(const Params *p)
- : PioDevice(p), gicvIIDR(p->gicv_iidr), platform(p->platform),
- gic(p->gic), vcpuAddr(p->vcpu_addr), hvAddr(p->hv_addr),
- pioDelay(p->pio_delay), maintInt(p->maint_int)
+VGic::VGic(const Params &p)
+ : PioDevice(p), gicvIIDR(p.gicv_iidr), platform(p.platform),
+ gic(p.gic), vcpuAddr(p.vcpu_addr), hvAddr(p.hv_addr),
+ pioDelay(p.pio_delay), maintInt(p.maint_int)
{
for (int x = 0; x < VGIC_CPU_MAX; x++) {
postVIntEvent[x] = new EventFunctionWrapper(
}
VGic *
-VGicParams::create()
+VGicParams::create() const
{
- return new VGic(this);
+ return new VGic(*this);
}
struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
public:
- typedef VGicParams Params;
- const Params *
+ typedef VGicParams Params;
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- VGic(const Params *p);
+ VGic(const Params &p);
~VGic();
AddrRangeList getAddrRanges() const override;
#include "mem/packet_access.hh"
#include "params/MmioVirtIO.hh"
-MmioVirtIO::MmioVirtIO(const MmioVirtIOParams *params)
- : BasicPioDevice(params, params->pio_size),
+MmioVirtIO::MmioVirtIO(const MmioVirtIOParams ¶ms)
+ : BasicPioDevice(params, params.pio_size),
hostFeaturesSelect(0), guestFeaturesSelect(0), pageSize(0),
- interruptStatus(0), vio(*params->vio),
- interrupt(params->interrupt->get())
+ interruptStatus(0), vio(*params.vio),
+ interrupt(params.interrupt->get())
{
fatal_if(!interrupt, "No MMIO VirtIO interrupt specified\n");
MmioVirtIO *
-MmioVirtIOParams::create()
+MmioVirtIOParams::create() const
{
- return new MmioVirtIO(this);
+ return new MmioVirtIO(*this);
}
class MmioVirtIO : public BasicPioDevice
{
public:
- MmioVirtIO(const MmioVirtIOParams *params);
+ MmioVirtIO(const MmioVirtIOParams ¶ms);
virtual ~MmioVirtIO();
protected: // BasicPioDevice
#include "mem/packet_access.hh"
#include "params/Sp805.hh"
-Sp805::Sp805(Sp805Params const* params)
+Sp805::Sp805(const Sp805Params ¶ms)
: AmbaIntDevice(params, 0x1000),
timeoutInterval(0xffffffff),
timeoutStartTick(MaxTick),
}
Sp805 *
-Sp805Params::create()
+Sp805Params::create() const
{
- return new Sp805(this);
+ return new Sp805(*this);
}
class Sp805 : public AmbaIntDevice
{
public:
- Sp805(Sp805Params const* params);
+ Sp805(const Sp805Params ¶ms);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
using namespace std;
-BadDevice::BadDevice(Params *p)
- : BasicPioDevice(p, 0x10), devname(p->devicename)
+BadDevice::BadDevice(const Params &p)
+ : BasicPioDevice(p, 0x10), devname(p.devicename)
{
}
}
BadDevice *
-BadDeviceParams::create()
+BadDeviceParams::create() const
{
- return new BadDevice(this);
+ return new BadDevice(*this);
}
typedef BadDeviceParams Params;
protected:
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
public:
* @param p object parameters
* @param a base address of the write
*/
- BadDevice(Params *p);
+ BadDevice(const Params &p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
return true;
}
-DmaDevice::DmaDevice(const Params *p)
- : PioDevice(p), dmaPort(this, sys, p->sid, p->ssid)
+DmaDevice::DmaDevice(const Params &p)
+ : PioDevice(p), dmaPort(this, sys, p.sid, p.ssid)
{ }
void
public:
typedef DmaDeviceParams Params;
- DmaDevice(const Params *p);
+ DmaDevice(const Params &p);
virtual ~DmaDevice() { }
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
public:
typedef HSADeviceParams Params;
- HSADevice(const Params *p) : DmaDevice(p), hsaPP(p->hsapp)
+ HSADevice(const Params &p) : DmaDevice(p), hsaPP(p.hsapp)
{
assert(hsaPP);
hsaPP->setDevice(this);
#include "sim/proxy_ptr.hh"
#include "sim/syscall_emul_buf.hh"
-HSADriver::HSADriver(HSADriverParams *p)
- : EmulatedDriver(p), device(p->device), queueId(0)
+HSADriver::HSADriver(const HSADriverParams &p)
+ : EmulatedDriver(p), device(p.device), queueId(0)
{
}
class HSADriver : public EmulatedDriver
{
public:
- HSADriver(HSADriverParams *p);
+ HSADriver(const HSADriverParams &p);
int open(ThreadContext *tc, int mode, int flags);
Addr mmap(ThreadContext *tc, Addr start, uint64_t length,
HSAPP_EVENT_DESCRIPTION_GENERATOR(QueueProcessEvent)
HSAPP_EVENT_DESCRIPTION_GENERATOR(DepSignalsReadDmaEvent)
-HSAPacketProcessor::HSAPacketProcessor(const Params *p)
- : DmaDevice(p), numHWQueues(p->numHWQueues), pioAddr(p->pioAddr),
- pioSize(PAGE_SIZE), pioDelay(10), pktProcessDelay(p->pktProcessDelay)
+HSAPacketProcessor::HSAPacketProcessor(const Params &p)
+ : DmaDevice(p), numHWQueues(p.numHWQueues), pioAddr(p.pioAddr),
+ pioSize(PAGE_SIZE), pioDelay(10), pktProcessDelay(p.pktProcessDelay)
{
DPRINTF(HSAPacketProcessor, "%s:\n", __FUNCTION__);
- hwSchdlr = new HWScheduler(this, p->wakeupDelay);
+ hwSchdlr = new HWScheduler(this, p.wakeupDelay);
regdQList.resize(numHWQueues);
for (int i = 0; i < numHWQueues; i++) {
regdQList[i] = new RQLEntry(this, i);
}
HSAPacketProcessor *
-HSAPacketProcessorParams::create()
+HSAPacketProcessorParams::create() const
{
- return new HSAPacketProcessor(this);
+ return new HSAPacketProcessor(*this);
}
void
const Tick pktProcessDelay;
typedef HSAPacketProcessorParams Params;
- HSAPacketProcessor(const Params *p);
+ HSAPacketProcessor(const Params &p);
~HSAPacketProcessor();
void setDeviceQueueDesc(uint64_t hostReadIndexPointer,
uint64_t basePointer,
* 4KB - see e.g.
* http://infocenter.arm.com/help/topic/com.arm.doc.dui0440b/Bbajihec.html
*/
-I2CBus::I2CBus(const I2CBusParams *p)
+I2CBus::I2CBus(const I2CBusParams &p)
: BasicPioDevice(p, 0x1000), scl(1), sda(1), state(IDLE), currBit(7),
i2cAddr(0x00), message(0x00)
{
- vector<I2CDevice*> devs = p->devices;
+ vector<I2CDevice*> devs = p.devices;
- for (auto d : p->devices) {
+ for (auto d : p.devices) {
devices[d->i2cAddr()] = d;
}
}
}
I2CBus*
-I2CBusParams::create()
+I2CBusParams::create() const
{
- return new I2CBus(this);
+ return new I2CBus(*this);
}
public:
- I2CBus(const I2CBusParams* p);
+ I2CBus(const I2CBusParams &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
public:
- I2CDevice(const I2CDeviceParams* p)
- : SimObject(p), _addr(p->i2c_addr)
+ I2CDevice(const I2CDeviceParams &p)
+ : SimObject(p), _addr(p.i2c_addr)
{ }
virtual ~I2CDevice() { }
#include "debug/AddrRanges.hh"
#include "sim/system.hh"
-PioDevice::PioDevice(const Params *p)
- : ClockedObject(p), sys(p->system), pioPort(this)
+PioDevice::PioDevice(const Params &p)
+ : ClockedObject(p), sys(p.system), pioPort(this)
{}
PioDevice::~PioDevice()
return ClockedObject::getPort(if_name, idx);
}
-BasicPioDevice::BasicPioDevice(const Params *p, Addr size)
- : PioDevice(p), pioAddr(p->pio_addr), pioSize(size),
- pioDelay(p->pio_latency)
+BasicPioDevice::BasicPioDevice(const Params &p, Addr size)
+ : PioDevice(p), pioAddr(p.pio_addr), pioSize(size),
+ pioDelay(p.pio_latency)
{}
AddrRangeList
public:
typedef PioDeviceParams Params;
- PioDevice(const Params *p);
+ PioDevice(const Params &p);
virtual ~PioDevice();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void init() override;
public:
typedef BasicPioDeviceParams Params;
- BasicPioDevice(const Params *p, Addr size);
+ BasicPioDevice(const Params &p, Addr size);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
using namespace std;
-IsaFake::IsaFake(Params *p)
- : BasicPioDevice(p, p->ret_bad_addr ? 0 : p->pio_size)
+IsaFake::IsaFake(const Params &p)
+ : BasicPioDevice(p, p.ret_bad_addr ? 0 : p.pio_size)
{
- retData8 = p->ret_data8;
- retData16 = p->ret_data16;
- retData32 = p->ret_data32;
- retData64 = p->ret_data64;
+ retData8 = p.ret_data8;
+ retData16 = p.ret_data16;
+ retData32 = p.ret_data32;
+ retData64 = p.ret_data64;
}
Tick
{
pkt->makeAtomicResponse();
- if (params()->warn_access != "")
+ if (params().warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
- if (params()->ret_bad_addr) {
+ if (params().ret_bad_addr) {
DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
pkt->setLE(retData8);
break;
default:
- if (params()->fake_mem)
+ if (params().fake_mem)
std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
else
panic("invalid access size! Device being accessed by cache?\n");
IsaFake::write(PacketPtr pkt)
{
pkt->makeAtomicResponse();
- if (params()->warn_access != "") {
+ if (params().warn_access != "") {
uint64_t data;
switch (pkt->getSize()) {
case sizeof(uint64_t):
warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
name(), pkt->getAddr(), pkt->getSize(), data);
}
- if (params()->ret_bad_addr) {
+ if (params().ret_bad_addr) {
DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
DPRINTF(IsaFake, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
- if (params()->update_data) {
+ if (params().update_data) {
switch (pkt->getSize()) {
case sizeof(uint64_t):
retData64 = pkt->getLE<uint64_t>();
}
IsaFake *
-IsaFakeParams::create()
+IsaFakeParams::create() const
{
- return new IsaFake(this);
+ return new IsaFake(*this);
}
public:
typedef IsaFakeParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for Isa Fake just registers itself with the MMU.
* @param p params structure
*/
- IsaFake(Params *p);
+ IsaFake(const Params &p);
/**
* This read always returns -1.
using namespace std;
-Malta::Malta(const Params *p)
- : Platform(p), system(p->system)
+Malta::Malta(const Params &p)
+ : Platform(p), system(p.system)
{
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;
}
Malta *
-MaltaParams::create()
+MaltaParams::create() const
{
- return new Malta(this);
+ return new Malta(*this);
}
* @param intctrl pointer to the interrupt controller
*/
typedef MaltaParams Params;
- Malta(const Params *p);
+ Malta(const Params &p);
/**
* Cause the cpu to post a serial interrupt to the CPU.
using namespace std;
-MaltaCChip::MaltaCChip(Params *p)
- : BasicPioDevice(p, 0xfffffff), malta(p->malta)
+MaltaCChip::MaltaCChip(const Params &p)
+ : BasicPioDevice(p, 0xfffffff), malta(p.malta)
{
warn("MaltaCCHIP::MaltaCChip() not implemented.");
}
MaltaCChip *
-MaltaCChipParams::create()
+MaltaCChipParams::create() const
{
- return new MaltaCChip(this);
+ return new MaltaCChip(*this);
}
public:
typedef MaltaCChipParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* device register to 0.
* @param p params struct
*/
- MaltaCChip(Params *p);
+ MaltaCChip(const Params &p);
Tick read(PacketPtr pkt) override;
using namespace std;
-MaltaIO::RTC::RTC(const string &name, const MaltaIOParams *p)
- : MC146818(p->malta, name, p->time, p->year_is_bcd, p->frequency),
- malta(p->malta)
+MaltaIO::RTC::RTC(const string &name, const MaltaIOParams &p)
+ : MC146818(p.malta, name, p.time, p.year_is_bcd, p.frequency),
+ malta(p.malta)
{
}
-MaltaIO::MaltaIO(const Params *p)
- : BasicPioDevice(p, 0x100), malta(p->malta),
- pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
+MaltaIO::MaltaIO(const Params &p)
+ : BasicPioDevice(p, 0x100), malta(p.malta),
+ pitimer(this, p.name + "pitimer"), rtc(p.name + ".rtc", p)
{
// set the back pointer from malta to myself
malta->io = this;
Tick
MaltaIO::frequency() const
{
- return SimClock::Frequency / params()->frequency;
+ return SimClock::Frequency / params().frequency;
}
Tick
}
MaltaIO *
-MaltaIOParams::create()
+MaltaIOParams::create() const
{
- return new MaltaIO(this);
+ return new MaltaIO(*this);
}
{
public:
Malta *malta;
- RTC(const std::string &name, const MaltaIOParams *p);
+ RTC(const std::string &name, const MaltaIOParams &p);
protected:
void handleEvent()
typedef MaltaIOParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
* Initialize all the data for devices supported by Malta I/O.
* @param p pointer to Params struct
*/
- MaltaIO(const Params *p);
+ MaltaIO(const Params &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
using namespace std;
-DistEtherLink::DistEtherLink(const Params *p)
- : SimObject(p), linkDelay(p->delay)
+DistEtherLink::DistEtherLink(const Params &p)
+ : SimObject(p), linkDelay(p.delay)
{
DPRINTF(DistEthernet,"DistEtherLink::DistEtherLink() "
- "link delay:%llu ticksPerByte:%f\n", p->delay, p->speed);
+ "link delay:%llu ticksPerByte:%f\n", p.delay, p.speed);
- txLink = new TxLink(name() + ".link0", this, p->speed, p->delay_var,
- p->dump);
- rxLink = new RxLink(name() + ".link1", this, p->delay, p->dump);
+ txLink = new TxLink(name() + ".link0", this, p.speed, p.delay_var,
+ p.dump);
+ rxLink = new RxLink(name() + ".link1", this, p.delay, p.dump);
Tick sync_repeat;
- if (p->sync_repeat != 0) {
- if (p->sync_repeat != p->delay)
+ if (p.sync_repeat != 0) {
+ if (p.sync_repeat != p.delay)
warn("DistEtherLink(): sync_repeat is %lu and linkdelay is %lu",
- p->sync_repeat, p->delay);
- sync_repeat = p->sync_repeat;
+ p.sync_repeat, p.delay);
+ sync_repeat = p.sync_repeat;
} else {
- sync_repeat = p->delay;
+ sync_repeat = p.delay;
}
// create the dist (TCP) interface to talk to the peer gem5 processes.
- distIface = new TCPIface(p->server_name, p->server_port,
- p->dist_rank, p->dist_size,
- p->sync_start, sync_repeat, this,
- p->dist_sync_on_pseudo_op, p->is_switch,
- p->num_nodes);
+ distIface = new TCPIface(p.server_name, p.server_port,
+ p.dist_rank, p.dist_size,
+ p.sync_start, sync_repeat, this,
+ p.dist_sync_on_pseudo_op, p.is_switch,
+ p.num_nodes);
localIface = new LocalIface(name() + ".int0", txLink, rxLink, distIface);
}
}
DistEtherLink *
-DistEtherLinkParams::create()
+DistEtherLinkParams::create() const
{
- return new DistEtherLink(this);
+ return new DistEtherLink(*this);
}
public:
typedef DistEtherLinkParams Params;
- DistEtherLink(const Params *p);
+ DistEtherLink(const Params &p);
~DistEtherLink();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,
using namespace std;
-EtherBus::EtherBus(const Params *p)
- : SimObject(p), ticksPerByte(p->speed), loopback(p->loopback),
+EtherBus::EtherBus(const Params &p)
+ : SimObject(p), ticksPerByte(p.speed), loopback(p.loopback),
event([this]{ txDone(); }, "ethernet bus completion"),
- sender(0), dump(p->dump)
+ sender(0), dump(p.dump)
{
}
}
EtherBus *
-EtherBusParams::create()
+EtherBusParams::create() const
{
- return new EtherBus(this);
+ return new EtherBus(*this);
}
public:
typedef EtherBusParams Params;
- EtherBus(const Params *p);
+ EtherBus(const Params &p);
virtual ~EtherBus() {}
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void txDone();
{
public:
typedef EtherDeviceParams Params;
- EtherDevice(const Params *params)
+ EtherDevice(const Params ¶ms)
: PciDevice(params)
{}
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
public:
class EtherDevBase : public EtherDevice
{
public:
- EtherDevBase(const EtherDevBaseParams *params)
+ EtherDevBase(const EtherDevBaseParams ¶ms)
: EtherDevice(params)
{}
- const EtherDevBaseParams *
+ const EtherDevBaseParams &
params() const
{
- return dynamic_cast<const EtherDevBaseParams *>(_params);
+ return dynamic_cast<const EtherDevBaseParams &>(_params);
}
};
using std::string;
-EtherDump::EtherDump(const Params *p)
- : SimObject(p), stream(simout.create(p->file, true)->stream()),
- maxlen(p->maxlen)
+EtherDump::EtherDump(const Params &p)
+ : SimObject(p), stream(simout.create(p.file, true)->stream()),
+ maxlen(p.maxlen)
{
}
}
EtherDump *
-EtherDumpParams::create()
+EtherDumpParams::create() const
{
- return new EtherDump(this);
+ return new EtherDump(*this);
}
public:
typedef EtherDumpParams Params;
- EtherDump(const Params *p);
+ EtherDump(const Params &p);
inline void dump(EthPacketPtr &pkt) { dumpPacket(pkt); }
};
using namespace std;
-EtherLink::EtherLink(const Params *p)
+EtherLink::EtherLink(const Params &p)
: SimObject(p)
{
- link[0] = new Link(name() + ".link0", this, 0, p->speed,
- p->delay, p->delay_var, p->dump);
- link[1] = new Link(name() + ".link1", this, 1, p->speed,
- p->delay, p->delay_var, p->dump);
+ link[0] = new Link(name() + ".link0", this, 0, p.speed,
+ p.delay, p.delay_var, p.dump);
+ link[1] = new Link(name() + ".link1", this, 1, p.speed,
+ p.delay, p.delay_var, p.dump);
interface[0] = new Interface(name() + ".int0", link[0], link[1]);
interface[1] = new Interface(name() + ".int1", link[1], link[0]);
}
EtherLink *
-EtherLinkParams::create()
+EtherLinkParams::create() const
{
- return new EtherLink(this);
+ return new EtherLink(*this);
}
public:
typedef EtherLinkParams Params;
- EtherLink(const Params *p);
+ EtherLink(const Params &p);
virtual ~EtherLink();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,
using namespace std;
-EtherSwitch::EtherSwitch(const Params *p)
- : SimObject(p), ttl(p->time_to_live)
+EtherSwitch::EtherSwitch(const Params &p)
+ : SimObject(p), ttl(p.time_to_live)
{
- for (int i = 0; i < p->port_interface_connection_count; ++i) {
+ for (int i = 0; i < p.port_interface_connection_count; ++i) {
std::string interfaceName = csprintf("%s.interface%d", name(), i);
Interface *interface = new Interface(interfaceName, this,
- p->output_buffer_size, p->delay,
- p->delay_var, p->fabric_speed, i);
+ p.output_buffer_size, p.delay,
+ p.delay_var, p.fabric_speed, i);
interfaces.push_back(interface);
}
}
}
EtherSwitch *
-EtherSwitchParams::create()
+EtherSwitchParams::create() const
{
- return new EtherSwitch(this);
+ return new EtherSwitch(*this);
}
public:
typedef EtherSwitchParams Params;
- EtherSwitch(const Params *p);
+ EtherSwitch(const Params &p);
~EtherSwitch();
- const Params * params() const
+ const Params &
+ params() const
{
- return dynamic_cast<const Params*>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,
}
};
-EtherTapBase::EtherTapBase(const Params *p)
- : SimObject(p), buflen(p->bufsz), dump(p->dump), event(NULL),
+EtherTapBase::EtherTapBase(const Params &p)
+ : SimObject(p), buflen(p.bufsz), dump(p.dump), event(NULL),
interface(NULL),
txEvent([this]{ retransmit(); }, "EtherTapBase retransmit")
{
}
-EtherTapStub::EtherTapStub(const Params *p) : EtherTapBase(p), socket(-1)
+EtherTapStub::EtherTapStub(const Params &p) : EtherTapBase(p), socket(-1)
{
if (ListenSocket::allDisabled())
fatal("All listeners are disabled! EtherTapStub can't work!");
- listener = new TapListener(this, p->port);
+ listener = new TapListener(this, p.port);
listener->listen();
}
#if USE_TUNTAP
-EtherTap::EtherTap(const Params *p) : EtherTapBase(p)
+EtherTap::EtherTap(const Params &p) : EtherTapBase(p)
{
- int fd = open(p->tun_clone_device.c_str(), O_RDWR | O_NONBLOCK);
+ int fd = open(p.tun_clone_device.c_str(), O_RDWR | O_NONBLOCK);
if (fd < 0)
- panic("Couldn't open %s.\n", p->tun_clone_device);
+ panic("Couldn't open %s.\n", p.tun_clone_device);
struct ifreq ifr;
memset(&ifr, 0, sizeof(ifr));
ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
- strncpy(ifr.ifr_name, p->tap_device_name.c_str(), IFNAMSIZ - 1);
+ strncpy(ifr.ifr_name, p.tap_device_name.c_str(), IFNAMSIZ - 1);
if (ioctl(fd, TUNSETIFF, (void *)&ifr) < 0)
panic("Failed to access tap device %s.\n", ifr.ifr_name);
}
EtherTap *
-EtherTapParams::create()
+EtherTapParams::create() const
{
- return new EtherTap(this);
+ return new EtherTap(*this);
}
#endif
EtherTapStub *
-EtherTapStubParams::create()
+EtherTapStubParams::create() const
{
- return new EtherTapStub(this);
+ return new EtherTapStub(*this);
}
{
public:
typedef EtherTapBaseParams Params;
- EtherTapBase(const Params *p);
+ EtherTapBase(const Params &p);
virtual ~EtherTapBase();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void serialize(CheckpointOut &cp) const override;
{
public:
typedef EtherTapStubParams Params;
- EtherTapStub(const Params *p);
+ EtherTapStub(const Params &p);
~EtherTapStub();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
void serialize(CheckpointOut &cp) const override;
{
public:
typedef EtherTapParams Params;
- EtherTap(const Params *p);
+ EtherTap(const Params &p);
~EtherTap();
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
using namespace iGbReg;
using namespace Net;
-IGbE::IGbE(const Params *p)
+IGbE::IGbE(const Params &p)
: EtherDevice(p), etherInt(NULL),
- rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), inTick(false),
+ rxFifo(p.rx_fifo_size), txFifo(p.tx_fifo_size), inTick(false),
rxTick(false), txTick(false), txFifoTick(false), rxDmaPacket(false),
- pktOffset(0), fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
- fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay),
- rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay),
+ pktOffset(0), fetchDelay(p.fetch_delay), wbDelay(p.wb_delay),
+ fetchCompDelay(p.fetch_comp_delay), wbCompDelay(p.wb_comp_delay),
+ rxWriteDelay(p.rx_write_delay), txReadDelay(p.tx_read_delay),
rdtrEvent([this]{ rdtrProcess(); }, name()),
radvEvent([this]{ radvProcess(); }, name()),
tadvEvent([this]{ tadvProcess(); }, name()),
tidvEvent([this]{ tidvProcess(); }, name()),
tickEvent([this]{ tick(); }, name()),
interEvent([this]{ delayIntEvent(); }, name()),
- rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
- txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
+ rxDescCache(this, name()+".RxDesc", p.rx_desc_cache_size),
+ txDescCache(this, name()+".TxDesc", p.tx_desc_cache_size),
lastInterrupt(0)
{
etherInt = new IGbEInt(name() + ".int", this);
memset(&flash, 0, EEPROM_SIZE*2);
// Set the MAC address
- memcpy(flash, p->hardware_address.bytes(), ETH_ADDR_LEN);
+ memcpy(flash, p.hardware_address.bytes(), ETH_ADDR_LEN);
for (int x = 0; x < ETH_ADDR_LEN/2; x++)
flash[x] = htobe(flash[x]);
flash[EEPROM_SIZE-1] = htobe((uint16_t)(EEPROM_CSUM - csum));
// Store the MAC address as queue ID
- macAddr = p->hardware_address;
+ macAddr = p.hardware_address;
rxFifo.clear();
txFifo.clear();
regs.mdic.data(0x796D); // link up
break;
case PHY_PID:
- regs.mdic.data(params()->phy_pid);
+ regs.mdic.data(params().phy_pid);
break;
case PHY_EPID:
- regs.mdic.data(params()->phy_epid);
+ regs.mdic.data(params().phy_epid);
break;
case PHY_GSTATUS:
regs.mdic.data(0x7C00);
}
IGbE *
-IGbEParams::create()
+IGbEParams::create() const
{
- return new IGbE(this);
+ return new IGbE(*this);
}
public:
typedef IGbEParams Params;
- const Params *
- params() const {
- return dynamic_cast<const Params *>(_params);
+ const Params &
+ params() const
+ {
+ return dynamic_cast<const Params &>(_params);
}
- IGbE(const Params *params);
+ IGbE(const Params ¶ms);
~IGbE();
void init() override;
//
// NSGigE PCI Device
//
-NSGigE::NSGigE(Params *p)
+NSGigE::NSGigE(const Params &p)
: EtherDevBase(p), ioEnable(false),
- txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
+ txFifo(p.tx_fifo_size), rxFifo(p.rx_fifo_size),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
txState(txIdle), txEnable(false), CTDD(false), txHalt(false),
rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
eepromState(eepromStart), eepromClk(false), eepromBitsToRx(0),
eepromOpcode(0), eepromAddress(0), eepromData(0),
- dmaReadDelay(p->dma_read_delay), dmaWriteDelay(p->dma_write_delay),
- dmaReadFactor(p->dma_read_factor), dmaWriteFactor(p->dma_write_factor),
+ dmaReadDelay(p.dma_read_delay), dmaWriteDelay(p.dma_write_delay),
+ dmaReadFactor(p.dma_read_factor), dmaWriteFactor(p.dma_write_factor),
rxDmaData(NULL), rxDmaAddr(0), rxDmaLen(0),
txDmaData(NULL), txDmaAddr(0), txDmaLen(0),
rxDmaReadEvent([this]{ rxDmaReadDone(); }, name()),
rxDmaWriteEvent([this]{ rxDmaWriteDone(); }, name()),
txDmaReadEvent([this]{ txDmaReadDone(); }, name()),
txDmaWriteEvent([this]{ txDmaWriteDone(); }, name()),
- dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free),
- txDelay(p->tx_delay), rxDelay(p->rx_delay),
+ dmaDescFree(p.dma_desc_free), dmaDataFree(p.dma_data_free),
+ txDelay(p.tx_delay), rxDelay(p.rx_delay),
rxKickTick(0),
rxKickEvent([this]{ rxKick(); }, name()),
txKickTick(0),
txKickEvent([this]{ txKick(); }, name()),
txEvent([this]{ txEventTransmit(); }, name()),
- rxFilterEnable(p->rx_filter),
+ rxFilterEnable(p.rx_filter),
acceptBroadcast(false), acceptMulticast(false), acceptUnicast(false),
acceptPerfect(false), acceptArp(false), multicastHashEnable(false),
- intrDelay(p->intr_delay), intrTick(0), cpuPendingIntr(false),
+ intrDelay(p.intr_delay), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
interface = new NSGigEInt(name() + ".int0", this);
regsReset();
- memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
+ memcpy(&rom.perfectMatch, p.hardware_address.bytes(), ETH_ADDR_LEN);
memset(&rxDesc32, 0, sizeof(rxDesc32));
memset(&txDesc32, 0, sizeof(txDesc32));
case M5REG:
reg = 0;
- if (params()->rx_thread)
+ if (params().rx_thread)
reg |= M5REG_RX_THREAD;
- if (params()->tx_thread)
+ if (params().tx_thread)
reg |= M5REG_TX_THREAD;
- if (params()->rss)
+ if (params().rss)
reg |= M5REG_RSS;
break;
}
NSGigE *
-NSGigEParams::create()
+NSGigEParams::create() const
{
- return new NSGigE(this);
+ return new NSGigE(*this);
}
public:
typedef NSGigEParams Params;
- const Params *params() const {
- return dynamic_cast<const Params *>(_params);
+ const Params &
+ params() const
+ {
+ return dynamic_cast<const Params &>(_params);
}
- NSGigE(Params *params);
+ NSGigE(const Params ¶ms);
~NSGigE();
Port &getPort(const std::string &if_name,
//
// Sinic PCI Device
//
-Base::Base(const Params *p)
+Base::Base(const Params &p)
: EtherDevBase(p), rxEnable(false), txEnable(false),
- intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
+ intrDelay(p.intr_delay), intrTick(0), cpuIntrEnable(false),
cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
}
-Device::Device(const Params *p)
+Device::Device(const Params &p)
: Base(p), rxUnique(0), txUnique(0),
- virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
- rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
+ virtualRegs(p.virtual_count < 1 ? 1 : p.virtual_count),
+ rxFifo(p.rx_fifo_size), txFifo(p.tx_fifo_size),
rxKickTick(0), txKickTick(0),
txEvent([this]{ txEventTransmit(); }, name()),
rxDmaEvent([this]{ rxDmaDone(); }, name()),
txDmaEvent([this]{ txDmaDone(); }, name()),
- dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
- dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
+ dmaReadDelay(p.dma_read_delay), dmaReadFactor(p.dma_read_factor),
+ dmaWriteDelay(p.dma_write_delay), dmaWriteFactor(p.dma_write_factor)
{
interface = new Interface(name() + ".int0", this);
reset();
-
}
Device::~Device()
memset(®s, 0, sizeof(regs));
regs.Config = 0;
- if (params()->rx_thread)
+ if (params().rx_thread)
regs.Config |= Config_RxThread;
- if (params()->tx_thread)
+ if (params().tx_thread)
regs.Config |= Config_TxThread;
- if (params()->rss)
+ if (params().rss)
regs.Config |= Config_RSS;
- if (params()->zero_copy)
+ if (params().zero_copy)
regs.Config |= Config_ZeroCopy;
- if (params()->delay_copy)
+ if (params().delay_copy)
regs.Config |= Config_DelayCopy;
- if (params()->virtual_addr)
+ if (params().virtual_addr)
regs.Config |= Config_Vaddr;
- if (params()->delay_copy && params()->zero_copy)
+ if (params().delay_copy && params().zero_copy)
panic("Can't delay copy and zero copy");
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
- regs.RxMaxCopy = params()->rx_max_copy;
- regs.TxMaxCopy = params()->tx_max_copy;
- regs.ZeroCopySize = params()->zero_copy_size;
- regs.ZeroCopyMark = params()->zero_copy_threshold;
- regs.VirtualCount = params()->virtual_count;
- regs.RxMaxIntr = params()->rx_max_intr;
- regs.RxFifoSize = params()->rx_fifo_size;
- regs.TxFifoSize = params()->tx_fifo_size;
- regs.RxFifoLow = params()->rx_fifo_low_mark;
- regs.TxFifoLow = params()->tx_fifo_threshold;
- regs.RxFifoHigh = params()->rx_fifo_threshold;
- regs.TxFifoHigh = params()->tx_fifo_high_mark;
- regs.HwAddr = params()->hardware_address;
+ regs.RxMaxCopy = params().rx_max_copy;
+ regs.TxMaxCopy = params().tx_max_copy;
+ regs.ZeroCopySize = params().zero_copy_size;
+ regs.ZeroCopyMark = params().zero_copy_threshold;
+ regs.VirtualCount = params().virtual_count;
+ regs.RxMaxIntr = params().rx_max_intr;
+ regs.RxFifoSize = params().rx_fifo_size;
+ regs.TxFifoSize = params().tx_fifo_size;
+ regs.RxFifoLow = params().rx_fifo_low_mark;
+ regs.TxFifoLow = params().tx_fifo_threshold;
+ regs.RxFifoHigh = params().rx_fifo_threshold;
+ regs.TxFifoHigh = params().tx_fifo_high_mark;
+ regs.HwAddr = params().hardware_address;
if (regs.RxMaxCopy < regs.ZeroCopyMark)
panic("Must be able to copy at least as many bytes as the threshold");
} // namespace Sinic
Sinic::Device *
-SinicParams::create()
+SinicParams::create() const
{
- return new Sinic::Device(this);
+ return new Sinic::Device(*this);
}
*/
public:
typedef SinicParams Params;
- const Params *params() const { return (const Params *)_params; }
- Base(const Params *p);
+ const Params ¶ms() const { return (const Params &)_params; }
+ Base(const Params &p);
};
class Device : public Base
void unserialize(CheckpointIn &cp) override;
public:
- Device(const Params *p);
+ Device(const Params &p);
~Device();
};
using namespace CopyEngineReg;
-CopyEngine::CopyEngine(const Params *p)
+CopyEngine::CopyEngine(const Params &p)
: PciDevice(p)
{
// All Reg regs are initialized to 0 by default
- regs.chanCount = p->ChanCnt;
- regs.xferCap = findMsbSet(p->XferCap);
+ regs.chanCount = p.ChanCnt;
+ regs.xferCap = findMsbSet(p.XferCap);
regs.attnStatus = 0;
if (regs.chanCount > 64)
CopyEngine::CopyEngineChannel::CopyEngineChannel(CopyEngine *_ce, int cid)
: cePort(_ce, _ce->sys),
ce(_ce), channelId(cid), busy(false), underReset(false),
- refreshNext(false), latBeforeBegin(ce->params()->latBeforeBegin),
- latAfterCompletion(ce->params()->latAfterCompletion),
+ refreshNext(false), latBeforeBegin(ce->params().latBeforeBegin),
+ latAfterCompletion(ce->params().latAfterCompletion),
completionDataReg(0), nextState(Idle),
fetchCompleteEvent([this]{ fetchDescComplete(); }, name()),
addrCompleteEvent([this]{ fetchAddrComplete(); }, name()),
curDmaDesc = new DmaDesc;
memset(curDmaDesc, 0, sizeof(DmaDesc));
- copyBuffer = new uint8_t[ce->params()->XferCap];
+ copyBuffer = new uint8_t[ce->params().XferCap];
}
CopyEngine::~CopyEngine()
int nextState = this->nextState;
SERIALIZE_SCALAR(nextState);
arrayParamOut(cp, "curDmaDesc", (uint8_t*)curDmaDesc, sizeof(DmaDesc));
- SERIALIZE_ARRAY(copyBuffer, ce->params()->XferCap);
+ SERIALIZE_ARRAY(copyBuffer, ce->params().XferCap);
cr.serialize(cp);
}
UNSERIALIZE_SCALAR(nextState);
this->nextState = (ChannelState)nextState;
arrayParamIn(cp, "curDmaDesc", (uint8_t*)curDmaDesc, sizeof(DmaDesc));
- UNSERIALIZE_ARRAY(copyBuffer, ce->params()->XferCap);
+ UNSERIALIZE_ARRAY(copyBuffer, ce->params().XferCap);
cr.unserialize(cp);
}
}
CopyEngine *
-CopyEngineParams::create()
+CopyEngineParams::create() const
{
- return new CopyEngine(this);
+ return new CopyEngine(*this);
}
public:
typedef CopyEngineParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- CopyEngine(const Params *params);
+ CopyEngine(const Params ¶ms);
~CopyEngine();
void regStats() override;
#include "sim/byteswap.hh"
#include "sim/core.hh"
-PciDevice::PciDevice(const PciDeviceParams *p)
+PciDevice::PciDevice(const PciDeviceParams &p)
: DmaDevice(p),
- _busAddr(p->pci_bus, p->pci_dev, p->pci_func),
- PMCAP_BASE(p->PMCAPBaseOffset),
- PMCAP_ID_OFFSET(p->PMCAPBaseOffset+PMCAP_ID),
- PMCAP_PC_OFFSET(p->PMCAPBaseOffset+PMCAP_PC),
- PMCAP_PMCS_OFFSET(p->PMCAPBaseOffset+PMCAP_PMCS),
- MSICAP_BASE(p->MSICAPBaseOffset),
- MSIXCAP_BASE(p->MSIXCAPBaseOffset),
- MSIXCAP_ID_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_ID),
- MSIXCAP_MXC_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MXC),
- MSIXCAP_MTAB_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MTAB),
- MSIXCAP_MPBA_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MPBA),
- PXCAP_BASE(p->PXCAPBaseOffset),
-
- hostInterface(p->host->registerDevice(this, _busAddr,
- (PciIntPin)p->InterruptPin)),
- pioDelay(p->pio_latency),
- configDelay(p->config_latency)
+ _busAddr(p.pci_bus, p.pci_dev, p.pci_func),
+ PMCAP_BASE(p.PMCAPBaseOffset),
+ PMCAP_ID_OFFSET(p.PMCAPBaseOffset+PMCAP_ID),
+ PMCAP_PC_OFFSET(p.PMCAPBaseOffset+PMCAP_PC),
+ PMCAP_PMCS_OFFSET(p.PMCAPBaseOffset+PMCAP_PMCS),
+ MSICAP_BASE(p.MSICAPBaseOffset),
+ MSIXCAP_BASE(p.MSIXCAPBaseOffset),
+ MSIXCAP_ID_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_ID),
+ MSIXCAP_MXC_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MXC),
+ MSIXCAP_MTAB_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MTAB),
+ MSIXCAP_MPBA_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MPBA),
+ PXCAP_BASE(p.PXCAPBaseOffset),
+
+ hostInterface(p.host->registerDevice(this, _busAddr,
+ (PciIntPin)p.InterruptPin)),
+ pioDelay(p.pio_latency),
+ configDelay(p.config_latency)
{
- fatal_if(p->InterruptPin >= 5,
- "Invalid PCI interrupt '%i' specified.", p->InterruptPin);
-
- config.vendor = htole(p->VendorID);
- config.device = htole(p->DeviceID);
- config.command = htole(p->Command);
- config.status = htole(p->Status);
- config.revision = htole(p->Revision);
- config.progIF = htole(p->ProgIF);
- config.subClassCode = htole(p->SubClassCode);
- config.classCode = htole(p->ClassCode);
- config.cacheLineSize = htole(p->CacheLineSize);
- config.latencyTimer = htole(p->LatencyTimer);
- config.headerType = htole(p->HeaderType);
- config.bist = htole(p->BIST);
-
- config.baseAddr[0] = htole(p->BAR0);
- config.baseAddr[1] = htole(p->BAR1);
- config.baseAddr[2] = htole(p->BAR2);
- config.baseAddr[3] = htole(p->BAR3);
- config.baseAddr[4] = htole(p->BAR4);
- config.baseAddr[5] = htole(p->BAR5);
- config.cardbusCIS = htole(p->CardbusCIS);
- config.subsystemVendorID = htole(p->SubsystemVendorID);
- config.subsystemID = htole(p->SubsystemID);
- config.expansionROM = htole(p->ExpansionROM);
- config.capabilityPtr = htole(p->CapabilityPtr);
+ fatal_if(p.InterruptPin >= 5,
+ "Invalid PCI interrupt '%i' specified.", p.InterruptPin);
+
+ config.vendor = htole(p.VendorID);
+ config.device = htole(p.DeviceID);
+ config.command = htole(p.Command);
+ config.status = htole(p.Status);
+ config.revision = htole(p.Revision);
+ config.progIF = htole(p.ProgIF);
+ config.subClassCode = htole(p.SubClassCode);
+ config.classCode = htole(p.ClassCode);
+ config.cacheLineSize = htole(p.CacheLineSize);
+ config.latencyTimer = htole(p.LatencyTimer);
+ config.headerType = htole(p.HeaderType);
+ config.bist = htole(p.BIST);
+
+ config.baseAddr[0] = htole(p.BAR0);
+ config.baseAddr[1] = htole(p.BAR1);
+ config.baseAddr[2] = htole(p.BAR2);
+ config.baseAddr[3] = htole(p.BAR3);
+ config.baseAddr[4] = htole(p.BAR4);
+ config.baseAddr[5] = htole(p.BAR5);
+ config.cardbusCIS = htole(p.CardbusCIS);
+ config.subsystemVendorID = htole(p.SubsystemVendorID);
+ config.subsystemID = htole(p.SubsystemID);
+ config.expansionROM = htole(p.ExpansionROM);
+ config.capabilityPtr = htole(p.CapabilityPtr);
// Zero out the 7 bytes of reserved space in the PCI Config space register.
bzero(config.reserved, 7*sizeof(uint8_t));
- config.interruptLine = htole(p->InterruptLine);
- config.interruptPin = htole(p->InterruptPin);
- config.minimumGrant = htole(p->MinimumGrant);
- config.maximumLatency = htole(p->MaximumLatency);
+ config.interruptLine = htole(p.InterruptLine);
+ config.interruptPin = htole(p.InterruptPin);
+ config.minimumGrant = htole(p.MinimumGrant);
+ config.maximumLatency = htole(p.MaximumLatency);
// Initialize the capability lists
// These structs are bitunions, meaning the data is stored in host
// endianess and must be converted to Little Endian when accessed
// by the guest
// PMCAP
- pmcap.pid = (uint16_t)p->PMCAPCapId; // pid.cid
- pmcap.pid |= (uint16_t)p->PMCAPNextCapability << 8; //pid.next
- pmcap.pc = p->PMCAPCapabilities;
- pmcap.pmcs = p->PMCAPCtrlStatus;
+ pmcap.pid = (uint16_t)p.PMCAPCapId; // pid.cid
+ pmcap.pid |= (uint16_t)p.PMCAPNextCapability << 8; //pid.next
+ pmcap.pc = p.PMCAPCapabilities;
+ pmcap.pmcs = p.PMCAPCtrlStatus;
// MSICAP
- msicap.mid = (uint16_t)p->MSICAPCapId; //mid.cid
- msicap.mid |= (uint16_t)p->MSICAPNextCapability << 8; //mid.next
- msicap.mc = p->MSICAPMsgCtrl;
- msicap.ma = p->MSICAPMsgAddr;
- msicap.mua = p->MSICAPMsgUpperAddr;
- msicap.md = p->MSICAPMsgData;
- msicap.mmask = p->MSICAPMaskBits;
- msicap.mpend = p->MSICAPPendingBits;
+ msicap.mid = (uint16_t)p.MSICAPCapId; //mid.cid
+ msicap.mid |= (uint16_t)p.MSICAPNextCapability << 8; //mid.next
+ msicap.mc = p.MSICAPMsgCtrl;
+ msicap.ma = p.MSICAPMsgAddr;
+ msicap.mua = p.MSICAPMsgUpperAddr;
+ msicap.md = p.MSICAPMsgData;
+ msicap.mmask = p.MSICAPMaskBits;
+ msicap.mpend = p.MSICAPPendingBits;
// MSIXCAP
- msixcap.mxid = (uint16_t)p->MSIXCAPCapId; //mxid.cid
- msixcap.mxid |= (uint16_t)p->MSIXCAPNextCapability << 8; //mxid.next
- msixcap.mxc = p->MSIXMsgCtrl;
- msixcap.mtab = p->MSIXTableOffset;
- msixcap.mpba = p->MSIXPbaOffset;
+ msixcap.mxid = (uint16_t)p.MSIXCAPCapId; //mxid.cid
+ msixcap.mxid |= (uint16_t)p.MSIXCAPNextCapability << 8; //mxid.next
+ msixcap.mxc = p.MSIXMsgCtrl;
+ msixcap.mtab = p.MSIXTableOffset;
+ msixcap.mpba = p.MSIXPbaOffset;
// allocate MSIX structures if MSIXCAP_BASE
// indicates the MSIXCAP is being used by having a
}
// PXCAP
- pxcap.pxid = (uint16_t)p->PXCAPCapId; //pxid.cid
- pxcap.pxid |= (uint16_t)p->PXCAPNextCapability << 8; //pxid.next
- pxcap.pxcap = p->PXCAPCapabilities;
- pxcap.pxdcap = p->PXCAPDevCapabilities;
- pxcap.pxdc = p->PXCAPDevCtrl;
- pxcap.pxds = p->PXCAPDevStatus;
- pxcap.pxlcap = p->PXCAPLinkCap;
- pxcap.pxlc = p->PXCAPLinkCtrl;
- pxcap.pxls = p->PXCAPLinkStatus;
- pxcap.pxdcap2 = p->PXCAPDevCap2;
- pxcap.pxdc2 = p->PXCAPDevCtrl2;
-
- BARSize[0] = p->BAR0Size;
- BARSize[1] = p->BAR1Size;
- BARSize[2] = p->BAR2Size;
- BARSize[3] = p->BAR3Size;
- BARSize[4] = p->BAR4Size;
- BARSize[5] = p->BAR5Size;
-
- legacyIO[0] = p->BAR0LegacyIO;
- legacyIO[1] = p->BAR1LegacyIO;
- legacyIO[2] = p->BAR2LegacyIO;
- legacyIO[3] = p->BAR3LegacyIO;
- legacyIO[4] = p->BAR4LegacyIO;
- legacyIO[5] = p->BAR5LegacyIO;
+ pxcap.pxid = (uint16_t)p.PXCAPCapId; //pxid.cid
+ pxcap.pxid |= (uint16_t)p.PXCAPNextCapability << 8; //pxid.next
+ pxcap.pxcap = p.PXCAPCapabilities;
+ pxcap.pxdcap = p.PXCAPDevCapabilities;
+ pxcap.pxdc = p.PXCAPDevCtrl;
+ pxcap.pxds = p.PXCAPDevStatus;
+ pxcap.pxlcap = p.PXCAPLinkCap;
+ pxcap.pxlc = p.PXCAPLinkCtrl;
+ pxcap.pxls = p.PXCAPLinkStatus;
+ pxcap.pxdcap2 = p.PXCAPDevCap2;
+ pxcap.pxdc2 = p.PXCAPDevCtrl2;
+
+ BARSize[0] = p.BAR0Size;
+ BARSize[1] = p.BAR1Size;
+ BARSize[2] = p.BAR2Size;
+ BARSize[3] = p.BAR3Size;
+ BARSize[4] = p.BAR4Size;
+ BARSize[5] = p.BAR5Size;
+
+ legacyIO[0] = p.BAR0LegacyIO;
+ legacyIO[1] = p.BAR1LegacyIO;
+ legacyIO[2] = p.BAR2LegacyIO;
+ legacyIO[3] = p.BAR3LegacyIO;
+ legacyIO[4] = p.BAR4LegacyIO;
+ legacyIO[5] = p.BAR5LegacyIO;
for (int i = 0; i < 6; ++i) {
if (legacyIO[i]) {
- BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
+ BARAddrs[i] = p.LegacyIOBase + letoh(config.baseAddr[i]);
config.baseAddr[i] = 0;
} else {
BARAddrs[i] = 0;
* config file object PCIConfigData and registers the device with
* a PciHost object.
*/
- PciDevice(const PciDeviceParams *params);
+ PciDevice(const PciDeviceParams ¶ms);
/**
* Serialize this object to the given output stream.
#include "params/GenericPciHost.hh"
#include "params/PciHost.hh"
-PciHost::PciHost(const PciHostParams *p)
+PciHost::PciHost(const PciHostParams &p)
: PioDevice(p)
{
}
}
-GenericPciHost::GenericPciHost(const GenericPciHostParams *p)
+GenericPciHost::GenericPciHost(const GenericPciHostParams &p)
: PciHost(p),
- platform(*p->platform),
- confBase(p->conf_base), confSize(p->conf_size),
- confDeviceBits(p->conf_device_bits),
- pciPioBase(p->pci_pio_base), pciMemBase(p->pci_mem_base),
- pciDmaBase(p->pci_dma_base)
+ platform(*p.platform),
+ confBase(p.conf_base), confSize(p.conf_size),
+ confDeviceBits(p.conf_device_bits),
+ pciPioBase(p.pci_pio_base), pciMemBase(p.pci_mem_base),
+ pciDmaBase(p.pci_dma_base)
{
}
GenericPciHost *
-GenericPciHostParams::create()
+GenericPciHostParams::create() const
{
- return new GenericPciHost(this);
+ return new GenericPciHost(*this);
}
class PciHost : public PioDevice
{
public:
- PciHost(const PciHostParams *p);
+ PciHost(const PciHostParams &p);
virtual ~PciHost();
public:
class GenericPciHost : public PciHost
{
public:
- GenericPciHost(const GenericPciHostParams *p);
+ GenericPciHost(const GenericPciHostParams &p);
virtual ~GenericPciHost();
public: // PioDevice
using namespace std;
-Platform::Platform(const Params *p)
- : SimObject(p), intrctrl(p->intrctrl)
+Platform::Platform(const Params &p)
+ : SimObject(p), intrctrl(p.intrctrl)
{
}
public:
typedef PlatformParams Params;
- Platform(const Params *p);
+ Platform(const Params &p);
virtual ~Platform();
/**
#include "dev/ps2/types.hh"
#include "params/PS2Device.hh"
-PS2Device::PS2Device(const PS2DeviceParams *p)
+PS2Device::PS2Device(const PS2DeviceParams &p)
: SimObject(p)
{
inBuffer.reserve(16);
class PS2Device : public SimObject
{
public:
- PS2Device(const PS2DeviceParams *p);
+ PS2Device(const PS2DeviceParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
#include "dev/ps2/types.hh"
#include "params/PS2Keyboard.hh"
-PS2Keyboard::PS2Keyboard(const PS2KeyboardParams *p)
+PS2Keyboard::PS2Keyboard(const PS2KeyboardParams &p)
: PS2Device(p),
shiftDown(false),
enabled(false)
{
- if (p->vnc)
- p->vnc->setKeyboard(this);
+ if (p.vnc)
+ p.vnc->setKeyboard(this);
}
void
PS2Keyboard *
-PS2KeyboardParams::create()
+PS2KeyboardParams::create() const
{
- return new PS2Keyboard(this);
+ return new PS2Keyboard(*this);
}
bool enabled;
public:
- PS2Keyboard(const PS2KeyboardParams *p);
+ PS2Keyboard(const PS2KeyboardParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
#include "dev/ps2/types.hh"
#include "params/PS2Mouse.hh"
-PS2Mouse::PS2Mouse(const PS2MouseParams *p)
+PS2Mouse::PS2Mouse(const PS2MouseParams &p)
: PS2Device(p),
status(0), resolution(4), sampleRate(100)
{
}
PS2Mouse *
-PS2MouseParams::create()
+PS2MouseParams::create() const
{
- return new PS2Mouse(this);
+ return new PS2Mouse(*this);
}
uint8_t sampleRate;
public:
- PS2Mouse(const PS2MouseParams *p);
+ PS2Mouse(const PS2MouseParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
#include "dev/ps2/types.hh"
#include "params/PS2TouchKit.hh"
-PS2TouchKit::PS2TouchKit(const PS2TouchKitParams *p)
+PS2TouchKit::PS2TouchKit(const PS2TouchKitParams &p)
: PS2Device(p),
- vnc(p->vnc),
+ vnc(p.vnc),
enabled(false), touchKitEnabled(false)
{
if (vnc)
}
PS2TouchKit *
-PS2TouchKitParams::create()
+PS2TouchKitParams::create() const
{
- return new PS2TouchKit(this);
+ return new PS2TouchKit(*this);
}
};
public:
- PS2TouchKit(const PS2TouchKitParams *p);
+ PS2TouchKit(const PS2TouchKitParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
#include "params/SerialDevice.hh"
#include "params/SerialNullDevice.hh"
-SerialDevice::SerialDevice(const SerialDeviceParams *p) : SimObject(p)
+SerialDevice::SerialDevice(const SerialDeviceParams &p) : SimObject(p)
{
}
-SerialNullDevice::SerialNullDevice(const SerialNullDeviceParams *p)
+SerialNullDevice::SerialNullDevice(const SerialNullDeviceParams &p)
: SerialDevice(p)
{
}
SerialNullDevice *
-SerialNullDeviceParams::create()
+SerialNullDeviceParams::create() const
{
- return new SerialNullDevice(this);
+ return new SerialNullDevice(*this);
}
class SerialDevice : public SimObject
{
public:
- SerialDevice(const SerialDeviceParams *p);
+ SerialDevice(const SerialDeviceParams &p);
~SerialDevice();
public: // Serial device API (UART->Device)
class SerialNullDevice : public SerialDevice
{
public:
- SerialNullDevice(const SerialNullDeviceParams *p);
+ SerialNullDevice(const SerialNullDeviceParams &p);
public:
bool dataAvailable() const override { return false; }
#include "params/SimpleUart.hh"
#include "sim/sim_exit.hh"
-SimpleUart::SimpleUart(const SimpleUartParams *p)
- : Uart(p, p->pio_size), byteOrder(p->byte_order), endOnEOT(p->end_on_eot)
+SimpleUart::SimpleUart(const SimpleUartParams &p)
+ : Uart(p, p.pio_size), byteOrder(p.byte_order), endOnEOT(p.end_on_eot)
{
}
}
SimpleUart *
-SimpleUartParams::create()
+SimpleUartParams::create() const
{
- return new SimpleUart(this);
+ return new SimpleUart(*this);
}
class SimpleUart : public Uart
{
public:
- SimpleUart(const SimpleUartParams *p);
+ SimpleUart(const SimpleUartParams &p);
public: // PioDevice
Tick read(PacketPtr pkt) override;
/*
* Terminal code
*/
-Terminal::Terminal(const Params *p)
+Terminal::Terminal(const Params &p)
: SerialDevice(p), listenEvent(NULL), dataEvent(NULL),
- number(p->number), data_fd(-1), txbuf(16384), rxbuf(16384),
+ number(p.number), data_fd(-1), txbuf(16384), rxbuf(16384),
outfile(terminalDump(p))
#if TRACING_ON == 1
, linebuf(16384)
if (outfile)
outfile->stream()->setf(ios::unitbuf);
- if (p->port)
- listen(p->port);
+ if (p.port)
+ listen(p.port);
}
Terminal::~Terminal()
}
OutputStream *
-Terminal::terminalDump(const TerminalParams* p)
+Terminal::terminalDump(const TerminalParams &p)
{
- switch (p->outfile) {
+ switch (p.outfile) {
case TerminalDump::none:
return nullptr;
case TerminalDump::stdoutput:
case TerminalDump::stderror:
return simout.findOrCreate("stderr");
case TerminalDump::file:
- return simout.findOrCreate(p->name);
+ return simout.findOrCreate(p.name);
default:
panic("Invalid option\n");
}
}
Terminal *
-TerminalParams::create()
+TerminalParams::create() const
{
- return new Terminal(this);
+ return new Terminal(*this);
}
public:
typedef TerminalParams Params;
- Terminal(const Params *p);
+ Terminal(const Params &p);
~Terminal();
- OutputStream * terminalDump(const TerminalParams* p);
+ OutputStream * terminalDump(const TerminalParams &p);
protected:
ListenSocket listener;
#include "dev/serial/uart.hh"
-Uart::Uart(const Params *p, Addr pio_size) :
- BasicPioDevice(p, pio_size), platform(p->platform), device(p->device)
+Uart::Uart(const Params &p, Addr pio_size) :
+ BasicPioDevice(p, pio_size), platform(p.platform), device(p.device)
{
status = 0;
public:
typedef UartParams Params;
- Uart(const Params *p, Addr pio_size);
+ Uart(const Params &p, Addr pio_size);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
}
-Uart8250::Uart8250(const Params *p)
+Uart8250::Uart8250(const Params &p)
: Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
txIntrEvent([this]{ processIntrEvent(TX_INT); }, "TX"),
rxIntrEvent([this]{ processIntrEvent(RX_INT); }, "RX")
}
Uart8250 *
-Uart8250Params::create()
+Uart8250Params::create() const
{
- return new Uart8250(this);
+ return new Uart8250(*this);
}
public:
typedef Uart8250Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Uart8250(const Params *p);
+ Uart8250(const Params &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
using namespace std;
-DumbTOD::DumbTOD(const Params *p)
+DumbTOD::DumbTOD(const Params &p)
: BasicPioDevice(p, 0x08)
{
- struct tm tm = p->time;
+ struct tm tm = p.time;
todTime = mkutctime(&tm);
DPRINTFN("Real-time clock set to %s\n", asctime(&tm));
}
DumbTOD *
-DumbTODParams::create()
+DumbTODParams::create() const
{
- return new DumbTOD(this);
+ return new DumbTOD(*this);
}
public:
typedef DumbTODParams Params;
- DumbTOD(const Params *p);
+ DumbTOD(const Params &p);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Tick read(PacketPtr pkt) override;
#include "sim/faults.hh"
#include "sim/system.hh"
-Iob::Iob(const Params *p)
- : PioDevice(p), ic(p->platform->intrctrl)
+Iob::Iob(const Params &p)
+ : PioDevice(p), ic(p.platform->intrctrl)
{
iobManAddr = ULL(0x9800000000);
iobManSize = ULL(0x0100000000);
iobJBusAddr = ULL(0x9F00000000);
iobJBusSize = ULL(0x0100000000);
- assert(params()->system->threads.size() <= MaxNiagaraProcs);
+ assert(params().system->threads.size() <= MaxNiagaraProcs);
- pioDelay = p->pio_latency;
+ pioDelay = p.pio_latency;
for (int x = 0; x < NumDeviceIds; ++x) {
intMan[x].cpu = 0;
}
Iob *
-IobParams::create()
+IobParams::create() const
{
- return new Iob(this);
+ return new Iob(*this);
}
public:
typedef IobParams Params;
- Iob(const Params *p);
+ Iob(const Params &p);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Tick read(PacketPtr pkt) override;
#include "sim/byteswap.hh"
#include "sim/system.hh"
-MmDisk::MmDisk(const Params *p)
- : BasicPioDevice(p, p->image->size() * SectorSize),
- image(p->image), curSector((off_t)-1), dirty(false)
+MmDisk::MmDisk(const Params &p)
+ : BasicPioDevice(p, p.image->size() * SectorSize),
+ image(p.image), curSector((off_t)-1), dirty(false)
{
std::memset(&diskData, 0, SectorSize);
}
}
MmDisk *
-MmDiskParams::create()
+MmDiskParams::create() const
{
- return new MmDisk(this);
+ return new MmDisk(*this);
}
public:
typedef MmDiskParams Params;
- MmDisk(const Params *p);
+ MmDisk(const Params &p);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
Tick read(PacketPtr pkt) override;
using namespace std;
-T1000::T1000(const Params *p)
- : Platform(p), system(p->system)
+T1000::T1000(const Params &p)
+ : Platform(p), system(p.system)
{}
void
}
T1000 *
-T1000Params::create()
+T1000Params::create() const
{
- return new T1000(this);
+ return new T1000(*this);
}
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
- T1000(const Params *p);
+ T1000(const Params &p);
/**
* Cause the cpu to post a serial interrupt to the CPU.
//
// Raw Disk image
//
-RawDiskImage::RawDiskImage(const Params* p)
+RawDiskImage::RawDiskImage(const Params &p)
: DiskImage(p), disk_size(0)
-{ open(p->image_file, p->read_only); }
+{
+ open(p.image_file, p.read_only);
+}
RawDiskImage::~RawDiskImage()
-{ close(); }
+{
+ close();
+}
void
RawDiskImage::notifyFork()
if (initialized && !readonly)
panic("Attempting to fork system with read-write raw disk image.");
- const Params *p(dynamic_cast<const Params *>(params()));
+ const Params &p = dynamic_cast<const Params &>(params());
close();
- open(p->image_file, p->read_only);
+ open(p.image_file, p.read_only);
}
void
}
RawDiskImage *
-RawDiskImageParams::create()
+RawDiskImageParams::create() const
{
- return new RawDiskImage(this);
+ return new RawDiskImage(*this);
}
////////////////////////////////////////////////////////////////////////
const uint32_t CowDiskImage::VersionMajor = 1;
const uint32_t CowDiskImage::VersionMinor = 0;
-CowDiskImage::CowDiskImage(const Params *p)
- : DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
+CowDiskImage::CowDiskImage(const Params &p)
+ : DiskImage(p), filename(p.image_file), child(p.child), table(NULL)
{
if (filename.empty()) {
- initSectorTable(p->table_size);
+ initSectorTable(p.table_size);
} else {
if (!open(filename)) {
- if (p->read_only)
+ if (p.read_only)
fatal("could not open read-only file");
- initSectorTable(p->table_size);
+ initSectorTable(p.table_size);
}
- if (!p->read_only)
+ if (!p.read_only)
registerExitCallback([this]() { save(); });
}
}
void
CowDiskImage::notifyFork()
{
- if (!dynamic_cast<const Params *>(params())->read_only &&
+ if (!dynamic_cast<const Params &>(params()).read_only &&
!filename.empty()) {
inform("Disabling saving of COW image in forked child process.\n");
filename = "";
}
CowDiskImage *
-CowDiskImageParams::create()
+CowDiskImageParams::create() const
{
- return new CowDiskImage(this);
+ return new CowDiskImage(*this);
}
public:
typedef DiskImageParams Params;
- DiskImage(const Params *p) : SimObject(p), initialized(false) {}
+ DiskImage(const Params &p) : SimObject(p), initialized(false) {}
virtual ~DiskImage() {}
virtual std::streampos size() const = 0;
public:
typedef RawDiskImageParams Params;
- RawDiskImage(const Params *p);
+ RawDiskImage(const Params &p);
~RawDiskImage();
void notifyFork() override;
public:
typedef CowDiskImageParams Params;
- CowDiskImage(const Params *p);
+ CowDiskImage(const Params &p);
~CowDiskImage();
void notifyFork() override;
{
}
-IdeController::IdeController(Params *p)
+IdeController::IdeController(const Params &p)
: PciDevice(p), primary(name() + ".primary", BARSize[0], BARSize[1]),
secondary(name() + ".secondary", BARSize[2], BARSize[3]),
bmiAddr(0), bmiSize(BARSize[4]),
secondaryTiming(htole(timeRegWithDecodeEn)),
deviceTiming(0), udmaControl(0), udmaTiming(0), ideConfig(0),
ioEnabled(false), bmEnabled(false),
- ioShift(p->io_shift), ctrlOffset(p->ctrl_offset)
+ ioShift(p.io_shift), ctrlOffset(p.ctrl_offset)
{
// Assign the disks to channels
- for (int i = 0; i < params()->disks.size(); i++) {
- if (!params()->disks[i])
+ for (int i = 0; i < params().disks.size(); i++) {
+ if (!params().disks[i])
continue;
switch (i) {
case 0:
- primary.device0 = params()->disks[0];
+ primary.device0 = params().disks[0];
break;
case 1:
- primary.device1 = params()->disks[1];
+ primary.device1 = params().disks[1];
break;
case 2:
- secondary.device0 = params()->disks[2];
+ secondary.device0 = params().disks[2];
break;
case 3:
- secondary.device1 = params()->disks[3];
+ secondary.device1 = params().disks[3];
break;
default:
panic("IDE controllers support a maximum "
"of 4 devices attached!\n");
}
// Arbitrarily set the chunk size to 4K.
- params()->disks[i]->setController(this, 4 * 1024);
+ params().disks[i]->setController(this, 4 * 1024);
}
primary.select(false);
}
IdeController *
-IdeControllerParams::create()
+IdeControllerParams::create() const
{
- return new IdeController(this);
+ return new IdeController(*this);
}
public:
typedef IdeControllerParams Params;
- const Params *params() const { return (const Params *)_params; }
- IdeController(Params *p);
+ const Params ¶ms() const { return (const Params &)_params; }
+ IdeController(const Params &p);
/** See if a disk is selected based on its pointer */
bool isDiskSelected(IdeDisk *diskPtr);
#include "sim/core.hh"
#include "sim/sim_object.hh"
-IdeDisk::IdeDisk(const Params *p)
- : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
+IdeDisk::IdeDisk(const Params &p)
+ : SimObject(p), ctrl(NULL), image(p.image), diskDelay(p.delay),
dmaTransferEvent([this]{ doDmaTransfer(); }, name()),
dmaReadCG(NULL),
dmaReadWaitEvent([this]{ doDmaRead(); }, name()),
dmaWriteEvent([this]{ dmaWriteDone(); }, name())
{
// Reset the device state
- reset(p->driveID);
+ reset(p.driveID);
// fill out the drive ID structure
memset(&driveID, 0, sizeof(struct ataparams));
}
IdeDisk *
-IdeDiskParams::create()
+IdeDiskParams::create() const
{
- return new IdeDisk(this);
+ return new IdeDisk(*this);
}
public:
typedef IdeDiskParams Params;
- IdeDisk(const Params *p);
+ IdeDisk(const Params &p);
/**
* Delete the data buffer.
using namespace std;
-SimpleDisk::SimpleDisk(const Params *p)
- : SimObject(p), system(p->system), image(p->disk)
+SimpleDisk::SimpleDisk(const Params &p)
+ : SimObject(p), system(p.system), image(p.disk)
{}
SimpleDisk::~SimpleDisk()
}
SimpleDisk *
-SimpleDiskParams::create()
+SimpleDiskParams::create() const
{
- return new SimpleDisk(this);
+ return new SimpleDisk(*this);
}
public:
typedef SimpleDiskParams Params;
- SimpleDisk(const Params *p);
+ SimpleDisk(const Params &p);
~SimpleDisk();
void read(Addr addr, baddr_t block, int count) const;
}
-VirtIODeviceBase::VirtIODeviceBase(Params *params, DeviceId id,
+VirtIODeviceBase::VirtIODeviceBase(const Params ¶ms, DeviceId id,
size_t config_size, FeatureBits features)
: SimObject(params),
guestFeatures(0),
- byteOrder(params->byte_order),
+ byteOrder(params.byte_order),
deviceId(id), configSize(config_size), deviceFeatures(features),
_deviceStatus(0), _queueSelect(0)
{
}
-VirtIODummyDevice::VirtIODummyDevice(VirtIODummyDeviceParams *params)
+VirtIODummyDevice::VirtIODummyDevice(const VirtIODummyDeviceParams ¶ms)
: VirtIODeviceBase(params, ID_INVALID, 0, 0)
{
}
VirtIODummyDevice *
-VirtIODummyDeviceParams::create()
+VirtIODummyDeviceParams::create() const
{
- return new VirtIODummyDevice(this);
+ return new VirtIODummyDevice(*this);
}
EndBitUnion(DeviceStatus)
typedef VirtIODeviceBaseParams Params;
- VirtIODeviceBase(Params *params, DeviceId id, size_t config_size,
+ VirtIODeviceBase(const Params ¶ms, DeviceId id, size_t config_size,
FeatureBits features);
virtual ~VirtIODeviceBase();
class VirtIODummyDevice : public VirtIODeviceBase
{
public:
- VirtIODummyDevice(VirtIODummyDeviceParams *params);
+ VirtIODummyDevice(const VirtIODummyDeviceParams ¶ms);
protected:
/** VirtIO device ID */
#include "params/VirtIOBlock.hh"
#include "sim/system.hh"
-VirtIOBlock::VirtIOBlock(Params *params)
+VirtIOBlock::VirtIOBlock(const Params ¶ms)
: VirtIODeviceBase(params, ID_BLOCK, sizeof(Config), 0),
- qRequests(params->system->physProxy, byteOrder,
- params->queueSize, *this),
- image(*params->image)
+ qRequests(params.system->physProxy, byteOrder,
+ params.queueSize, *this),
+ image(*params.image)
{
registerQueue(qRequests);
}
VirtIOBlock *
-VirtIOBlockParams::create()
+VirtIOBlockParams::create() const
{
- return new VirtIOBlock(this);
+ return new VirtIOBlock(*this);
}
{
public:
typedef VirtIOBlockParams Params;
- VirtIOBlock(Params *params);
+ VirtIOBlock(const Params ¶ms);
virtual ~VirtIOBlock();
void readConfig(PacketPtr pkt, Addr cfgOffset);
#include "params/VirtIOConsole.hh"
#include "sim/system.hh"
-VirtIOConsole::VirtIOConsole(Params *params)
+VirtIOConsole::VirtIOConsole(const Params ¶ms)
: VirtIODeviceBase(params, ID_CONSOLE, sizeof(Config), F_SIZE),
- qRecv(params->system->physProxy, byteOrder, params->qRecvSize, *this),
- qTrans(params->system->physProxy, byteOrder, params->qTransSize, *this),
- device(*params->device)
+ qRecv(params.system->physProxy, byteOrder, params.qRecvSize, *this),
+ qTrans(params.system->physProxy, byteOrder, params.qTransSize, *this),
+ device(*params.device)
{
registerQueue(qRecv);
registerQueue(qTrans);
}
VirtIOConsole *
-VirtIOConsoleParams::create()
+VirtIOConsoleParams::create() const
{
- return new VirtIOConsole(this);
+ return new VirtIOConsole(*this);
}
{
public:
typedef VirtIOConsoleParams Params;
- VirtIOConsole(Params *params);
+ VirtIOConsole(const Params ¶ms);
virtual ~VirtIOConsole();
void readConfig(PacketPtr pkt, Addr cfgOffset);
#undef P9MSG
-VirtIO9PBase::VirtIO9PBase(Params *params)
+VirtIO9PBase::VirtIO9PBase(const Params ¶ms)
: VirtIODeviceBase(params, ID_9P,
- sizeof(Config) + params->tag.size(),
+ sizeof(Config) + params.tag.size(),
F_MOUNT_TAG),
- queue(params->system->physProxy, byteOrder, params->queueSize, *this)
+ queue(params.system->physProxy, byteOrder, params.queueSize, *this)
{
config.reset((Config *)
operator new(configSize));
- config->len = htog(params->tag.size(), byteOrder);
- memcpy(config->tag, params->tag.c_str(), params->tag.size());
+ config->len = htog(params.tag.size(), byteOrder);
+ memcpy(config->tag, params.tag.c_str(), params.tag.size());
registerQueue(queue);
}
}
-VirtIO9PProxy::VirtIO9PProxy(Params *params)
+VirtIO9PProxy::VirtIO9PProxy(const Params ¶ms)
: VirtIO9PBase(params), deviceUsed(false)
{
}
-VirtIO9PDiod::VirtIO9PDiod(Params *params)
+VirtIO9PDiod::VirtIO9PDiod(const Params ¶ms)
: VirtIO9PProxy(params),
fd_to_diod(-1), fd_from_diod(-1), diod_pid(-1)
{
void
VirtIO9PDiod::startDiod()
{
- const Params *p(dynamic_cast<const Params *>(params()));
+ const Params &p = dynamic_cast<const Params &>(params());
int pipe_rfd[2];
int pipe_wfd[2];
const int DIOD_RFD = 3;
const int DIOD_WFD = 4;
- const char *diod(p->diod.c_str());
+ const char *diod(p.diod.c_str());
- DPRINTF(VIO9P, "Using diod at %s \n", p->diod.c_str());
+ DPRINTF(VIO9P, "Using diod at %s \n", p.diod.c_str());
if (pipe(pipe_rfd) == -1 || pipe(pipe_wfd) == -1)
panic("Failed to create DIOD pipes: %i\n", errno);
memset(&socket_address, 0, sizeof(struct sockaddr_un));
socket_address.sun_family = AF_UNIX;
- const std::string socket_path = simout.resolve(p->socketPath);
+ const std::string socket_path = simout.resolve(p.socketPath);
fatal_if(!OutputDirectory::isAbsolute(socket_path), "Please make the" \
" output directory an absolute path, else diod will fail!\n");
"-f", // start in foreground
"-r", "3", // setup read FD
"-w", "4", // setup write FD
- "-e", p->root.c_str(), // path to export
+ "-e", p.root.c_str(), // path to export
"-n", // disable security
"-S", // squash all users
"-l", socket_path.c_str(), // pass the socket
}
VirtIO9PDiod *
-VirtIO9PDiodParams::create()
+VirtIO9PDiodParams::create() const
{
- return new VirtIO9PDiod(this);
+ return new VirtIO9PDiod(*this);
}
-VirtIO9PSocket::VirtIO9PSocket(Params *params)
+VirtIO9PSocket::VirtIO9PSocket(const Params ¶ms)
: VirtIO9PProxy(params), fdSocket(-1)
{
}
void
VirtIO9PSocket::connectSocket()
{
- const Params &p(dynamic_cast<const Params &>(*params()));
+ const Params &p = dynamic_cast<const Params &>(params());
int ret;
struct addrinfo hints, *result;
VirtIO9PSocket *
-VirtIO9PSocketParams::create()
+VirtIO9PSocketParams::create() const
{
- return new VirtIO9PSocket(this);
+ return new VirtIO9PSocket(*this);
}
{
public:
typedef VirtIO9PBaseParams Params;
- VirtIO9PBase(Params *params);
+ VirtIO9PBase(const Params ¶ms);
virtual ~VirtIO9PBase();
void readConfig(PacketPtr pkt, Addr cfgOffset);
{
public:
typedef VirtIO9PProxyParams Params;
- VirtIO9PProxy(Params *params);
+ VirtIO9PProxy(const Params ¶ms);
virtual ~VirtIO9PProxy();
void serialize(CheckpointOut &cp) const override;
{
public:
typedef VirtIO9PDiodParams Params;
- VirtIO9PDiod(Params *params);
+ VirtIO9PDiod(const Params ¶ms);
virtual ~VirtIO9PDiod();
void startup();
{
public:
typedef VirtIO9PSocketParams Params;
- VirtIO9PSocket(Params *params);
+ VirtIO9PSocket(const Params ¶ms);
virtual ~VirtIO9PSocket();
void startup();
#include "mem/packet_access.hh"
#include "params/PciVirtIO.hh"
-PciVirtIO::PciVirtIO(const Params *params)
+PciVirtIO::PciVirtIO(const Params ¶ms)
: PciDevice(params), queueNotify(0), interruptDeliveryPending(false),
- vio(*params->vio)
+ vio(*params.vio)
{
// Override the subsystem ID with the device ID from VirtIO
config.subsystemID = htole(vio.deviceId);
}
PciVirtIO *
-PciVirtIOParams::create()
+PciVirtIOParams::create() const
{
- return new PciVirtIO(this);
+ return new PciVirtIO(*this);
}
{
public:
typedef PciVirtIOParams Params;
- PciVirtIO(const Params *params);
+ PciVirtIO(const Params ¶ms);
virtual ~PciVirtIO();
Tick read(PacketPtr pkt);
}
X86ISA::Cmos *
-CmosParams::create()
+CmosParams::create() const
{
- return new X86ISA::Cmos(this);
+ return new X86ISA::Cmos(*this);
}
public:
typedef CmosParams Params;
- Cmos(const Params *p) : BasicPioDevice(p, 2), latency(p->pio_latency),
- rtc(this, name() + ".rtc", p->time, true, ULL(5000000000),
- p->port_int_pin_connection_count)
+ Cmos(const Params &p) : BasicPioDevice(p, 2), latency(p.pio_latency),
+ rtc(this, name() + ".rtc", p.time, true, ULL(5000000000),
+ p.port_int_pin_connection_count)
{
memset(regs, 0, numRegs * sizeof(uint8_t));
address = 0;
const uint8_t NumOutputBits = 14;
-X86ISA::I8042::I8042(Params *p)
+X86ISA::I8042::I8042(const Params &p)
: BasicPioDevice(p, 0), // pioSize arg is dummy value... not used
- latency(p->pio_latency),
- dataPort(p->data_port), commandPort(p->command_port),
+ latency(p.pio_latency),
+ dataPort(p.data_port), commandPort(p.command_port),
statusReg(0), commandByte(0), dataReg(0), lastCommand(NoCommand),
- mouse(p->mouse), keyboard(p->keyboard)
+ mouse(p.mouse), keyboard(p.keyboard)
{
fatal_if(!mouse, "The i8042 model requires a mouse instance");
fatal_if(!keyboard, "The i8042 model requires a keyboard instance");
commandByte.passedSelfTest = 1;
commandByte.keyboardFullInt = 1;
- for (int i = 0; i < p->port_keyboard_int_pin_connection_count; i++) {
+ for (int i = 0; i < p.port_keyboard_int_pin_connection_count; i++) {
keyboardIntPin.push_back(new IntSourcePin<I8042>(
csprintf("%s.keyboard_int_pin[%d]", name(), i), i, this));
}
- for (int i = 0; i < p->port_mouse_int_pin_connection_count; i++) {
+ for (int i = 0; i < p.port_mouse_int_pin_connection_count; i++) {
mouseIntPin.push_back(new IntSourcePin<I8042>(
csprintf("%s.mouse_int_pin[%d]", name(), i), i, this));
}
}
X86ISA::I8042 *
-I8042Params::create()
+I8042Params::create() const
{
- return new X86ISA::I8042(this);
+ return new X86ISA::I8042(*this);
}
public:
typedef I8042Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- I8042(Params *p);
+ I8042(const Params &p);
Port &
getPort(const std::string &if_name, PortID idx=InvalidPortID) override
#include "mem/packet_access.hh"
#include "sim/system.hh"
-X86ISA::I82094AA::I82094AA(Params *p)
- : BasicPioDevice(p, 20), extIntPic(p->external_int_pic),
+X86ISA::I82094AA::I82094AA(const Params &p)
+ : BasicPioDevice(p, 20), extIntPic(p.external_int_pic),
lowestPriorityOffset(0),
- intRequestPort(name() + ".int_request", this, this, p->int_latency)
+ intRequestPort(name() + ".int_request", this, this, p.int_latency)
{
// This assumes there's only one I/O APIC in the system and since the apic
// id is stored in a 8-bit field with 0xff meaning broadcast, the id must
// be less than 0xff
- assert(p->apic_id < 0xff);
- initialApicId = id = p->apic_id;
+ assert(p.apic_id < 0xff);
+ initialApicId = id = p.apic_id;
arbId = id;
regSel = 0;
RedirTableEntry entry = 0;
pinStates[i] = false;
}
- for (int i = 0; i < p->port_inputs_connection_count; i++)
+ for (int i = 0; i < p.port_inputs_connection_count; i++)
inputs.push_back(new IntSinkPin<I82094AA>(
csprintf("%s.inputs[%d]", name(), i), i, this));
}
}
X86ISA::I82094AA *
-I82094AAParams::create()
+I82094AAParams::create() const
{
- return new X86ISA::I82094AA(this);
+ return new X86ISA::I82094AA(*this);
}
public:
typedef I82094AAParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- I82094AA(Params *p);
+ I82094AA(const Params &p);
void init() override;
}
X86ISA::I8237 *
-I8237Params::create()
+I8237Params::create() const
{
- return new X86ISA::I8237(this);
+ return new X86ISA::I8237(*this);
}
{
protected:
Tick latency;
- uint8_t maskReg;
+ uint8_t maskReg = 0;
public:
typedef I8237Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- I8237(Params *p) : BasicPioDevice(p, 16), latency(p->pio_latency), maskReg(0)
- {
- }
- Tick read(PacketPtr pkt) override;
+ I8237(const Params &p) : BasicPioDevice(p, 16), latency(p.pio_latency) {}
+ Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override;
}
X86ISA::I8254 *
-I8254Params::create()
+I8254Params::create() const
{
- return new X86ISA::I8254(this);
+ return new X86ISA::I8254(*this);
}
return BasicPioDevice::getPort(if_name, idx);
}
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- I8254(Params *p) : BasicPioDevice(p, 4), latency(p->pio_latency),
- pit(p->name, this)
+ I8254(const Params &p) : BasicPioDevice(p, 4), latency(p.pio_latency),
+ pit(p.name, this)
{
- for (int i = 0; i < p->port_int_pin_connection_count; i++) {
+ for (int i = 0; i < p.port_int_pin_connection_count; i++) {
intPin.push_back(new IntSourcePin<I8254>(csprintf(
"%s.int_pin[%d]", name(), i), i, this));
}
}
- Tick read(PacketPtr pkt) override;
+ Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
bool
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-X86ISA::I8259::I8259(Params * p)
+X86ISA::I8259::I8259(const Params &p)
: BasicPioDevice(p, 2),
- latency(p->pio_latency),
- mode(p->mode), slave(p->slave),
+ latency(p.pio_latency),
+ mode(p.mode), slave(p.slave),
IRR(0), ISR(0), IMR(0),
readIRR(true), initControlWord(0), autoEOI(false)
{
- for (int i = 0; i < p->port_output_connection_count; i++) {
+ for (int i = 0; i < p.port_output_connection_count; i++) {
output.push_back(new IntSourcePin<I8259>(
csprintf("%s.output[%d]", name(), i), i, this));
}
- int in_count = p->port_inputs_connection_count;
+ int in_count = p.port_inputs_connection_count;
panic_if(in_count >= NumLines,
"I8259 only supports 8 inputs, but there are %d.", in_count);
for (int i = 0; i < in_count; i++) {
}
X86ISA::I8259 *
-I8259Params::create()
+I8259Params::create() const
{
- return new X86ISA::I8259(this);
+ return new X86ISA::I8259(*this);
}
public:
typedef I8259Params Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- I8259(Params * p);
+ I8259(const Params &p);
Port &
getPort(const std::string &if_name, PortID idx=InvalidPortID) override
#include "dev/x86/south_bridge.hh"
#include "sim/system.hh"
-Pc::Pc(const Params *p)
- : Platform(p), system(p->system)
+Pc::Pc(const Params &p)
+ : Platform(p), system(p.system)
{
southBridge = NULL;
}
}
Pc *
-PcParams::create()
+PcParams::create() const
{
- return new Pc(this);
+ return new Pc(*this);
}
*/
void init() override;
- Pc(const Params *p);
+ Pc(const Params &p);
public:
void postConsoleInt() override;
using namespace X86ISA;
-SouthBridge::SouthBridge(const Params *p) : SimObject(p),
- platform(p->platform), pit(p->pit), pic1(p->pic1), pic2(p->pic2),
- cmos(p->cmos), speaker(p->speaker), ioApic(p->io_apic)
+SouthBridge::SouthBridge(const Params &p) : SimObject(p),
+ platform(p.platform), pit(p.pit), pic1(p.pic1), pic2(p.pic2),
+ cmos(p.cmos), speaker(p.speaker), ioApic(p.io_apic)
{
// Let the platform know where we are
Pc * pc = dynamic_cast<Pc *>(platform);
}
SouthBridge *
-SouthBridgeParams::create()
+SouthBridgeParams::create() const
{
- return new SouthBridge(this);
+ return new SouthBridge(*this);
}
public:
typedef SouthBridgeParams Params;
- SouthBridge(const Params *p);
+ SouthBridge(const Params &p);
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
};
}
X86ISA::Speaker *
-PcSpeakerParams::create()
+PcSpeakerParams::create() const
{
- return new X86ISA::Speaker(this);
+ return new X86ISA::Speaker(*this);
}
public:
typedef PcSpeakerParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Speaker(Params *p) : BasicPioDevice(p, 1),
- latency(p->pio_latency), controlVal(0), timer(p->i8254)
+ Speaker(const Params &p) : BasicPioDevice(p, 1),
+ latency(p.pio_latency), controlVal(0), timer(p.i8254)
{
}
* Scoreboard/Schedule stage interface.
*/
ScoreboardCheckToSchedule::ScoreboardCheckToSchedule(const ComputeUnitParams
- *p)
+ &p)
{
- int num_func_units = p->num_SIMDs + p->num_scalar_cores
- + p->num_global_mem_pipes + p->num_shared_mem_pipes
- + p->num_scalar_mem_pipes;
+ int num_func_units = p.num_SIMDs + p.num_scalar_cores
+ + p.num_global_mem_pipes + p.num_shared_mem_pipes
+ + p.num_scalar_mem_pipes;
_readyWFs.resize(num_func_units);
for (auto &func_unit_wf_list : _readyWFs) {
- func_unit_wf_list.reserve(p->n_wf);
+ func_unit_wf_list.reserve(p.n_wf);
}
}
/**
* Schedule/Execute stage interface.
*/
-ScheduleToExecute::ScheduleToExecute(const ComputeUnitParams *p)
+ScheduleToExecute::ScheduleToExecute(const ComputeUnitParams &p)
{
- int num_func_units = p->num_SIMDs + p->num_scalar_cores
- + p->num_global_mem_pipes + p->num_shared_mem_pipes
- + p->num_scalar_mem_pipes;
+ int num_func_units = p.num_SIMDs + p.num_scalar_cores
+ + p.num_global_mem_pipes + p.num_shared_mem_pipes
+ + p.num_scalar_mem_pipes;
_readyInsts.resize(num_func_units, nullptr);
_dispatchStatus.resize(num_func_units, EMPTY);
}
{
public:
ScoreboardCheckToSchedule() = delete;
- ScoreboardCheckToSchedule(const ComputeUnitParams *p);
+ ScoreboardCheckToSchedule(const ComputeUnitParams &p);
void reset() override;
/**
* Mark the WF as ready for execution on a particular functional
{
public:
ScheduleToExecute() = delete;
- ScheduleToExecute(const ComputeUnitParams *p);
+ ScheduleToExecute(const ComputeUnitParams &p);
void reset() override;
GPUDynInstPtr& readyInst(int func_unit_id);
/**
#include "sim/process.hh"
#include "sim/sim_exit.hh"
-ComputeUnit::ComputeUnit(const Params *p) : ClockedObject(p),
- numVectorGlobalMemUnits(p->num_global_mem_pipes),
- numVectorSharedMemUnits(p->num_shared_mem_pipes),
- numScalarMemUnits(p->num_scalar_mem_pipes),
- numVectorALUs(p->num_SIMDs),
- numScalarALUs(p->num_scalar_cores),
- vrfToCoalescerBusWidth(p->vrf_to_coalescer_bus_width),
- coalescerToVrfBusWidth(p->coalescer_to_vrf_bus_width),
- registerManager(p->register_manager),
+ComputeUnit::ComputeUnit(const Params &p) : ClockedObject(p),
+ numVectorGlobalMemUnits(p.num_global_mem_pipes),
+ numVectorSharedMemUnits(p.num_shared_mem_pipes),
+ numScalarMemUnits(p.num_scalar_mem_pipes),
+ numVectorALUs(p.num_SIMDs),
+ numScalarALUs(p.num_scalar_cores),
+ vrfToCoalescerBusWidth(p.vrf_to_coalescer_bus_width),
+ coalescerToVrfBusWidth(p.coalescer_to_vrf_bus_width),
+ registerManager(p.register_manager),
fetchStage(p, *this),
scoreboardCheckStage(p, *this, scoreboardCheckToSchedule),
scheduleStage(p, *this, scoreboardCheckToSchedule, scheduleToExecute),
scalarMemoryPipe(p, *this),
tickEvent([this]{ exec(); }, "Compute unit tick event",
false, Event::CPU_Tick_Pri),
- cu_id(p->cu_id),
- vrf(p->vector_register_file), srf(p->scalar_register_file),
- simdWidth(p->simd_width),
- spBypassPipeLength(p->spbypass_pipe_length),
- dpBypassPipeLength(p->dpbypass_pipe_length),
- scalarPipeStages(p->scalar_pipe_length),
- operandNetworkLength(p->operand_network_length),
- issuePeriod(p->issue_period),
- vrf_gm_bus_latency(p->vrf_gm_bus_latency),
- srf_scm_bus_latency(p->srf_scm_bus_latency),
- vrf_lm_bus_latency(p->vrf_lm_bus_latency),
- perLaneTLB(p->perLaneTLB), prefetchDepth(p->prefetch_depth),
- prefetchStride(p->prefetch_stride), prefetchType(p->prefetch_prev_type),
- debugSegFault(p->debugSegFault),
- functionalTLB(p->functionalTLB), localMemBarrier(p->localMemBarrier),
- countPages(p->countPages),
- req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
- resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
- _requestorId(p->system->getRequestorId(this, "ComputeUnit")),
- lds(*p->localDataStore), gmTokenPort(name() + ".gmTokenPort", this),
+ cu_id(p.cu_id),
+ vrf(p.vector_register_file), srf(p.scalar_register_file),
+ simdWidth(p.simd_width),
+ spBypassPipeLength(p.spbypass_pipe_length),
+ dpBypassPipeLength(p.dpbypass_pipe_length),
+ scalarPipeStages(p.scalar_pipe_length),
+ operandNetworkLength(p.operand_network_length),
+ issuePeriod(p.issue_period),
+ vrf_gm_bus_latency(p.vrf_gm_bus_latency),
+ srf_scm_bus_latency(p.srf_scm_bus_latency),
+ vrf_lm_bus_latency(p.vrf_lm_bus_latency),
+ perLaneTLB(p.perLaneTLB), prefetchDepth(p.prefetch_depth),
+ prefetchStride(p.prefetch_stride), prefetchType(p.prefetch_prev_type),
+ debugSegFault(p.debugSegFault),
+ functionalTLB(p.functionalTLB), localMemBarrier(p.localMemBarrier),
+ countPages(p.countPages),
+ req_tick_latency(p.mem_req_latency * p.clk_domain->clockPeriod()),
+ resp_tick_latency(p.mem_resp_latency * p.clk_domain->clockPeriod()),
+ _requestorId(p.system->getRequestorId(this, "ComputeUnit")),
+ lds(*p.localDataStore), gmTokenPort(name() + ".gmTokenPort", this),
ldsPort(csprintf("%s-port", name()), this),
scalarDataPort(csprintf("%s-port", name()), this),
scalarDTLBPort(csprintf("%s-port", name()), this),
sqcPort(csprintf("%s-port", name()), this),
sqcTLBPort(csprintf("%s-port", name()), this),
- _cacheLineSize(p->system->cacheLineSize()),
- _numBarrierSlots(p->num_barrier_slots),
- globalSeqNum(0), wavefrontSize(p->wf_size),
+ _cacheLineSize(p.system->cacheLineSize()),
+ _numBarrierSlots(p.num_barrier_slots),
+ globalSeqNum(0), wavefrontSize(p.wf_size),
scoreboardCheckToSchedule(p),
scheduleToExecute(p)
{
* to_long() or to_ullong() so we can have wavefrontSize greater than 64b,
* however until that is done this assert is required.
*/
- fatal_if(p->wf_size > std::numeric_limits<unsigned long long>::digits ||
- p->wf_size <= 0,
+ fatal_if(p.wf_size > std::numeric_limits<unsigned long long>::digits ||
+ p.wf_size <= 0,
"WF size is larger than the host can support");
fatal_if(!isPowerOf2(wavefrontSize),
"Wavefront size should be a power of 2");
/ coalescerToVrfBusWidth;
// Initialization: all WF slots are assumed STOPPED
- idleWfs = p->n_wf * numVectorALUs;
+ idleWfs = p.n_wf * numVectorALUs;
lastVaddrWF.resize(numVectorALUs);
wfList.resize(numVectorALUs);
- wfBarrierSlots.resize(p->num_barrier_slots, WFBarrier());
+ wfBarrierSlots.resize(p.num_barrier_slots, WFBarrier());
- for (int i = 0; i < p->num_barrier_slots; ++i) {
+ for (int i = 0; i < p.num_barrier_slots; ++i) {
freeBarrierIds.insert(i);
}
for (int j = 0; j < numVectorALUs; ++j) {
- lastVaddrWF[j].resize(p->n_wf);
+ lastVaddrWF[j].resize(p.n_wf);
- for (int i = 0; i < p->n_wf; ++i) {
+ for (int i = 0; i < p.n_wf; ++i) {
lastVaddrWF[j][i].resize(wfSize());
- wfList[j].push_back(p->wavefronts[j * p->n_wf + i]);
+ wfList[j].push_back(p.wavefronts[j * p.n_wf + i]);
wfList[j][i]->setParent(this);
for (int k = 0; k < wfSize(); ++k) {
lds.setParent(this);
- if (p->execPolicy == "OLDEST-FIRST") {
+ if (p.execPolicy == "OLDEST-FIRST") {
exec_policy = EXEC_POLICY::OLDEST;
- } else if (p->execPolicy == "ROUND-ROBIN") {
+ } else if (p.execPolicy == "ROUND-ROBIN") {
exec_policy = EXEC_POLICY::RR;
} else {
fatal("Invalid WF execution policy (CU)\n");
}
- for (int i = 0; i < p->port_memory_port_connection_count; ++i) {
+ for (int i = 0; i < p.port_memory_port_connection_count; ++i) {
memPort.emplace_back(csprintf("%s-port%d", name(), i), this, i);
}
- for (int i = 0; i < p->port_translation_port_connection_count; ++i) {
+ for (int i = 0; i < p.port_translation_port_connection_count; ++i) {
tlbPort.emplace_back(csprintf("%s-port%d", name(), i), this, i);
}
// Setup tokens for response ports. The number of tokens in memPortTokens
// is the total token count for the entire vector port (i.e., this CU).
- memPortTokens = new TokenManager(p->max_cu_tokens);
+ memPortTokens = new TokenManager(p.max_cu_tokens);
registerExitCallback([this]() { exitCallback(); });
}
ComputeUnit*
-ComputeUnitParams::create()
+ComputeUnitParams::create() const
{
- return new ComputeUnit(this);
+ return new ComputeUnit(*this);
}
bool
void insertInPipeMap(Wavefront *w);
void deleteFromPipeMap(Wavefront *w);
- ComputeUnit(const Params *p);
+ ComputeUnit(const Params &p);
~ComputeUnit();
// Timing Functions
#include "sim/syscall_emul_buf.hh"
#include "sim/system.hh"
-GPUDispatcher::GPUDispatcher(const Params *p)
+GPUDispatcher::GPUDispatcher(const Params &p)
: SimObject(p), shader(nullptr), gpuCmdProc(nullptr),
tickEvent([this]{ exec(); },
"GPU Dispatcher tick", false, Event::CPU_Tick_Pri),
}
}
-GPUDispatcher *GPUDispatcherParams::create()
+GPUDispatcher *
+GPUDispatcherParams::create() const
{
- return new GPUDispatcher(this);
+ return new GPUDispatcher(*this);
}
public:
typedef GPUDispatcherParams Params;
- GPUDispatcher(const Params *p);
+ GPUDispatcher(const Params &p);
~GPUDispatcher();
void serialize(CheckpointOut &cp) const override;
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
-ExecStage::ExecStage(const ComputeUnitParams *p, ComputeUnit &cu,
+ExecStage::ExecStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScheduleToExecute &from_schedule)
: computeUnit(cu), fromSchedule(from_schedule),
lastTimeInstExecuted(false),
class ExecStage
{
public:
- ExecStage(const ComputeUnitParams* p, ComputeUnit &cu,
+ ExecStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScheduleToExecute &from_schedule);
~ExecStage() { }
void init();
#include "gpu-compute/compute_unit.hh"
#include "gpu-compute/wavefront.hh"
-FetchStage::FetchStage(const ComputeUnitParams* p, ComputeUnit &cu)
- : numVectorALUs(p->num_SIMDs), computeUnit(cu),
+FetchStage::FetchStage(const ComputeUnitParams &p, ComputeUnit &cu)
+ : numVectorALUs(p.num_SIMDs), computeUnit(cu),
_name(cu.name() + ".FetchStage")
{
for (int j = 0; j < numVectorALUs; ++j) {
class FetchStage
{
public:
- FetchStage(const ComputeUnitParams* p, ComputeUnit &cu);
+ FetchStage(const ComputeUnitParams &p, ComputeUnit &cu);
~FetchStage();
void init();
void exec();
uint32_t FetchUnit::globalFetchUnitID;
-FetchUnit::FetchUnit(const ComputeUnitParams *p, ComputeUnit &cu)
+FetchUnit::FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
: timingSim(true), computeUnit(cu), fetchScheduler(p),
- waveList(nullptr), fetchDepth(p->fetch_depth)
+ waveList(nullptr), fetchDepth(p.fetch_depth)
{
}
class FetchUnit
{
public:
- FetchUnit(const ComputeUnitParams* p, ComputeUnit &cu);
+ FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu);
~FetchUnit();
void init();
void exec();
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
-GlobalMemPipeline::GlobalMemPipeline(const ComputeUnitParams* p,
+GlobalMemPipeline::GlobalMemPipeline(const ComputeUnitParams &p,
ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".GlobalMemPipeline"),
- gmQueueSize(p->global_mem_queue_size),
- maxWaveRequests(p->max_wave_requests), inflightStores(0),
+ gmQueueSize(p.global_mem_queue_size),
+ maxWaveRequests(p.max_wave_requests), inflightStores(0),
inflightLoads(0)
{
}
class GlobalMemPipeline
{
public:
- GlobalMemPipeline(const ComputeUnitParams *p, ComputeUnit &cu);
+ GlobalMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu);
void init();
void exec();
#include "gpu-compute/dispatcher.hh"
#include "params/GPUCommandProcessor.hh"
-GPUCommandProcessor::GPUCommandProcessor(const Params *p)
- : HSADevice(p), dispatcher(*p->dispatcher)
+GPUCommandProcessor::GPUCommandProcessor(const Params &p)
+ : HSADevice(p), dispatcher(*p.dispatcher)
{
dispatcher.setCommandProcessor(this);
}
}
GPUCommandProcessor*
-GPUCommandProcessorParams::create()
+GPUCommandProcessorParams::create() const
{
- return new GPUCommandProcessor(this);
+ return new GPUCommandProcessor(*this);
}
typedef GPUCommandProcessorParams Params;
GPUCommandProcessor() = delete;
- GPUCommandProcessor(const Params *p);
+ GPUCommandProcessor(const Params &p);
void setShader(Shader *shader);
Shader* shader();
#include "params/GPUComputeDriver.hh"
#include "sim/syscall_emul_buf.hh"
-GPUComputeDriver::GPUComputeDriver(Params *p)
+GPUComputeDriver::GPUComputeDriver(const Params &p)
: HSADriver(p)
{
DPRINTF(GPUDriver, "Constructing KFD: device\n");
}
GPUComputeDriver*
-GPUComputeDriverParams::create()
+GPUComputeDriverParams::create() const
{
- return new GPUComputeDriver(this);
+ return new GPUComputeDriver(*this);
}
{
public:
typedef GPUComputeDriverParams Params;
- GPUComputeDriver(Params *p);
+ GPUComputeDriver(const Params &p);
int ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) override;
private:
namespace X86ISA
{
- GpuTLB::GpuTLB(const Params *p)
- : ClockedObject(p), configAddress(0), size(p->size),
+ GpuTLB::GpuTLB(const Params &p)
+ : ClockedObject(p), configAddress(0), size(p.size),
cleanupEvent([this]{ cleanup(); }, name(), false,
Event::Maximum_Pri),
exitEvent([this]{ exitCallback(); }, name())
{
- assoc = p->assoc;
+ assoc = p.assoc;
assert(assoc <= size);
numSets = size/assoc;
- allocationPolicy = p->allocationPolicy;
+ allocationPolicy = p.allocationPolicy;
hasMemSidePort = false;
- accessDistance = p->accessDistance;
+ accessDistance = p.accessDistance;
tlb.assign(size, TlbEntry());
*/
setMask = numSets - 1;
- maxCoalescedReqs = p->maxOutstandingReqs;
+ maxCoalescedReqs = p.maxOutstandingReqs;
// Do not allow maxCoalescedReqs to be more than the TLB associativity
if (maxCoalescedReqs > assoc) {
}
outstandingReqs = 0;
- hitLatency = p->hitLatency;
- missLatency1 = p->missLatency1;
- missLatency2 = p->missLatency2;
+ hitLatency = p.hitLatency;
+ missLatency1 = p.missLatency1;
+ missLatency2 = p.missLatency2;
// create the response ports based on the number of connected ports
- for (size_t i = 0; i < p->port_cpu_side_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d",
name(), i), this, i));
}
// create the request ports based on the number of connected ports
- for (size_t i = 0; i < p->port_mem_side_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
memSidePort.push_back(new MemSidePort(csprintf("%s-port%d",
name(), i), this, i));
}
} // namespace X86ISA
X86ISA::GpuTLB*
-X86GPUTLBParams::create()
+X86GPUTLBParams::create() const
{
- return new X86ISA::GpuTLB(this);
+ return new X86ISA::GpuTLB(*this);
}
public:
typedef X86GPUTLBParams Params;
- GpuTLB(const Params *p);
+ GpuTLB(const Params &p);
~GpuTLB();
typedef enum BaseTLB::Mode Mode;
/**
* the default constructor that works with SWIG
*/
-LdsState::LdsState(const Params *params) :
+LdsState::LdsState(const Params ¶ms) :
ClockedObject(params),
tickEvent(this),
cuPort(name() + ".port", this),
- maximumSize(params->size),
- range(params->range),
- bankConflictPenalty(params->bankConflictPenalty),
- banks(params->banks)
+ maximumSize(params.size),
+ range(params.range),
+ bankConflictPenalty(params.bankConflictPenalty),
+ banks(params.banks)
{
- fatal_if(params->banks <= 0,
+ fatal_if(params.banks <= 0,
"Number of LDS banks should be positive number");
- fatal_if((params->banks & (params->banks - 1)) != 0,
+ fatal_if((params.banks & (params.banks - 1)) != 0,
"Number of LDS banks should be a power of 2");
- fatal_if(params->size <= 0,
+ fatal_if(params.size <= 0,
"cannot allocate an LDS with a size less than 1");
- fatal_if(params->size % 2,
+ fatal_if(params.size % 2,
"the LDS should be an even number");
}
* Needed by the SWIG compiler
*/
LdsState *
-LdsStateParams::create()
+LdsStateParams::create() const
{
- return new LdsState(this);
+ return new LdsState(*this);
}
/**
public:
typedef LdsStateParams Params;
- LdsState(const Params *params);
+ LdsState(const Params ¶ms);
// prevent copy construction
LdsState(const LdsState&) = delete;
parent = nullptr;
}
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
bool
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
-LocalMemPipeline::LocalMemPipeline(const ComputeUnitParams* p, ComputeUnit &cu)
+LocalMemPipeline::LocalMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".LocalMemPipeline"),
- lmQueueSize(p->local_mem_queue_size)
+ lmQueueSize(p.local_mem_queue_size)
{
}
class LocalMemPipeline
{
public:
- LocalMemPipeline(const ComputeUnitParams *p, ComputeUnit &cu);
+ LocalMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu);
void exec();
std::queue<GPUDynInstPtr> &getLMRespFIFO() { return lmReturnedRequests; }
#include "gpu-compute/pool_manager.hh"
-PoolManager::PoolManager(const PoolManagerParams *p)
- : SimObject(p), _minAllocation(p->min_alloc), _poolSize(p->pool_size)
+PoolManager::PoolManager(const PoolManagerParams &p)
+ : SimObject(p), _minAllocation(p.min_alloc), _poolSize(p.pool_size)
{
assert(_poolSize > 0);
}
class PoolManager : public SimObject
{
public:
- PoolManager(const PoolManagerParams *p);
+ PoolManager(const PoolManagerParams &p);
virtual ~PoolManager() { _poolSize = 0; }
uint32_t minAllocation() { return _minAllocation; }
virtual std::string printRegion() = 0;
#include "gpu-compute/wavefront.hh"
#include "params/RegisterFile.hh"
-RegisterFile::RegisterFile(const RegisterFileParams *p)
- : SimObject(p), simdId(p->simd_id), _numRegs(p->num_regs)
+RegisterFile::RegisterFile(const RegisterFileParams &p)
+ : SimObject(p), simdId(p.simd_id), _numRegs(p.num_regs)
{
fatal_if((_numRegs % 2) != 0, "VRF size is illegal\n");
fatal_if(simdId < 0, "Illegal SIMD id for VRF");
}
RegisterFile*
-RegisterFileParams::create()
+RegisterFileParams::create() const
{
- return new RegisterFile(this);
+ return new RegisterFile(*this);
}
// Events
class RegisterFile : public SimObject
{
public:
- RegisterFile(const RegisterFileParams *p);
+ RegisterFile(const RegisterFileParams &p);
virtual ~RegisterFile();
virtual void setParent(ComputeUnit *_computeUnit);
int numRegs() const { return _numRegs; }
#include "gpu-compute/wavefront.hh"
#include "params/RegisterManager.hh"
-RegisterManager::RegisterManager(const RegisterManagerParams *p)
- : SimObject(p), srfPoolMgrs(p->srf_pool_managers),
- vrfPoolMgrs(p->vrf_pool_managers)
+RegisterManager::RegisterManager(const RegisterManagerParams &p)
+ : SimObject(p), srfPoolMgrs(p.srf_pool_managers),
+ vrfPoolMgrs(p.vrf_pool_managers)
{
- if (p->policy == "static") {
+ if (p.policy == "static") {
policy = new StaticRegisterManagerPolicy();
} else {
fatal("Unimplemented Register Manager Policy");
}
RegisterManager*
-RegisterManagerParams::create()
+RegisterManagerParams::create() const
{
- return new RegisterManager(this);
+ return new RegisterManager(*this);
}
class RegisterManager : public SimObject
{
public:
- RegisterManager(const RegisterManagerParams* params);
+ RegisterManager(const RegisterManagerParams ¶ms);
~RegisterManager();
void setParent(ComputeUnit *cu);
void exec();
#include "gpu-compute/shader.hh"
#include "gpu-compute/wavefront.hh"
-ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams* p,
+ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams &p,
ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".ScalarMemPipeline"),
- queueSize(p->scalar_mem_queue_size),
+ queueSize(p.scalar_mem_queue_size),
inflightStores(0), inflightLoads(0)
{
}
class ScalarMemPipeline
{
public:
- ScalarMemPipeline(const ComputeUnitParams *p, ComputeUnit &cu);
+ ScalarMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu);
void exec();
std::queue<GPUDynInstPtr> &getGMReqFIFO() { return issuedRequests; }
#include "gpu-compute/wavefront.hh"
#include "params/ScalarRegisterFile.hh"
-ScalarRegisterFile::ScalarRegisterFile(const ScalarRegisterFileParams *p)
+ScalarRegisterFile::ScalarRegisterFile(const ScalarRegisterFileParams &p)
: RegisterFile(p)
{
regFile.resize(numRegs(), 0);
}
ScalarRegisterFile*
-ScalarRegisterFileParams::create()
+ScalarRegisterFileParams::create() const
{
- return new ScalarRegisterFile(this);
+ return new ScalarRegisterFile(*this);
}
public:
using ScalarRegU32 = TheGpuISA::ScalarRegU32;
- ScalarRegisterFile(const ScalarRegisterFileParams *p);
+ ScalarRegisterFile(const ScalarRegisterFileParams &p);
~ScalarRegisterFile() { }
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
-ScheduleStage::ScheduleStage(const ComputeUnitParams *p, ComputeUnit &cu,
+ScheduleStage::ScheduleStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScoreboardCheckToSchedule &from_scoreboard_check,
ScheduleToExecute &to_execute)
: computeUnit(cu), fromScoreboardCheck(from_scoreboard_check),
class ScheduleStage
{
public:
- ScheduleStage(const ComputeUnitParams *p, ComputeUnit &cu,
+ ScheduleStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScoreboardCheckToSchedule &from_scoreboard_check,
ScheduleToExecute &to_execute);
~ScheduleStage();
#include "gpu-compute/rr_scheduling_policy.hh"
#include "params/ComputeUnit.hh"
-Scheduler::Scheduler(const ComputeUnitParams *p)
+Scheduler::Scheduler(const ComputeUnitParams &p)
{
- if (p->execPolicy == "OLDEST-FIRST") {
+ if (p.execPolicy == "OLDEST-FIRST") {
schedPolicy = new OFSchedulingPolicy();
- } else if (p->execPolicy == "ROUND-ROBIN") {
+ } else if (p.execPolicy == "ROUND-ROBIN") {
schedPolicy = new RRSchedulingPolicy();
} else {
fatal("Unimplemented scheduling policy.\n");
class Scheduler
{
public:
- Scheduler(const ComputeUnitParams *params);
+ Scheduler(const ComputeUnitParams ¶ms);
Wavefront *chooseWave();
void bindList(std::vector<Wavefront*> *sched_list);
#include "gpu-compute/wavefront.hh"
#include "params/ComputeUnit.hh"
-ScoreboardCheckStage::ScoreboardCheckStage(const ComputeUnitParams *p,
+ScoreboardCheckStage::ScoreboardCheckStage(const ComputeUnitParams &p,
ComputeUnit &cu,
ScoreboardCheckToSchedule
&to_schedule)
NRDY_CONDITIONS
};
- ScoreboardCheckStage(const ComputeUnitParams* p, ComputeUnit &cu,
+ ScoreboardCheckStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScoreboardCheckToSchedule &to_schedule);
~ScoreboardCheckStage();
void exec();
#include "mem/ruby/system/RubySystem.hh"
#include "sim/sim_exit.hh"
-Shader::Shader(const Params *p) : ClockedObject(p),
+Shader::Shader(const Params &p) : ClockedObject(p),
_activeCus(0), _lastInactiveTick(0), cpuThread(nullptr),
- gpuTc(nullptr), cpuPointer(p->cpu_pointer),
+ gpuTc(nullptr), cpuPointer(p.cpu_pointer),
tickEvent([this]{ execScheduledAdds(); }, "Shader scheduled adds event",
false, Event::CPU_Tick_Pri),
- timingSim(p->timing), hsail_mode(SIMT),
- impl_kern_launch_acq(p->impl_kern_launch_acq),
- impl_kern_end_rel(p->impl_kern_end_rel),
+ timingSim(p.timing), hsail_mode(SIMT),
+ impl_kern_launch_acq(p.impl_kern_launch_acq),
+ impl_kern_end_rel(p.impl_kern_end_rel),
coissue_return(1),
- trace_vgpr_all(1), n_cu((p->CUs).size()), n_wf(p->n_wf),
- globalMemSize(p->globalmem),
- nextSchedCu(0), sa_n(0), gpuCmdProc(*p->gpu_cmd_proc),
- _dispatcher(*p->dispatcher),
- max_valu_insts(p->max_valu_insts), total_valu_insts(0)
+ trace_vgpr_all(1), n_cu((p.CUs).size()), n_wf(p.n_wf),
+ globalMemSize(p.globalmem),
+ nextSchedCu(0), sa_n(0), gpuCmdProc(*p.gpu_cmd_proc),
+ _dispatcher(*p.dispatcher),
+ max_valu_insts(p.max_valu_insts), total_valu_insts(0)
{
gpuCmdProc.setShader(this);
_dispatcher.setShader(this);
panic_if(n_wf <= 0, "Must have at least 1 WF Slot per SIMD");
for (int i = 0; i < n_cu; ++i) {
- cuList[i] = p->CUs[i];
+ cuList[i] = p.CUs[i];
assert(i == cuList[i]->cu_id);
cuList[i]->shader = this;
- cuList[i]->idleCUTimeout = p->idlecu_timeout;
+ cuList[i]->idleCUTimeout = p.idlecu_timeout;
}
}
}
Shader*
-ShaderParams::create()
+ShaderParams::create() const
{
- return new Shader(this);
+ return new Shader(*this);
}
void
int64_t max_valu_insts;
int64_t total_valu_insts;
- Shader(const Params *p);
+ Shader(const Params &p);
~Shader();
virtual void init();
#include "base/logging.hh"
SimplePoolManager *
-SimplePoolManagerParams::create()
+SimplePoolManagerParams::create() const
{
- return new SimplePoolManager(this);
+ return new SimplePoolManager(*this);
}
// return the min number of elements that the manager can reserve given
class SimplePoolManager : public PoolManager
{
public:
- SimplePoolManager(const PoolManagerParams *p)
+ SimplePoolManager(const PoolManagerParams &p)
: PoolManager(p), _regionSize(0), _nxtFreeIdx(0),
_reservedGroups(0)
{
#include "debug/GPUTLB.hh"
#include "sim/process.hh"
-TLBCoalescer::TLBCoalescer(const Params *p)
+TLBCoalescer::TLBCoalescer(const Params &p)
: ClockedObject(p),
- TLBProbesPerCycle(p->probesPerCycle),
- coalescingWindow(p->coalescingWindow),
- disableCoalescing(p->disableCoalescing),
+ TLBProbesPerCycle(p.probesPerCycle),
+ coalescingWindow(p.coalescingWindow),
+ disableCoalescing(p.disableCoalescing),
probeTLBEvent([this]{ processProbeTLBEvent(); },
"Probe the TLB below",
false, Event::CPU_Tick_Pri),
false, Event::Maximum_Pri)
{
// create the response ports based on the number of connected ports
- for (size_t i = 0; i < p->port_cpu_side_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d", name(), i),
this, i));
}
// create the request ports based on the number of connected ports
- for (size_t i = 0; i < p->port_mem_side_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
memSidePort.push_back(new MemSidePort(csprintf("%s-port%d", name(), i),
this, i));
}
TLBCoalescer*
-TLBCoalescerParams::create()
+TLBCoalescerParams::create() const
{
- return new TLBCoalescer(this);
+ return new TLBCoalescer(*this);
}
{
public:
typedef TLBCoalescerParams Params;
- TLBCoalescer(const Params *p);
+ TLBCoalescer(const Params &p);
~TLBCoalescer() { }
// Number of TLB probes per cycle. Parameterizable - default 2.
#include "gpu-compute/wavefront.hh"
#include "params/VectorRegisterFile.hh"
-VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams *p)
+VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams &p)
: RegisterFile(p)
{
regFile.resize(numRegs(), VecRegContainer());
}
VectorRegisterFile*
-VectorRegisterFileParams::create()
+VectorRegisterFileParams::create() const
{
- return new VectorRegisterFile(this);
+ return new VectorRegisterFile(*this);
}
public:
using VecRegContainer = TheGpuISA::VecRegContainerU32;
- VectorRegisterFile(const VectorRegisterFileParams *p);
+ VectorRegisterFile(const VectorRegisterFileParams &p);
~VectorRegisterFile() { }
virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
#include "gpu-compute/vector_register_file.hh"
Wavefront*
-WavefrontParams::create()
+WavefrontParams::create() const
{
- return new Wavefront(this);
+ return new Wavefront(*this);
}
-Wavefront::Wavefront(const Params *p)
- : SimObject(p), wfSlotId(p->wf_slot_id), simdId(p->simdId),
- maxIbSize(p->max_ib_size), _gpuISA(*this),
+Wavefront::Wavefront(const Params &p)
+ : SimObject(p), wfSlotId(p.wf_slot_id), simdId(p.simdId),
+ maxIbSize(p.max_ib_size), _gpuISA(*this),
vmWaitCnt(-1), expWaitCnt(-1), lgkmWaitCnt(-1),
vmemInstsIssued(0), expInstsIssued(0), lgkmInstsIssued(0),
barId(WFBarrier::InvalidID)
memTraceBusy = 0;
oldVgprTcnt = 0xffffffffffffffffll;
oldDgprTcnt = 0xffffffffffffffffll;
- oldVgpr.resize(p->wf_size);
+ oldVgpr.resize(p.wf_size);
pendingFetch = false;
dropFetch = false;
maxVgprs = 0;
maxSgprs = 0;
- lastAddr.resize(p->wf_size);
- workItemFlatId.resize(p->wf_size);
- oldDgpr.resize(p->wf_size);
+ lastAddr.resize(p.wf_size);
+ workItemFlatId.resize(p.wf_size);
+ oldDgpr.resize(p.wf_size);
for (int i = 0; i < 3; ++i) {
- workItemId[i].resize(p->wf_size);
+ workItemId[i].resize(p.wf_size);
}
_execMask.set();
uint8_t *context;
typedef WavefrontParams Params;
- Wavefront(const Params *p);
+ Wavefront(const Params &p);
~Wavefront();
virtual void init();
#include "debug/HelloExample.hh"
#include "sim/sim_exit.hh"
-GoodbyeObject::GoodbyeObject(GoodbyeObjectParams *params) :
+GoodbyeObject::GoodbyeObject(const GoodbyeObjectParams ¶ms) :
SimObject(params), event([this]{ processEvent(); }, name() + ".event"),
- bandwidth(params->write_bandwidth), bufferSize(params->buffer_size),
+ bandwidth(params.write_bandwidth), bufferSize(params.buffer_size),
buffer(nullptr), bufferUsed(0)
{
buffer = new char[bufferSize]();
}
GoodbyeObject*
-GoodbyeObjectParams::create()
+GoodbyeObjectParams::create() const
{
- return new GoodbyeObject(this);
+ return new GoodbyeObject(*this);
}
int bufferUsed;
public:
- GoodbyeObject(GoodbyeObjectParams *p);
+ GoodbyeObject(const GoodbyeObjectParams &p);
~GoodbyeObject();
/**
#include "base/trace.hh"
#include "debug/HelloExample.hh"
-HelloObject::HelloObject(HelloObjectParams *params) :
+HelloObject::HelloObject(const HelloObjectParams ¶ms) :
SimObject(params),
// This is a C++ lambda. When the event is triggered, it will call the
// processEvent() function. (this must be captured)
event([this]{ processEvent(); }, name() + ".event"),
- goodbye(params->goodbye_object),
+ goodbye(params.goodbye_object),
// Note: This is not needed as you can *always* reference this->name()
- myName(params->name),
- latency(params->time_to_wait),
- timesLeft(params->number_of_fires)
+ myName(params.name),
+ latency(params.time_to_wait),
+ timesLeft(params.number_of_fires)
{
DPRINTF(HelloExample, "Created the hello object\n");
panic_if(!goodbye, "HelloObject must have a non-null GoodbyeObject");
}
HelloObject*
-HelloObjectParams::create()
+HelloObjectParams::create() const
{
- return new HelloObject(this);
+ return new HelloObject(*this);
}
int timesLeft;
public:
- HelloObject(HelloObjectParams *p);
+ HelloObject(const HelloObjectParams &p);
/**
* Part of a SimObject's initilaization. Startup is called after all
#include "debug/SimpleCache.hh"
#include "sim/system.hh"
-SimpleCache::SimpleCache(SimpleCacheParams *params) :
+SimpleCache::SimpleCache(const SimpleCacheParams ¶ms) :
ClockedObject(params),
- latency(params->latency),
- blockSize(params->system->cacheLineSize()),
- capacity(params->size / blockSize),
- memPort(params->name + ".mem_side", this),
+ latency(params.latency),
+ blockSize(params.system->cacheLineSize()),
+ capacity(params.size / blockSize),
+ memPort(params.name + ".mem_side", this),
blocked(false), originalPacket(nullptr), waitingPortId(-1), stats(this)
{
// Since the CPU side ports are a vector of ports, create an instance of
// the CPUSidePort for each connection. This member of params is
// automatically created depending on the name of the vector port and
// holds the number of connections to this port name
- for (int i = 0; i < params->port_cpu_side_connection_count; ++i) {
- cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i),
- i, this);
+ for (int i = 0; i < params.port_cpu_side_connection_count; ++i) {
+ cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i), i, this);
}
}
SimpleCache*
-SimpleCacheParams::create()
+SimpleCacheParams::create() const
{
- return new SimpleCache(this);
+ return new SimpleCache(*this);
}
/** constructor
*/
- SimpleCache(SimpleCacheParams *params);
+ SimpleCache(const SimpleCacheParams ¶ms);
/**
* Get a port with a given name and index. This is used at
#include "base/trace.hh"
#include "debug/SimpleMemobj.hh"
-SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
+SimpleMemobj::SimpleMemobj(const SimpleMemobjParams ¶ms) :
SimObject(params),
- instPort(params->name + ".inst_port", this),
- dataPort(params->name + ".data_port", this),
- memPort(params->name + ".mem_side", this),
+ instPort(params.name + ".inst_port", this),
+ dataPort(params.name + ".data_port", this),
+ memPort(params.name + ".mem_side", this),
blocked(false)
{
}
SimpleMemobj*
-SimpleMemobjParams::create()
+SimpleMemobjParams::create() const
{
- return new SimpleMemobj(this);
+ return new SimpleMemobj(*this);
}
/** constructor
*/
- SimpleMemobj(SimpleMemobjParams *params);
+ SimpleMemobj(const SimpleMemobjParams ¶ms);
/**
* Get a port with a given name and index. This is used at
#include <iostream>
-SimpleObject::SimpleObject(SimpleObjectParams *params) :
+SimpleObject::SimpleObject(const SimpleObjectParams ¶ms) :
SimObject(params)
{
std::cout << "Hello World! From a SimObject!" << std::endl;
}
SimpleObject*
-SimpleObjectParams::create()
+SimpleObjectParams::create() const
{
- return new SimpleObject(this);
+ return new SimpleObject(*this);
}
class SimpleObject : public SimObject
{
public:
- SimpleObject(SimpleObjectParams *p);
+ SimpleObject(const SimpleObjectParams &p);
};
#endif // __LEARNING_GEM5_SIMPLE_OBJECT_HH__
using namespace std;
-AbstractMemory::AbstractMemory(const Params *p) :
- ClockedObject(p), range(params()->range), pmemAddr(NULL),
- backdoor(params()->range, nullptr,
+AbstractMemory::AbstractMemory(const Params &p) :
+ ClockedObject(p), range(p.range), pmemAddr(NULL),
+ backdoor(params().range, nullptr,
(MemBackdoor::Flags)(MemBackdoor::Readable |
MemBackdoor::Writeable)),
- confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
- kvmMap(p->kvm_map), _system(NULL),
+ confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
+ kvmMap(p.kvm_map), _system(NULL),
stats(*this)
{
panic_if(!range.valid() || !range.size(),
{
ClockedObject::initState();
- const auto &file = params()->image_file;
+ const auto &file = params().image_file;
if (file == "")
return;
typedef AbstractMemoryParams Params;
- AbstractMemory(const Params* p);
+ AbstractMemory(const Params &p);
virtual ~AbstractMemory() {}
void initState() override;
*
* @return true if null
*/
- bool isNull() const { return params()->null; }
+ bool isNull() const { return params().null; }
/**
* Set the host memory backing store to be used by this memory
*/
void system(System *sys) { _system = sys; }
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
/**
#include "mem/addr_mapper.hh"
-AddrMapper::AddrMapper(const AddrMapperParams* p)
+AddrMapper::AddrMapper(const AddrMapperParams &p)
: SimObject(p),
memSidePort(name() + "-mem_side_port", *this),
cpuSidePort(name() + "-cpu_side_port", *this)
cpuSidePort.sendRangeChange();
}
-RangeAddrMapper::RangeAddrMapper(const RangeAddrMapperParams* p) :
+RangeAddrMapper::RangeAddrMapper(const RangeAddrMapperParams &p) :
AddrMapper(p),
- originalRanges(p->original_ranges),
- remappedRanges(p->remapped_ranges)
+ originalRanges(p.original_ranges),
+ remappedRanges(p.remapped_ranges)
{
if (originalRanges.size() != remappedRanges.size())
fatal("AddrMapper: original and shadowed range list must "
}
RangeAddrMapper*
-RangeAddrMapperParams::create()
+RangeAddrMapperParams::create() const
{
- return new RangeAddrMapper(this);
+ return new RangeAddrMapper(*this);
}
Addr
public:
- AddrMapper(const AddrMapperParams* params);
+ AddrMapper(const AddrMapperParams ¶ms);
virtual ~AddrMapper() { }
public:
- RangeAddrMapper(const RangeAddrMapperParams* p);
+ RangeAddrMapper(const RangeAddrMapperParams &p);
~RangeAddrMapper() { }
{
}
-Bridge::Bridge(Params *p)
+Bridge::Bridge(const Params &p)
: ClockedObject(p),
- cpuSidePort(p->name + ".cpu_side_port", *this, memSidePort,
- ticksToCycles(p->delay), p->resp_size, p->ranges),
- memSidePort(p->name + ".mem_side_port", *this, cpuSidePort,
- ticksToCycles(p->delay), p->req_size)
+ cpuSidePort(p.name + ".cpu_side_port", *this, memSidePort,
+ ticksToCycles(p.delay), p.resp_size, p.ranges),
+ memSidePort(p.name + ".mem_side_port", *this, cpuSidePort,
+ ticksToCycles(p.delay), p.req_size)
{
}
}
Bridge *
-BridgeParams::create()
+BridgeParams::create() const
{
- return new Bridge(this);
+ return new Bridge(*this);
}
typedef BridgeParams Params;
- Bridge(Params *p);
+ Bridge(const Params &p);
};
#endif //__MEM_BRIDGE_HH__
{
}
-BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
+BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
: ClockedObject(p),
- cpuSidePort (p->name + ".cpu_side_port", this, "CpuSidePort"),
- memSidePort(p->name + ".mem_side_port", this, "MemSidePort"),
- mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
- writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
- tags(p->tags),
- compressor(p->compressor),
- prefetcher(p->prefetcher),
- writeAllocator(p->write_allocator),
- writebackClean(p->writeback_clean),
+ cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
+ memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
+ mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
+ writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
+ tags(p.tags),
+ compressor(p.compressor),
+ prefetcher(p.prefetcher),
+ writeAllocator(p.write_allocator),
+ writebackClean(p.writeback_clean),
tempBlockWriteback(nullptr),
writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
name(), false,
EventBase::Delayed_Writeback_Pri),
blkSize(blk_size),
- lookupLatency(p->tag_latency),
- dataLatency(p->data_latency),
- forwardLatency(p->tag_latency),
- fillLatency(p->data_latency),
- responseLatency(p->response_latency),
- sequentialAccess(p->sequential_access),
- numTarget(p->tgts_per_mshr),
+ lookupLatency(p.tag_latency),
+ dataLatency(p.data_latency),
+ forwardLatency(p.tag_latency),
+ fillLatency(p.data_latency),
+ responseLatency(p.response_latency),
+ sequentialAccess(p.sequential_access),
+ numTarget(p.tgts_per_mshr),
forwardSnoops(true),
- clusivity(p->clusivity),
- isReadOnly(p->is_read_only),
+ clusivity(p.clusivity),
+ isReadOnly(p.is_read_only),
blocked(0),
order(0),
noTargetMSHR(nullptr),
- missCount(p->max_miss_count),
- addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
- system(p->system),
+ missCount(p.max_miss_count),
+ addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
+ system(p.system),
stats(*this)
{
// the MSHR queue has no reserve entries as we check the MSHR
}
WriteAllocator*
-WriteAllocatorParams::create()
+WriteAllocatorParams::create() const
{
- return new WriteAllocator(this);
+ return new WriteAllocator(*this);
}
void regProbePoints() override;
public:
- BaseCache(const BaseCacheParams *p, unsigned blk_size);
+ BaseCache(const BaseCacheParams &p, unsigned blk_size);
~BaseCache();
void init() override;
*/
class WriteAllocator : public SimObject {
public:
- WriteAllocator(const WriteAllocatorParams *p) :
+ WriteAllocator(const WriteAllocatorParams &p) :
SimObject(p),
- coalesceLimit(p->coalesce_limit * p->block_size),
- noAllocateLimit(p->no_allocate_limit * p->block_size),
- delayThreshold(p->delay_threshold)
+ coalesceLimit(p.coalesce_limit * p.block_size),
+ noAllocateLimit(p.no_allocate_limit * p.block_size),
+ delayThreshold(p.delay_threshold)
{
reset();
}
#include "mem/request.hh"
#include "params/Cache.hh"
-Cache::Cache(const CacheParams *p)
- : BaseCache(p, p->system->cacheLineSize()),
+Cache::Cache(const CacheParams &p)
+ : BaseCache(p, p.system->cacheLineSize()),
doFastWrites(true)
{
}
}
Cache*
-CacheParams::create()
+CacheParams::create() const
{
assert(tags);
assert(replacement_policy);
- return new Cache(this);
+ return new Cache(*this);
}
public:
/** Instantiates a basic cache object. */
- Cache(const CacheParams *p);
+ Cache(const CacheParams &p);
/**
* Take an MSHR, turn it into a suitable downstream packet, and
return std::ceil(_size/8);
}
-Base::Base(const Params *p)
- : SimObject(p), blkSize(p->block_size), chunkSizeBits(p->chunk_size_bits),
- sizeThreshold((blkSize * p->size_threshold_percentage) / 100),
+Base::Base(const Params &p)
+ : SimObject(p), blkSize(p.block_size), chunkSizeBits(p.chunk_size_bits),
+ sizeThreshold((blkSize * p.size_threshold_percentage) / 100),
stats(*this)
{
fatal_if(64 % chunkSizeBits,
public:
typedef BaseCacheCompressorParams Params;
- Base(const Params *p);
+ Base(const Params &p);
virtual ~Base() = default;
/**
namespace Compressor {
-Base64Delta8::Base64Delta8(const Params *p)
+Base64Delta8::Base64Delta8(const Params &p)
: BaseDelta<uint64_t, 8>(p)
{
}
-Base64Delta16::Base64Delta16(const Params *p)
+Base64Delta16::Base64Delta16(const Params &p)
: BaseDelta<uint64_t, 16>(p)
{
}
-Base64Delta32::Base64Delta32(const Params *p)
+Base64Delta32::Base64Delta32(const Params &p)
: BaseDelta<uint64_t, 32>(p)
{
}
-Base32Delta8::Base32Delta8(const Params *p)
+Base32Delta8::Base32Delta8(const Params &p)
: BaseDelta<uint32_t, 8>(p)
{
}
-Base32Delta16::Base32Delta16(const Params *p)
+Base32Delta16::Base32Delta16(const Params &p)
: BaseDelta<uint32_t, 16>(p)
{
}
-Base16Delta8::Base16Delta8(const Params *p)
+Base16Delta8::Base16Delta8(const Params &p)
: BaseDelta<uint16_t, 8>(p)
{
}
} // namespace Compressor
Compressor::Base64Delta8*
-Base64Delta8Params::create()
+Base64Delta8Params::create() const
{
- return new Compressor::Base64Delta8(this);
+ return new Compressor::Base64Delta8(*this);
}
Compressor::Base64Delta16*
-Base64Delta16Params::create()
+Base64Delta16Params::create() const
{
- return new Compressor::Base64Delta16(this);
+ return new Compressor::Base64Delta16(*this);
}
Compressor::Base64Delta32*
-Base64Delta32Params::create()
+Base64Delta32Params::create() const
{
- return new Compressor::Base64Delta32(this);
+ return new Compressor::Base64Delta32(*this);
}
Compressor::Base32Delta8*
-Base32Delta8Params::create()
+Base32Delta8Params::create() const
{
- return new Compressor::Base32Delta8(this);
+ return new Compressor::Base32Delta8(*this);
}
Compressor::Base32Delta16*
-Base32Delta16Params::create()
+Base32Delta16Params::create() const
{
- return new Compressor::Base32Delta16(this);
+ return new Compressor::Base32Delta16(*this);
}
Compressor::Base16Delta8*
-Base16Delta8Params::create()
+Base16Delta8Params::create() const
{
- return new Compressor::Base16Delta8(this);
+ return new Compressor::Base16Delta8(*this);
}
public:
typedef BaseDictionaryCompressorParams Params;
- BaseDelta(const Params *p);
+ BaseDelta(const Params &p);
~BaseDelta() = default;
};
{
public:
typedef Base64Delta8Params Params;
- Base64Delta8(const Params *p);
+ Base64Delta8(const Params &p);
~Base64Delta8() = default;
};
{
public:
typedef Base64Delta16Params Params;
- Base64Delta16(const Params *p);
+ Base64Delta16(const Params &p);
~Base64Delta16() = default;
};
{
public:
typedef Base64Delta32Params Params;
- Base64Delta32(const Params *p);
+ Base64Delta32(const Params &p);
~Base64Delta32() = default;
};
{
public:
typedef Base32Delta8Params Params;
- Base32Delta8(const Params *p);
+ Base32Delta8(const Params &p);
~Base32Delta8() = default;
};
{
public:
typedef Base32Delta16Params Params;
- Base32Delta16(const Params *p);
+ Base32Delta16(const Params &p);
~Base32Delta16() = default;
};
{
public:
typedef Base16Delta8Params Params;
- Base16Delta8(const Params *p);
+ Base16Delta8(const Params &p);
~Base16Delta8() = default;
};
namespace Compressor {
template <class BaseType, std::size_t DeltaSizeBits>
-BaseDelta<BaseType, DeltaSizeBits>::BaseDelta(const Params *p)
+BaseDelta<BaseType, DeltaSizeBits>::BaseDelta(const Params &p)
: DictionaryCompressor<BaseType>(p)
{
}
namespace Compressor {
-BaseDictionaryCompressor::BaseDictionaryCompressor(const Params *p)
- : Base(p), dictionarySize(p->dictionary_size),
+BaseDictionaryCompressor::BaseDictionaryCompressor(const Params &p)
+ : Base(p), dictionarySize(p.dictionary_size),
numEntries(0), dictionaryStats(stats, *this)
{
}
namespace Compressor {
-CPack::CPack(const Params *p)
+CPack::CPack(const Params &p)
: DictionaryCompressor<uint32_t>(p)
{
}
} // namespace Compressor
Compressor::CPack*
-CPackParams::create()
+CPackParams::create() const
{
- return new Compressor::CPack(this);
+ return new Compressor::CPack(*this);
}
/**
* Default constructor.
*/
- CPack(const Params *p);
+ CPack(const Params &p);
/**
* Default destructor.
public:
typedef BaseDictionaryCompressorParams Params;
- BaseDictionaryCompressor(const Params *p);
+ BaseDictionaryCompressor(const Params &p);
~BaseDictionaryCompressor() = default;
};
public:
typedef BaseDictionaryCompressorParams Params;
- DictionaryCompressor(const Params *p);
+ DictionaryCompressor(const Params &p);
~DictionaryCompressor() = default;
};
}
template <class T>
-DictionaryCompressor<T>::DictionaryCompressor(const Params *p)
+DictionaryCompressor<T>::DictionaryCompressor(const Params &p)
: BaseDictionaryCompressor(p)
{
dictionary.resize(dictionarySize);
namespace Compressor {
-FPCD::FPCD(const Params *p)
+FPCD::FPCD(const Params &p)
: DictionaryCompressor<uint32_t>(p)
{
}
} // namespace Compressor
Compressor::FPCD*
-FPCDParams::create()
+FPCDParams::create() const
{
- return new Compressor::FPCD(this);
+ return new Compressor::FPCD(*this);
}
public:
typedef FPCDParams Params;
- FPCD(const Params *p);
+ FPCD(const Params &p);
~FPCD() = default;
};
return index;
}
-Multi::Multi(const Params *p)
- : Base(p), compressors(p->compressors),
- numEncodingBits(p->encoding_in_tags ? 0 :
+Multi::Multi(const Params &p)
+ : Base(p), compressors(p.compressors),
+ numEncodingBits(p.encoding_in_tags ? 0 :
std::log2(alignToPowerOfTwo(compressors.size()))),
- extraDecompressionLatency(p->extra_decomp_lat),
+ extraDecompressionLatency(p.extra_decomp_lat),
multiStats(stats, *this)
{
fatal_if(compressors.size() == 0, "There must be at least one compressor");
} // namespace Compressor
Compressor::Multi*
-MultiCompressorParams::create()
+MultiCompressorParams::create() const
{
- return new Compressor::Multi(this);
+ return new Compressor::Multi(*this);
}
public:
typedef MultiCompressorParams Params;
- Multi(const Params *p);
+ Multi(const Params &p);
~Multi();
std::unique_ptr<Base::CompressionData> compress(
namespace Compressor {
-Perfect::Perfect(const Params *p)
- : Base(p), compressedSize(8 * blkSize / p->max_compression_ratio),
- compressionLatency(p->compression_latency),
- decompressionLatency(p->decompression_latency)
+Perfect::Perfect(const Params &p)
+ : Base(p), compressedSize(8 * blkSize / p.max_compression_ratio),
+ compressionLatency(p.compression_latency),
+ decompressionLatency(p.decompression_latency)
{
}
} // namespace Compressor
Compressor::Perfect*
-PerfectCompressorParams::create()
+PerfectCompressorParams::create() const
{
- return new Compressor::Perfect(this);
+ return new Compressor::Perfect(*this);
}
public:
typedef PerfectCompressorParams Params;
- Perfect(const Params *p);
+ Perfect(const Params &p);
~Perfect() = default;
};
namespace Compressor {
-RepeatedQwords::RepeatedQwords(const Params *p)
+RepeatedQwords::RepeatedQwords(const Params &p)
: DictionaryCompressor<uint64_t>(p)
{
}
} // namespace Compressor
Compressor::RepeatedQwords*
-RepeatedQwordsCompressorParams::create()
+RepeatedQwordsCompressorParams::create() const
{
- return new Compressor::RepeatedQwords(this);
+ return new Compressor::RepeatedQwords(*this);
}
public:
typedef RepeatedQwordsCompressorParams Params;
- RepeatedQwords(const Params *p);
+ RepeatedQwords(const Params &p);
~RepeatedQwords() = default;
};
namespace Compressor {
-Zero::Zero(const Params *p)
+Zero::Zero(const Params &p)
: DictionaryCompressor<uint64_t>(p)
{
}
} // namespace Compressor
Compressor::Zero*
-ZeroCompressorParams::create()
+ZeroCompressorParams::create() const
{
- return new Compressor::Zero(this);
+ return new Compressor::Zero(*this);
}
public:
typedef ZeroCompressorParams Params;
- Zero(const Params *p);
+ Zero(const Params &p);
~Zero() = default;
};
#include "mem/cache/mshr.hh"
#include "params/NoncoherentCache.hh"
-NoncoherentCache::NoncoherentCache(const NoncoherentCacheParams *p)
- : BaseCache(p, p->system->cacheLineSize())
+NoncoherentCache::NoncoherentCache(const NoncoherentCacheParams &p)
+ : BaseCache(p, p.system->cacheLineSize())
{
}
}
NoncoherentCache*
-NoncoherentCacheParams::create()
+NoncoherentCacheParams::create() const
{
assert(tags);
assert(replacement_policy);
- return new NoncoherentCache(this);
+ return new NoncoherentCache(*this);
}
M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
public:
- NoncoherentCache(const NoncoherentCacheParams *p);
+ NoncoherentCache(const NoncoherentCacheParams &p);
};
#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__
namespace Prefetcher {
AccessMapPatternMatching::AccessMapPatternMatching(
- const AccessMapPatternMatchingParams *p)
- : ClockedObject(p), blkSize(p->block_size), limitStride(p->limit_stride),
- startDegree(p->start_degree), hotZoneSize(p->hot_zone_size),
- highCoverageThreshold(p->high_coverage_threshold),
- lowCoverageThreshold(p->low_coverage_threshold),
- highAccuracyThreshold(p->high_accuracy_threshold),
- lowAccuracyThreshold(p->low_accuracy_threshold),
- highCacheHitThreshold(p->high_cache_hit_threshold),
- lowCacheHitThreshold(p->low_cache_hit_threshold),
- epochCycles(p->epoch_cycles),
- offChipMemoryLatency(p->offchip_memory_latency),
- accessMapTable(p->access_map_table_assoc, p->access_map_table_entries,
- p->access_map_table_indexing_policy,
- p->access_map_table_replacement_policy,
+ const AccessMapPatternMatchingParams &p)
+ : ClockedObject(p), blkSize(p.block_size), limitStride(p.limit_stride),
+ startDegree(p.start_degree), hotZoneSize(p.hot_zone_size),
+ highCoverageThreshold(p.high_coverage_threshold),
+ lowCoverageThreshold(p.low_coverage_threshold),
+ highAccuracyThreshold(p.high_accuracy_threshold),
+ lowAccuracyThreshold(p.low_accuracy_threshold),
+ highCacheHitThreshold(p.high_cache_hit_threshold),
+ lowCacheHitThreshold(p.low_cache_hit_threshold),
+ epochCycles(p.epoch_cycles),
+ offChipMemoryLatency(p.offchip_memory_latency),
+ accessMapTable(p.access_map_table_assoc, p.access_map_table_entries,
+ p.access_map_table_indexing_policy,
+ p.access_map_table_replacement_policy,
AccessMapEntry(hotZoneSize / blkSize)),
numGoodPrefetches(0), numTotalPrefetches(0), numRawCacheMisses(0),
numRawCacheHits(0), degree(startDegree), usefulDegree(startDegree),
}
}
-AMPM::AMPM(const AMPMPrefetcherParams *p)
- : Queued(p), ampm(*p->ampm)
+AMPM::AMPM(const AMPMPrefetcherParams &p)
+ : Queued(p), ampm(*p.ampm)
{
}
} // namespace Prefetcher
Prefetcher::AccessMapPatternMatching*
-AccessMapPatternMatchingParams::create()
+AccessMapPatternMatchingParams::create() const
{
- return new Prefetcher::AccessMapPatternMatching(this);
+ return new Prefetcher::AccessMapPatternMatching(*this);
}
Prefetcher::AMPM*
-AMPMPrefetcherParams::create()
+AMPMPrefetcherParams::create() const
{
- return new Prefetcher::AMPM(this);
+ return new Prefetcher::AMPM(*this);
}
EventFunctionWrapper epochEvent;
public:
- AccessMapPatternMatching(const AccessMapPatternMatchingParams* p);
+ AccessMapPatternMatching(const AccessMapPatternMatchingParams &p);
~AccessMapPatternMatching() = default;
void startup() override;
{
AccessMapPatternMatching &m;
public:
- AMPM(const AMPMPrefetcherParams* p);
+ AMPM(const AMPMPrefetcherParams &p);
~AMPM() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
}
}
-Base::Base(const BasePrefetcherParams *p)
- : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
- lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
- onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
- requestorId(p->sys->getRequestorId(this)),
- pageBytes(p->sys->getPageBytes()),
- prefetchOnAccess(p->prefetch_on_access),
- useVirtualAddresses(p->use_virtual_addresses),
+Base::Base(const BasePrefetcherParams &p)
+ : ClockedObject(p), listeners(), cache(nullptr), blkSize(p.block_size),
+ lBlkSize(floorLog2(blkSize)), onMiss(p.on_miss), onRead(p.on_read),
+ onWrite(p.on_write), onData(p.on_data), onInst(p.on_inst),
+ requestorId(p.sys->getRequestorId(this)),
+ pageBytes(p.sys->getPageBytes()),
+ prefetchOnAccess(p.prefetch_on_access),
+ useVirtualAddresses(p.use_virtual_addresses),
prefetchStats(this), issuedPrefetches(0),
usefulPrefetches(0), tlb(nullptr)
{
BaseTLB * tlb;
public:
- Base(const BasePrefetcherParams *p);
+ Base(const BasePrefetcherParams &p);
virtual ~Base() = default;
virtual void setCache(BaseCache *_cache);
namespace Prefetcher {
-BOP::BOP(const BOPPrefetcherParams *p)
+BOP::BOP(const BOPPrefetcherParams &p)
: Queued(p),
- scoreMax(p->score_max), roundMax(p->round_max),
- badScore(p->bad_score), rrEntries(p->rr_size),
- tagMask((1 << p->tag_bits) - 1),
- delayQueueEnabled(p->delay_queue_enable),
- delayQueueSize(p->delay_queue_size),
- delayTicks(cyclesToTicks(p->delay_queue_cycles)),
+ scoreMax(p.score_max), roundMax(p.round_max),
+ badScore(p.bad_score), rrEntries(p.rr_size),
+ tagMask((1 << p.tag_bits) - 1),
+ delayQueueEnabled(p.delay_queue_enable),
+ delayQueueSize(p.delay_queue_size),
+ delayTicks(cyclesToTicks(p.delay_queue_cycles)),
delayQueueEvent([this]{ delayQueueEventWrapper(); }, name()),
issuePrefetchRequests(false), bestOffset(1), phaseBestOffset(0),
bestScore(0), round(0)
if (!isPowerOf2(blkSize)) {
fatal("%s: cache line size is not power of 2\n", name());
}
- if (!(p->negative_offsets_enable && (p->offset_list_size % 2 == 0))) {
+ if (!(p.negative_offsets_enable && (p.offset_list_size % 2 == 0))) {
fatal("%s: negative offsets enabled with odd offset list size\n",
name());
}
unsigned int i = 0;
int64_t offset_i = 1;
- while (i < p->offset_list_size)
+ while (i < p.offset_list_size)
{
int64_t offset = offset_i;
i++;
// If we want to use negative offsets, add also the negative value
// of the offset just calculated
- if (p->negative_offsets_enable) {
+ if (p.negative_offsets_enable) {
offsetsList.push_back(OffsetListEntry(-offset_i, 0));
i++;
}
} // namespace Prefetcher
Prefetcher::BOP*
-BOPPrefetcherParams::create()
+BOPPrefetcherParams::create() const
{
- return new Prefetcher::BOP(this);
+ return new Prefetcher::BOP(*this);
}
public:
- BOP(const BOPPrefetcherParams *p);
+ BOP(const BOPPrefetcherParams &p);
~BOP() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
DeltaCorrelatingPredictionTables::DeltaCorrelatingPredictionTables(
- DeltaCorrelatingPredictionTablesParams *p) : SimObject(p),
- deltaBits(p->delta_bits), deltaMaskBits(p->delta_mask_bits),
- table(p->table_assoc, p->table_entries, p->table_indexing_policy,
- p->table_replacement_policy, DCPTEntry(p->deltas_per_entry))
+ const DeltaCorrelatingPredictionTablesParams &p) : SimObject(p),
+ deltaBits(p.delta_bits), deltaMaskBits(p.delta_mask_bits),
+ table(p.table_assoc, p.table_entries, p.table_indexing_policy,
+ p.table_replacement_policy, DCPTEntry(p.deltas_per_entry))
{
}
}
}
-DCPT::DCPT(const DCPTPrefetcherParams *p)
- : Queued(p), dcpt(*p->dcpt)
+DCPT::DCPT(const DCPTPrefetcherParams &p)
+ : Queued(p), dcpt(*p.dcpt)
{
}
} // namespace Prefetcher
Prefetcher::DeltaCorrelatingPredictionTables*
-DeltaCorrelatingPredictionTablesParams::create()
+DeltaCorrelatingPredictionTablesParams::create() const
{
- return new Prefetcher::DeltaCorrelatingPredictionTables(this);
+ return new Prefetcher::DeltaCorrelatingPredictionTables(*this);
}
Prefetcher::DCPT*
-DCPTPrefetcherParams::create()
+DCPTPrefetcherParams::create() const
{
- return new Prefetcher::DCPT(this);
+ return new Prefetcher::DCPT(*this);
}
public:
DeltaCorrelatingPredictionTables(
- DeltaCorrelatingPredictionTablesParams *p);
+ const DeltaCorrelatingPredictionTablesParams &p);
~DeltaCorrelatingPredictionTables() = default;
/**
/** DCPT object */
DeltaCorrelatingPredictionTables &dcpt;
public:
- DCPT(const DCPTPrefetcherParams *p);
+ DCPT(const DCPTPrefetcherParams &p);
~DCPT() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
-IndirectMemory::IndirectMemory(const IndirectMemoryPrefetcherParams *p)
+IndirectMemory::IndirectMemory(const IndirectMemoryPrefetcherParams &p)
: Queued(p),
- maxPrefetchDistance(p->max_prefetch_distance),
- shiftValues(p->shift_values), prefetchThreshold(p->prefetch_threshold),
- streamCounterThreshold(p->stream_counter_threshold),
- streamingDistance(p->streaming_distance),
- prefetchTable(p->pt_table_assoc, p->pt_table_entries,
- p->pt_table_indexing_policy, p->pt_table_replacement_policy,
- PrefetchTableEntry(p->num_indirect_counter_bits)),
- ipd(p->ipd_table_assoc, p->ipd_table_entries, p->ipd_table_indexing_policy,
- p->ipd_table_replacement_policy,
- IndirectPatternDetectorEntry(p->addr_array_len, shiftValues.size())),
- ipdEntryTrackingMisses(nullptr), byteOrder(p->sys->getGuestByteOrder())
+ maxPrefetchDistance(p.max_prefetch_distance),
+ shiftValues(p.shift_values), prefetchThreshold(p.prefetch_threshold),
+ streamCounterThreshold(p.stream_counter_threshold),
+ streamingDistance(p.streaming_distance),
+ prefetchTable(p.pt_table_assoc, p.pt_table_entries,
+ p.pt_table_indexing_policy, p.pt_table_replacement_policy,
+ PrefetchTableEntry(p.num_indirect_counter_bits)),
+ ipd(p.ipd_table_assoc, p.ipd_table_entries, p.ipd_table_indexing_policy,
+ p.ipd_table_replacement_policy,
+ IndirectPatternDetectorEntry(p.addr_array_len, shiftValues.size())),
+ ipdEntryTrackingMisses(nullptr), byteOrder(p.sys->getGuestByteOrder())
{
}
} // namespace Prefetcher
Prefetcher::IndirectMemory*
-IndirectMemoryPrefetcherParams::create()
+IndirectMemoryPrefetcherParams::create() const
{
- return new Prefetcher::IndirectMemory(this);
+ return new Prefetcher::IndirectMemory(*this);
}
void checkAccessMatchOnActiveEntries(Addr addr);
public:
- IndirectMemory(const IndirectMemoryPrefetcherParams *p);
+ IndirectMemory(const IndirectMemoryPrefetcherParams &p);
~IndirectMemory() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
IrregularStreamBuffer::IrregularStreamBuffer(
- const IrregularStreamBufferPrefetcherParams *p)
+ const IrregularStreamBufferPrefetcherParams &p)
: Queued(p),
- chunkSize(p->chunk_size),
- prefetchCandidatesPerEntry(p->prefetch_candidates_per_entry),
- degree(p->degree),
- trainingUnit(p->training_unit_assoc, p->training_unit_entries,
- p->training_unit_indexing_policy,
- p->training_unit_replacement_policy),
- psAddressMappingCache(p->address_map_cache_assoc,
- p->address_map_cache_entries,
- p->ps_address_map_cache_indexing_policy,
- p->ps_address_map_cache_replacement_policy,
+ chunkSize(p.chunk_size),
+ prefetchCandidatesPerEntry(p.prefetch_candidates_per_entry),
+ degree(p.degree),
+ trainingUnit(p.training_unit_assoc, p.training_unit_entries,
+ p.training_unit_indexing_policy,
+ p.training_unit_replacement_policy),
+ psAddressMappingCache(p.address_map_cache_assoc,
+ p.address_map_cache_entries,
+ p.ps_address_map_cache_indexing_policy,
+ p.ps_address_map_cache_replacement_policy,
AddressMappingEntry(prefetchCandidatesPerEntry,
- p->num_counter_bits)),
- spAddressMappingCache(p->address_map_cache_assoc,
- p->address_map_cache_entries,
- p->sp_address_map_cache_indexing_policy,
- p->sp_address_map_cache_replacement_policy,
+ p.num_counter_bits)),
+ spAddressMappingCache(p.address_map_cache_assoc,
+ p.address_map_cache_entries,
+ p.sp_address_map_cache_indexing_policy,
+ p.sp_address_map_cache_replacement_policy,
AddressMappingEntry(prefetchCandidatesPerEntry,
- p->num_counter_bits)),
+ p.num_counter_bits)),
structuralAddressCounter(0)
{
assert(isPowerOf2(prefetchCandidatesPerEntry));
} // namespace Prefetcher
Prefetcher::IrregularStreamBuffer*
-IrregularStreamBufferPrefetcherParams::create()
+IrregularStreamBufferPrefetcherParams::create() const
{
- return new Prefetcher::IrregularStreamBuffer(this);
+ return new Prefetcher::IrregularStreamBuffer(*this);
}
*/
AddressMapping& getPSMapping(Addr paddr, bool is_secure);
public:
- IrregularStreamBuffer(const IrregularStreamBufferPrefetcherParams *p);
+ IrregularStreamBuffer(const IrregularStreamBufferPrefetcherParams &p);
~IrregularStreamBuffer() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
-Multi::Multi(const MultiPrefetcherParams *p)
+Multi::Multi(const MultiPrefetcherParams &p)
: Base(p),
- prefetchers(p->prefetchers.begin(), p->prefetchers.end())
+ prefetchers(p.prefetchers.begin(), p.prefetchers.end())
{
}
} // namespace Prefetcher
Prefetcher::Multi*
-MultiPrefetcherParams::create()
+MultiPrefetcherParams::create() const
{
- return new Prefetcher::Multi(this);
+ return new Prefetcher::Multi(*this);
}
class Multi : public Base
{
public: // SimObject
- Multi(const MultiPrefetcherParams *p);
+ Multi(const MultiPrefetcherParams &p);
public:
void setCache(BaseCache *_cache) override;
namespace Prefetcher {
-PIF::PIF(const PIFPrefetcherParams *p)
+PIF::PIF(const PIFPrefetcherParams &p)
: Queued(p),
- precSize(p->prec_spatial_region_bits),
- succSize(p->succ_spatial_region_bits),
- maxCompactorEntries(p->compactor_entries),
- historyBuffer(p->history_buffer_size),
- index(p->index_assoc, p->index_entries, p->index_indexing_policy,
- p->index_replacement_policy),
- streamAddressBuffer(p->stream_address_buffer_entries),
+ precSize(p.prec_spatial_region_bits),
+ succSize(p.succ_spatial_region_bits),
+ maxCompactorEntries(p.compactor_entries),
+ historyBuffer(p.history_buffer_size),
+ index(p.index_assoc, p.index_entries, p.index_indexing_policy,
+ p.index_replacement_policy),
+ streamAddressBuffer(p.stream_address_buffer_entries),
listenersPC()
{
}
} // namespace Prefetcher
Prefetcher::PIF*
-PIFPrefetcherParams::create()
+PIFPrefetcherParams::create() const
{
- return new Prefetcher::PIF(this);
+ return new Prefetcher::PIF(*this);
}
public:
- PIF(const PIFPrefetcherParams *p);
+ PIF(const PIFPrefetcherParams &p);
~PIF() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
owner->translationComplete(this, failed);
}
-Queued::Queued(const QueuedPrefetcherParams *p)
- : Base(p), queueSize(p->queue_size),
+Queued::Queued(const QueuedPrefetcherParams &p)
+ : Base(p), queueSize(p.queue_size),
missingTranslationQueueSize(
- p->max_prefetch_requests_with_pending_translation),
- latency(p->latency), queueSquash(p->queue_squash),
- queueFilter(p->queue_filter), cacheSnoop(p->cache_snoop),
- tagPrefetch(p->tag_prefetch),
- throttleControlPct(p->throttle_control_percentage), statsQueued(this)
+ p.max_prefetch_requests_with_pending_translation),
+ latency(p.latency), queueSquash(p.queue_squash),
+ queueFilter(p.queue_filter), cacheSnoop(p.cache_snoop),
+ tagPrefetch(p.tag_prefetch),
+ throttleControlPct(p.throttle_control_percentage), statsQueued(this)
{
}
public:
using AddrPriority = std::pair<Addr, int32_t>;
- Queued(const QueuedPrefetcherParams *p);
+ Queued(const QueuedPrefetcherParams &p);
virtual ~Queued();
void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override;
namespace Prefetcher {
-SBOOE::SBOOE(const SBOOEPrefetcherParams *p)
+SBOOE::SBOOE(const SBOOEPrefetcherParams &p)
: Queued(p),
- sequentialPrefetchers(p->sequential_prefetchers),
- scoreThreshold((p->sandbox_entries*p->score_threshold_pct)/100),
- latencyBuffer(p->latency_buffer_size),
+ sequentialPrefetchers(p.sequential_prefetchers),
+ scoreThreshold((p.sandbox_entries*p.score_threshold_pct)/100),
+ latencyBuffer(p.latency_buffer_size),
averageAccessLatency(0), latencyBufferSum(0),
bestSandbox(NULL),
accesses(0)
// Initialize a sandbox for every sequential prefetcher between
// -1 and the number of sequential prefetchers defined
for (int i = 0; i < sequentialPrefetchers; i++) {
- sandboxes.push_back(Sandbox(p->sandbox_entries, i-1));
+ sandboxes.push_back(Sandbox(p.sandbox_entries, i-1));
}
}
} // namespace Prefetcher
Prefetcher::SBOOE*
-SBOOEPrefetcherParams::create()
+SBOOEPrefetcherParams::create() const
{
- return new Prefetcher::SBOOE(this);
+ return new Prefetcher::SBOOE(*this);
}
void notifyFill(const PacketPtr& pkt) override;
public:
- SBOOE(const SBOOEPrefetcherParams *p);
+ SBOOE(const SBOOEPrefetcherParams &p);
void calculatePrefetch(const PrefetchInfo &pfi,
std::vector<AddrPriority> &addresses) override;
namespace Prefetcher {
-SignaturePath::SignaturePath(const SignaturePathPrefetcherParams *p)
+SignaturePath::SignaturePath(const SignaturePathPrefetcherParams &p)
: Queued(p),
- stridesPerPatternEntry(p->strides_per_pattern_entry),
- signatureShift(p->signature_shift),
- signatureBits(p->signature_bits),
- prefetchConfidenceThreshold(p->prefetch_confidence_threshold),
- lookaheadConfidenceThreshold(p->lookahead_confidence_threshold),
- signatureTable(p->signature_table_assoc, p->signature_table_entries,
- p->signature_table_indexing_policy,
- p->signature_table_replacement_policy),
- patternTable(p->pattern_table_assoc, p->pattern_table_entries,
- p->pattern_table_indexing_policy,
- p->pattern_table_replacement_policy,
- PatternEntry(stridesPerPatternEntry, p->num_counter_bits))
+ stridesPerPatternEntry(p.strides_per_pattern_entry),
+ signatureShift(p.signature_shift),
+ signatureBits(p.signature_bits),
+ prefetchConfidenceThreshold(p.prefetch_confidence_threshold),
+ lookaheadConfidenceThreshold(p.lookahead_confidence_threshold),
+ signatureTable(p.signature_table_assoc, p.signature_table_entries,
+ p.signature_table_indexing_policy,
+ p.signature_table_replacement_policy),
+ patternTable(p.pattern_table_assoc, p.pattern_table_entries,
+ p.pattern_table_indexing_policy,
+ p.pattern_table_replacement_policy,
+ PatternEntry(stridesPerPatternEntry, p.num_counter_bits))
{
fatal_if(prefetchConfidenceThreshold < 0,
"The prefetch confidence threshold must be greater than 0\n");
} // namespace Prefetcher
Prefetcher::SignaturePath*
-SignaturePathPrefetcherParams::create()
+SignaturePathPrefetcherParams::create() const
{
- return new Prefetcher::SignaturePath(this);
+ return new Prefetcher::SignaturePath(*this);
}
}
public:
- SignaturePath(const SignaturePathPrefetcherParams* p);
+ SignaturePath(const SignaturePathPrefetcherParams &p);
~SignaturePath() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
-SignaturePathV2::SignaturePathV2(const SignaturePathPrefetcherV2Params *p)
+SignaturePathV2::SignaturePathV2(const SignaturePathPrefetcherV2Params &p)
: SignaturePath(p),
- globalHistoryRegister(p->global_history_register_entries,
- p->global_history_register_entries,
- p->global_history_register_indexing_policy,
- p->global_history_register_replacement_policy,
+ globalHistoryRegister(p.global_history_register_entries,
+ p.global_history_register_entries,
+ p.global_history_register_indexing_policy,
+ p.global_history_register_replacement_policy,
GlobalHistoryEntry())
{
}
} // namespace Prefetcher
Prefetcher::SignaturePathV2*
-SignaturePathPrefetcherV2Params::create()
+SignaturePathPrefetcherV2Params::create() const
{
- return new Prefetcher::SignaturePathV2(this);
+ return new Prefetcher::SignaturePathV2(*this);
}
override;
public:
- SignaturePathV2(const SignaturePathPrefetcherV2Params* p);
+ SignaturePathV2(const SignaturePathPrefetcherV2Params &p);
~SignaturePathV2() = default;
};
namespace Prefetcher {
-SlimAMPM::SlimAMPM(const SlimAMPMPrefetcherParams* p)
- : Queued(p), ampm(*p->ampm), dcpt(*p->dcpt)
+SlimAMPM::SlimAMPM(const SlimAMPMPrefetcherParams &p)
+ : Queued(p), ampm(*p.ampm), dcpt(*p.dcpt)
{
}
} // namespace Prefetcher
Prefetcher::SlimAMPM*
-SlimAMPMPrefetcherParams::create()
+SlimAMPMPrefetcherParams::create() const
{
- return new Prefetcher::SlimAMPM(this);
+ return new Prefetcher::SlimAMPM(*this);
}
/** DCPT prefetcher object */
DeltaCorrelatingPredictionTables &dcpt;
public:
- SlimAMPM(const SlimAMPMPrefetcherParams *p);
+ SlimAMPM(const SlimAMPMPrefetcherParams &p);
~SlimAMPM() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
namespace Prefetcher {
-STeMS::STeMS(const STeMSPrefetcherParams *p)
- : Queued(p), spatialRegionSize(p->spatial_region_size),
- spatialRegionSizeBits(floorLog2(p->spatial_region_size)),
- reconstructionEntries(p->reconstruction_entries),
- activeGenerationTable(p->active_generation_table_assoc,
- p->active_generation_table_entries,
- p->active_generation_table_indexing_policy,
- p->active_generation_table_replacement_policy,
+STeMS::STeMS(const STeMSPrefetcherParams &p)
+ : Queued(p), spatialRegionSize(p.spatial_region_size),
+ spatialRegionSizeBits(floorLog2(p.spatial_region_size)),
+ reconstructionEntries(p.reconstruction_entries),
+ activeGenerationTable(p.active_generation_table_assoc,
+ p.active_generation_table_entries,
+ p.active_generation_table_indexing_policy,
+ p.active_generation_table_replacement_policy,
ActiveGenerationTableEntry(
spatialRegionSize / blkSize)),
- patternSequenceTable(p->pattern_sequence_table_assoc,
- p->pattern_sequence_table_entries,
- p->pattern_sequence_table_indexing_policy,
- p->pattern_sequence_table_replacement_policy,
+ patternSequenceTable(p.pattern_sequence_table_assoc,
+ p.pattern_sequence_table_entries,
+ p.pattern_sequence_table_indexing_policy,
+ p.pattern_sequence_table_replacement_policy,
ActiveGenerationTableEntry(
spatialRegionSize / blkSize)),
- rmob(p->region_miss_order_buffer_entries)
+ rmob(p.region_miss_order_buffer_entries)
{
fatal_if(!isPowerOf2(spatialRegionSize),
"The spatial region size must be a power of 2.");
} // namespace Prefetcher
Prefetcher::STeMS*
-STeMSPrefetcherParams::create()
+STeMSPrefetcherParams::create() const
{
- return new Prefetcher::STeMS(this);
+ return new Prefetcher::STeMS(*this);
}
std::vector<AddrPriority> &addresses);
public:
- STeMS(const STeMSPrefetcherParams* p);
+ STeMS(const STeMSPrefetcherParams &p);
~STeMS() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
confidence.reset();
}
-Stride::Stride(const StridePrefetcherParams *p)
+Stride::Stride(const StridePrefetcherParams &p)
: Queued(p),
- initConfidence(p->confidence_counter_bits, p->initial_confidence),
- threshConf(p->confidence_threshold/100.0),
- useRequestorId(p->use_requestor_id),
- degree(p->degree),
- pcTableInfo(p->table_assoc, p->table_entries, p->table_indexing_policy,
- p->table_replacement_policy)
+ initConfidence(p.confidence_counter_bits, p.initial_confidence),
+ threshConf(p.confidence_threshold/100.0),
+ useRequestorId(p.use_requestor_id),
+ degree(p.degree),
+ pcTableInfo(p.table_assoc, p.table_entries, p.table_indexing_policy,
+ p.table_replacement_policy)
{
}
} // namespace Prefetcher
Prefetcher::StridePrefetcherHashedSetAssociative*
-StridePrefetcherHashedSetAssociativeParams::create()
+StridePrefetcherHashedSetAssociativeParams::create() const
{
- return new Prefetcher::StridePrefetcherHashedSetAssociative(this);
+ return new Prefetcher::StridePrefetcherHashedSetAssociative(*this);
}
Prefetcher::Stride*
-StridePrefetcherParams::create()
+StridePrefetcherParams::create() const
{
- return new Prefetcher::Stride(this);
+ return new Prefetcher::Stride(*this);
}
public:
StridePrefetcherHashedSetAssociative(
- const StridePrefetcherHashedSetAssociativeParams *p)
+ const StridePrefetcherHashedSetAssociativeParams &p)
: SetAssociative(p)
{
}
PCTable* allocateNewContext(int context);
public:
- Stride(const StridePrefetcherParams *p);
+ Stride(const StridePrefetcherParams &p);
void calculatePrefetch(const PrefetchInfo &pfi,
std::vector<AddrPriority> &addresses) override;
namespace Prefetcher {
-Tagged::Tagged(const TaggedPrefetcherParams *p)
- : Queued(p), degree(p->degree)
+Tagged::Tagged(const TaggedPrefetcherParams &p)
+ : Queued(p), degree(p.degree)
{
}
} // namespace Prefetcher
Prefetcher::Tagged*
-TaggedPrefetcherParams::create()
+TaggedPrefetcherParams::create() const
{
- return new Prefetcher::Tagged(this);
+ return new Prefetcher::Tagged(*this);
}
const int degree;
public:
- Tagged(const TaggedPrefetcherParams *p);
+ Tagged(const TaggedPrefetcherParams &p);
~Tagged() = default;
void calculatePrefetch(const PrefetchInfo &pfi,
{
public:
typedef BaseReplacementPolicyParams Params;
- Base(const Params *p) : SimObject(p) {}
+ Base(const Params &p) : SimObject(p) {}
virtual ~Base() = default;
/**
namespace ReplacementPolicy {
-BIP::BIP(const Params *p)
- : LRU(p), btp(p->btp)
+BIP::BIP(const Params &p)
+ : LRU(p), btp(p.btp)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::BIP*
-BIPRPParams::create()
+BIPRPParams::create() const
{
- return new ReplacementPolicy::BIP(this);
+ return new ReplacementPolicy::BIP(*this);
}
public:
typedef BIPRPParams Params;
- BIP(const Params *p);
+ BIP(const Params &p);
~BIP() = default;
/**
namespace ReplacementPolicy {
-BRRIP::BRRIP(const Params *p)
- : Base(p), numRRPVBits(p->num_bits), hitPriority(p->hit_priority),
- btp(p->btp)
+BRRIP::BRRIP(const Params &p)
+ : Base(p), numRRPVBits(p.num_bits), hitPriority(p.hit_priority),
+ btp(p.btp)
{
fatal_if(numRRPVBits <= 0, "There should be at least one bit per RRPV.\n");
}
} // namespace ReplacementPolicy
ReplacementPolicy::BRRIP*
-BRRIPRPParams::create()
+BRRIPRPParams::create() const
{
- return new ReplacementPolicy::BRRIP(this);
+ return new ReplacementPolicy::BRRIP(*this);
}
public:
typedef BRRIPRPParams Params;
- BRRIP(const Params *p);
+ BRRIP(const Params &p);
~BRRIP() = default;
/**
namespace ReplacementPolicy {
-FIFO::FIFO(const Params *p)
+FIFO::FIFO(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::FIFO*
-FIFORPParams::create()
+FIFORPParams::create() const
{
- return new ReplacementPolicy::FIFO(this);
+ return new ReplacementPolicy::FIFO(*this);
}
public:
typedef FIFORPParams Params;
- FIFO(const Params *p);
+ FIFO(const Params &p);
~FIFO() = default;
/**
namespace ReplacementPolicy {
-LFU::LFU(const Params *p)
+LFU::LFU(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::LFU*
-LFURPParams::create()
+LFURPParams::create() const
{
- return new ReplacementPolicy::LFU(this);
+ return new ReplacementPolicy::LFU(*this);
}
public:
typedef LFURPParams Params;
- LFU(const Params *p);
+ LFU(const Params &p);
~LFU() = default;
/**
namespace ReplacementPolicy {
-LRU::LRU(const Params *p)
+LRU::LRU(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::LRU*
-LRURPParams::create()
+LRURPParams::create() const
{
- return new ReplacementPolicy::LRU(this);
+ return new ReplacementPolicy::LRU(*this);
}
public:
typedef LRURPParams Params;
- LRU(const Params *p);
+ LRU(const Params &p);
~LRU() = default;
/**
namespace ReplacementPolicy {
-MRU::MRU(const Params *p)
+MRU::MRU(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::MRU*
-MRURPParams::create()
+MRURPParams::create() const
{
- return new ReplacementPolicy::MRU(this);
+ return new ReplacementPolicy::MRU(*this);
}
public:
typedef MRURPParams Params;
- MRU(const Params *p);
+ MRU(const Params &p);
~MRU() = default;
/**
namespace ReplacementPolicy {
-Random::Random(const Params *p)
+Random::Random(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::Random*
-RandomRPParams::create()
+RandomRPParams::create() const
{
- return new ReplacementPolicy::Random(this);
+ return new ReplacementPolicy::Random(*this);
}
public:
typedef RandomRPParams Params;
- Random(const Params *p);
+ Random(const Params &p);
~Random() = default;
/**
namespace ReplacementPolicy {
-SecondChance::SecondChance(const Params *p)
+SecondChance::SecondChance(const Params &p)
: FIFO(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::SecondChance*
-SecondChanceRPParams::create()
+SecondChanceRPParams::create() const
{
- return new ReplacementPolicy::SecondChance(this);
+ return new ReplacementPolicy::SecondChance(*this);
}
public:
typedef SecondChanceRPParams Params;
- SecondChance(const Params *p);
+ SecondChance(const Params &p);
~SecondChance() = default;
/**
{
}
-TreePLRU::TreePLRU(const Params *p)
- : Base(p), numLeaves(p->num_leaves), count(0), treeInstance(nullptr)
+TreePLRU::TreePLRU(const Params &p)
+ : Base(p), numLeaves(p.num_leaves), count(0), treeInstance(nullptr)
{
fatal_if(!isPowerOf2(numLeaves),
"Number of leaves must be non-zero and a power of 2");
} // namespace ReplacementPolicy
ReplacementPolicy::TreePLRU*
-TreePLRURPParams::create()
+TreePLRURPParams::create() const
{
- return new ReplacementPolicy::TreePLRU(this);
+ return new ReplacementPolicy::TreePLRU(*this);
}
public:
typedef TreePLRURPParams Params;
- TreePLRU(const Params *p);
+ TreePLRU(const Params &p);
~TreePLRU() = default;
/**
namespace ReplacementPolicy {
-WeightedLRU::WeightedLRU(const Params* p)
+WeightedLRU::WeightedLRU(const Params &p)
: Base(p)
{
}
} // namespace ReplacementPolicy
ReplacementPolicy::WeightedLRU*
-WeightedLRURPParams::create()
+WeightedLRURPParams::create() const
{
- return new ReplacementPolicy::WeightedLRU(this);
+ return new ReplacementPolicy::WeightedLRU(*this);
}
};
public:
typedef WeightedLRURPParams Params;
- WeightedLRU(const Params* p);
+ WeightedLRU(const Params &p);
~WeightedLRU() = default;
/**
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-BaseTags::BaseTags(const Params *p)
- : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
- size(p->size), lookupLatency(p->tag_latency),
- system(p->system), indexingPolicy(p->indexing_policy),
- warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
- warmedUp(false), numBlocks(p->size / p->block_size),
- dataBlks(new uint8_t[p->size]), // Allocate data storage in one big chunk
+BaseTags::BaseTags(const Params &p)
+ : ClockedObject(p), blkSize(p.block_size), blkMask(blkSize - 1),
+ size(p.size), lookupLatency(p.tag_latency),
+ system(p.system), indexingPolicy(p.indexing_policy),
+ warmupBound((p.warmup_percentage/100.0) * (p.size / p.block_size)),
+ warmedUp(false), numBlocks(p.size / p.block_size),
+ dataBlks(new uint8_t[p.size]), // Allocate data storage in one big chunk
stats(*this)
{
registerExitCallback([this]() { cleanupRefs(); });
public:
typedef BaseTagsParams Params;
- BaseTags(const Params *p);
+ BaseTags(const Params &p);
/**
* Destructor.
#include "base/intmath.hh"
-BaseSetAssoc::BaseSetAssoc(const Params *p)
- :BaseTags(p), allocAssoc(p->assoc), blks(p->size / p->block_size),
- sequentialAccess(p->sequential_access),
- replacementPolicy(p->replacement_policy)
+BaseSetAssoc::BaseSetAssoc(const Params &p)
+ :BaseTags(p), allocAssoc(p.assoc), blks(p.size / p.block_size),
+ sequentialAccess(p.sequential_access),
+ replacementPolicy(p.replacement_policy)
{
// Check parameters
if (blkSize < 4 || !isPowerOf2(blkSize)) {
}
BaseSetAssoc *
-BaseSetAssocParams::create()
+BaseSetAssocParams::create() const
{
// There must be a indexing policy
fatal_if(!indexing_policy, "An indexing policy is required");
- return new BaseSetAssoc(this);
+ return new BaseSetAssoc(*this);
}
/**
* Construct and initialize this tag store.
*/
- BaseSetAssoc(const Params *p);
+ BaseSetAssoc(const Params &p);
/**
* Destructor
#include "mem/packet.hh"
#include "params/CompressedTags.hh"
-CompressedTags::CompressedTags(const Params *p)
+CompressedTags::CompressedTags(const Params &p)
: SectorTags(p)
{
}
}
CompressedTags *
-CompressedTagsParams::create()
+CompressedTagsParams::create() const
{
- return new CompressedTags(this);
+ return new CompressedTags(*this);
}
/**
* Construct and initialize this tag store.
*/
- CompressedTags(const Params *p);
+ CompressedTags(const Params &p);
/**
* Destructor.
return csprintf("%s inCachesMask: %#x", CacheBlk::print(), inCachesMask);
}
-FALRU::FALRU(const Params *p)
+FALRU::FALRU(const Params &p)
: BaseTags(p),
- cacheTracking(p->min_tracked_cache_size, size, blkSize)
+ cacheTracking(p.min_tracked_cache_size, size, blkSize)
{
if (!isPowerOf2(blkSize))
fatal("cache block size (in bytes) `%d' must be a power of two",
}
FALRU *
-FALRUParams::create()
+FALRUParams::create() const
{
- return new FALRU(this);
+ return new FALRU(*this);
}
void
/**
* Construct and initialize this cache tagstore.
*/
- FALRU(const Params *p);
+ FALRU(const Params &p);
~FALRU();
/**
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
-BaseIndexingPolicy::BaseIndexingPolicy(const Params *p)
- : SimObject(p), assoc(p->assoc),
- numSets(p->size / (p->entry_size * assoc)),
- setShift(floorLog2(p->entry_size)), setMask(numSets - 1), sets(numSets),
+BaseIndexingPolicy::BaseIndexingPolicy(const Params &p)
+ : SimObject(p), assoc(p.assoc),
+ numSets(p.size / (p.entry_size * assoc)),
+ setShift(floorLog2(p.entry_size)), setMask(numSets - 1), sets(numSets),
tagShift(setShift + floorLog2(numSets))
{
fatal_if(!isPowerOf2(numSets), "# of sets must be non-zero and a power " \
/**
* Construct and initialize this policy.
*/
- BaseIndexingPolicy(const Params *p);
+ BaseIndexingPolicy(const Params &p);
/**
* Destructor.
#include "mem/cache/replacement_policies/replaceable_entry.hh"
-SetAssociative::SetAssociative(const Params *p)
+SetAssociative::SetAssociative(const Params &p)
: BaseIndexingPolicy(p)
{
}
}
SetAssociative*
-SetAssociativeParams::create()
+SetAssociativeParams::create() const
{
- return new SetAssociative(this);
+ return new SetAssociative(*this);
}
/**
* Construct and initialize this policy.
*/
- SetAssociative(const Params *p);
+ SetAssociative(const Params &p);
/**
* Destructor.
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
-SkewedAssociative::SkewedAssociative(const Params *p)
+SkewedAssociative::SkewedAssociative(const Params &p)
: BaseIndexingPolicy(p), msbShift(floorLog2(numSets) - 1)
{
if (assoc > NUM_SKEWING_FUNCTIONS) {
}
SkewedAssociative *
-SkewedAssociativeParams::create()
+SkewedAssociativeParams::create() const
{
- return new SkewedAssociative(this);
+ return new SkewedAssociative(*this);
}
/**
* Construct and initialize this policy.
*/
- SkewedAssociative(const Params *p);
+ SkewedAssociative(const Params &p);
/**
* Destructor.
#include "mem/cache/replacement_policies/replaceable_entry.hh"
#include "mem/cache/tags/indexing_policies/base.hh"
-SectorTags::SectorTags(const SectorTagsParams *p)
- : BaseTags(p), allocAssoc(p->assoc),
- sequentialAccess(p->sequential_access),
- replacementPolicy(p->replacement_policy),
- numBlocksPerSector(p->num_blocks_per_sector),
+SectorTags::SectorTags(const SectorTagsParams &p)
+ : BaseTags(p), allocAssoc(p.assoc),
+ sequentialAccess(p.sequential_access),
+ replacementPolicy(p.replacement_policy),
+ numBlocksPerSector(p.num_blocks_per_sector),
numSectors(numBlocks / numBlocksPerSector),
sectorShift(floorLog2(blkSize)), sectorMask(numBlocksPerSector - 1),
sectorStats(stats, *this)
}
SectorTags *
-SectorTagsParams::create()
+SectorTagsParams::create() const
{
// There must be a indexing policy
fatal_if(!indexing_policy, "An indexing policy is required");
- return new SectorTags(this);
+ return new SectorTags(*this);
}
/**
* Construct and initialize this tag store.
*/
- SectorTags(const Params *p);
+ SectorTags(const Params &p);
/**
* Destructor.
#include "debug/CoherentXBar.hh"
#include "sim/system.hh"
-CoherentXBar::CoherentXBar(const CoherentXBarParams *p)
- : BaseXBar(p), system(p->system), snoopFilter(p->snoop_filter),
- snoopResponseLatency(p->snoop_response_latency),
- maxOutstandingSnoopCheck(p->max_outstanding_snoops),
- maxRoutingTableSizeCheck(p->max_routing_table_size),
- pointOfCoherency(p->point_of_coherency),
- pointOfUnification(p->point_of_unification),
+CoherentXBar::CoherentXBar(const CoherentXBarParams &p)
+ : BaseXBar(p), system(p.system), snoopFilter(p.snoop_filter),
+ snoopResponseLatency(p.snoop_response_latency),
+ maxOutstandingSnoopCheck(p.max_outstanding_snoops),
+ maxRoutingTableSizeCheck(p.max_routing_table_size),
+ pointOfCoherency(p.point_of_coherency),
+ pointOfUnification(p.point_of_unification),
snoops(this, "snoops", "Total snoops (count)"),
snoopTraffic(this, "snoopTraffic", "Total snoop traffic (bytes)"),
// create the ports based on the size of the memory-side port and
// CPU-side port vector ports, and the presence of the default port,
// the ports are enumerated starting from zero
- for (int i = 0; i < p->port_mem_side_ports_connection_count; ++i) {
+ for (int i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
std::string portName = csprintf("%s.mem_side_port[%d]", name(), i);
RequestPort* bp = new CoherentXBarRequestPort(portName, *this, i);
memSidePorts.push_back(bp);
// see if we have a default CPU-side-port device connected and if so add
// our corresponding memory-side port
- if (p->port_default_connection_count) {
+ if (p.port_default_connection_count) {
defaultPortID = memSidePorts.size();
std::string portName = name() + ".default";
RequestPort* bp = new CoherentXBarRequestPort(portName, *this,
}
// create the CPU-side ports, once again starting at zero
- for (int i = 0; i < p->port_cpu_side_ports_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
std::string portName = csprintf("%s.cpu_side_port[%d]", name(), i);
QueuedResponsePort* bp = new CoherentXBarResponsePort(portName,
*this, i);
}
CoherentXBar *
-CoherentXBarParams::create()
+CoherentXBarParams::create() const
{
- return new CoherentXBar(this);
+ return new CoherentXBar(*this);
}
virtual void init();
- CoherentXBar(const CoherentXBarParams *p);
+ CoherentXBar(const CoherentXBarParams &p);
virtual ~CoherentXBar();
#include "debug/CommMonitor.hh"
#include "sim/stats.hh"
-CommMonitor::CommMonitor(Params* params)
+CommMonitor::CommMonitor(const Params ¶ms)
: SimObject(params),
memSidePort(name() + "-mem_side_port", *this),
cpuSidePort(name() + "-cpu_side_port", *this),
samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
- samplePeriodTicks(params->sample_period),
- samplePeriod(params->sample_period / SimClock::Float::s),
+ samplePeriodTicks(params.sample_period),
+ samplePeriod(params.sample_period / SimClock::Float::s),
stats(this, params)
{
DPRINTF(CommMonitor,
}
CommMonitor*
-CommMonitorParams::create()
+CommMonitorParams::create() const
{
- return new CommMonitor(this);
+ return new CommMonitor(*this);
}
void
}
CommMonitor::MonitorStats::MonitorStats(Stats::Group *parent,
- const CommMonitorParams *params)
+ const CommMonitorParams ¶ms)
: Stats::Group(parent),
- disableBurstLengthHists(params->disable_burst_length_hists),
+ disableBurstLengthHists(params.disable_burst_length_hists),
ADD_STAT(readBurstLengthHist,
"Histogram of burst lengths of transmitted packets"),
ADD_STAT(writeBurstLengthHist,
"Histogram of burst lengths of transmitted packets"),
- disableBandwidthHists(params->disable_bandwidth_hists),
+ disableBandwidthHists(params.disable_bandwidth_hists),
readBytes(0),
ADD_STAT(readBandwidthHist,
"Histogram of read bandwidth per sample period (bytes/s)"),
ADD_STAT(averageWriteBandwidth, "Average write bandwidth (bytes/s)",
totalWrittenBytes / simSeconds),
- disableLatencyHists(params->disable_latency_hists),
+ disableLatencyHists(params.disable_latency_hists),
ADD_STAT(readLatencyHist, "Read request-response latency"),
ADD_STAT(writeLatencyHist, "Write request-response latency"),
- disableITTDists(params->disable_itt_dists),
+ disableITTDists(params.disable_itt_dists),
ADD_STAT(ittReadRead, "Read-to-read inter transaction time"),
ADD_STAT(ittWriteWrite , "Write-to-write inter transaction time"),
ADD_STAT(ittReqReq, "Request-to-request inter transaction time"),
timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0),
- disableOutstandingHists(params->disable_outstanding_hists),
+ disableOutstandingHists(params.disable_outstanding_hists),
ADD_STAT(outstandingReadsHist, "Outstanding read transactions"),
outstandingReadReqs(0),
ADD_STAT(outstandingWritesHist, "Outstanding write transactions"),
outstandingWriteReqs(0),
- disableTransactionHists(params->disable_transaction_hists),
+ disableTransactionHists(params.disable_transaction_hists),
ADD_STAT(readTransHist,
"Histogram of read transactions per sample period"),
readTrans(0),
"Histogram of write transactions per sample period"),
writeTrans(0),
- disableAddrDists(params->disable_addr_dists),
- readAddrMask(params->read_addr_mask),
- writeAddrMask(params->write_addr_mask),
+ disableAddrDists(params.disable_addr_dists),
+ readAddrMask(params.read_addr_mask),
+ writeAddrMask(params.write_addr_mask),
ADD_STAT(readAddrDist, "Read address distribution"),
ADD_STAT(writeAddrDist, "Write address distribution")
{
using namespace Stats;
readBurstLengthHist
- .init(params->burst_length_bins)
+ .init(params.burst_length_bins)
.flags(disableBurstLengthHists ? nozero : pdf);
writeBurstLengthHist
- .init(params->burst_length_bins)
+ .init(params.burst_length_bins)
.flags(disableBurstLengthHists ? nozero : pdf);
// Stats based on received responses
readBandwidthHist
- .init(params->bandwidth_bins)
+ .init(params.bandwidth_bins)
.flags(disableBandwidthHists ? nozero : pdf);
averageReadBandwidth
// Stats based on successfully sent requests
writeBandwidthHist
- .init(params->bandwidth_bins)
+ .init(params.bandwidth_bins)
.flags(disableBandwidthHists ? (pdf | nozero) : pdf);
averageWriteBandwidth
readLatencyHist
- .init(params->latency_bins)
+ .init(params.latency_bins)
.flags(disableLatencyHists ? nozero : pdf);
writeLatencyHist
- .init(params->latency_bins)
+ .init(params.latency_bins)
.flags(disableLatencyHists ? nozero : pdf);
ittReadRead
- .init(1, params->itt_max_bin, params->itt_max_bin /
- params->itt_bins)
+ .init(1, params.itt_max_bin, params.itt_max_bin /
+ params.itt_bins)
.flags(disableITTDists ? nozero : pdf);
ittWriteWrite
- .init(1, params->itt_max_bin, params->itt_max_bin /
- params->itt_bins)
+ .init(1, params.itt_max_bin, params.itt_max_bin /
+ params.itt_bins)
.flags(disableITTDists ? nozero : pdf);
ittReqReq
- .init(1, params->itt_max_bin, params->itt_max_bin /
- params->itt_bins)
+ .init(1, params.itt_max_bin, params.itt_max_bin /
+ params.itt_bins)
.flags(disableITTDists ? nozero : pdf);
outstandingReadsHist
- .init(params->outstanding_bins)
+ .init(params.outstanding_bins)
.flags(disableOutstandingHists ? nozero : pdf);
outstandingWritesHist
- .init(params->outstanding_bins)
+ .init(params.outstanding_bins)
.flags(disableOutstandingHists ? nozero : pdf);
readTransHist
- .init(params->transaction_bins)
+ .init(params.transaction_bins)
.flags(disableTransactionHists ? nozero : pdf);
writeTransHist
- .init(params->transaction_bins)
+ .init(params.transaction_bins)
.flags(disableTransactionHists ? nozero : pdf);
readAddrDist
/** Parameters of communication monitor */
typedef CommMonitorParams Params;
- const Params* params() const
- { return reinterpret_cast<const Params*>(_params); }
+ const Params &
+ params() const
+ {
+ return reinterpret_cast<const Params &>(_params);
+ }
/**
* Constructor based on the Python params
*
* @param params Python parameters
*/
- CommMonitor(Params* params);
+ CommMonitor(const Params ¶ms);
void init() override;
void startup() override;
* that are not statistics themselves, but used to control the
* stats or track values during a sample period.
*/
- MonitorStats(Stats::Group *parent, const CommMonitorParams* params);
+ MonitorStats(Stats::Group *parent, const CommMonitorParams ¶ms);
void updateReqStats(const ProbePoints::PacketInfo& pkt, bool is_atomic,
bool expects_response);
#include "base/intmath.hh"
#include "sim/core.hh"
-DRAMPower::DRAMPower(const DRAMInterfaceParams* p, bool include_io) :
+DRAMPower::DRAMPower(const DRAMInterfaceParams &p, bool include_io) :
powerlib(libDRAMPower(getMemSpec(p), include_io))
{
}
Data::MemArchitectureSpec
-DRAMPower::getArchParams(const DRAMInterfaceParams* p)
+DRAMPower::getArchParams(const DRAMInterfaceParams &p)
{
Data::MemArchitectureSpec archSpec;
- archSpec.burstLength = p->burst_length;
- archSpec.nbrOfBanks = p->banks_per_rank;
+ archSpec.burstLength = p.burst_length;
+ archSpec.nbrOfBanks = p.banks_per_rank;
// One DRAMPower instance per rank, hence set this to 1
archSpec.nbrOfRanks = 1;
- archSpec.dataRate = p->beats_per_clock;
+ archSpec.dataRate = p.beats_per_clock;
// For now we can ignore the number of columns and rows as they
// are not used in the power calculation.
archSpec.nbrOfColumns = 0;
archSpec.nbrOfRows = 0;
- archSpec.width = p->device_bus_width;
- archSpec.nbrOfBankGroups = p->bank_groups_per_rank;
- archSpec.dll = p->dll;
+ archSpec.width = p.device_bus_width;
+ archSpec.nbrOfBankGroups = p.bank_groups_per_rank;
+ archSpec.dll = p.dll;
archSpec.twoVoltageDomains = hasTwoVDD(p);
// Keep this disabled for now until the model is firmed up.
archSpec.termination = false;
}
Data::MemTimingSpec
-DRAMPower::getTimingParams(const DRAMInterfaceParams* p)
+DRAMPower::getTimingParams(const DRAMInterfaceParams &p)
{
// Set the values that are used for power calculations and ignore
// the ones only used by the controller functionality in DRAMPower
// All DRAMPower timings are in clock cycles
Data::MemTimingSpec timingSpec;
- timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
- timingSpec.RCD = divCeil(p->tRCD, p->tCK);
- timingSpec.RL = divCeil(p->tCL, p->tCK);
- timingSpec.RP = divCeil(p->tRP, p->tCK);
- timingSpec.RFC = divCeil(p->tRFC, p->tCK);
- timingSpec.RAS = divCeil(p->tRAS, p->tCK);
+ timingSpec.RC = divCeil((p.tRAS + p.tRP), p.tCK);
+ timingSpec.RCD = divCeil(p.tRCD, p.tCK);
+ timingSpec.RL = divCeil(p.tCL, p.tCK);
+ timingSpec.RP = divCeil(p.tRP, p.tCK);
+ timingSpec.RFC = divCeil(p.tRFC, p.tCK);
+ timingSpec.RAS = divCeil(p.tRAS, p.tCK);
// Write latency is read latency - 1 cycle
// Source: B.Jacob Memory Systems Cache, DRAM, Disk
timingSpec.WL = timingSpec.RL - 1;
timingSpec.DQSCK = 0; // ignore for now
- timingSpec.RTP = divCeil(p->tRTP, p->tCK);
- timingSpec.WR = divCeil(p->tWR, p->tCK);
- timingSpec.XP = divCeil(p->tXP, p->tCK);
- timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK);
- timingSpec.XS = divCeil(p->tXS, p->tCK);
- timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK);
+ timingSpec.RTP = divCeil(p.tRTP, p.tCK);
+ timingSpec.WR = divCeil(p.tWR, p.tCK);
+ timingSpec.XP = divCeil(p.tXP, p.tCK);
+ timingSpec.XPDLL = divCeil(p.tXPDLL, p.tCK);
+ timingSpec.XS = divCeil(p.tXS, p.tCK);
+ timingSpec.XSDLL = divCeil(p.tXSDLL, p.tCK);
// Clock period in ns
- timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
+ timingSpec.clkPeriod = (p.tCK / (double)(SimClock::Int::ns));
assert(timingSpec.clkPeriod != 0);
timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
return timingSpec;
}
Data::MemPowerSpec
-DRAMPower::getPowerParams(const DRAMInterfaceParams* p)
+DRAMPower::getPowerParams(const DRAMInterfaceParams &p)
{
// All DRAMPower currents are in mA
Data::MemPowerSpec powerSpec;
- powerSpec.idd0 = p->IDD0 * 1000;
- powerSpec.idd02 = p->IDD02 * 1000;
- powerSpec.idd2p0 = p->IDD2P0 * 1000;
- powerSpec.idd2p02 = p->IDD2P02 * 1000;
- powerSpec.idd2p1 = p->IDD2P1 * 1000;
- powerSpec.idd2p12 = p->IDD2P12 * 1000;
- powerSpec.idd2n = p->IDD2N * 1000;
- powerSpec.idd2n2 = p->IDD2N2 * 1000;
- powerSpec.idd3p0 = p->IDD3P0 * 1000;
- powerSpec.idd3p02 = p->IDD3P02 * 1000;
- powerSpec.idd3p1 = p->IDD3P1 * 1000;
- powerSpec.idd3p12 = p->IDD3P12 * 1000;
- powerSpec.idd3n = p->IDD3N * 1000;
- powerSpec.idd3n2 = p->IDD3N2 * 1000;
- powerSpec.idd4r = p->IDD4R * 1000;
- powerSpec.idd4r2 = p->IDD4R2 * 1000;
- powerSpec.idd4w = p->IDD4W * 1000;
- powerSpec.idd4w2 = p->IDD4W2 * 1000;
- powerSpec.idd5 = p->IDD5 * 1000;
- powerSpec.idd52 = p->IDD52 * 1000;
- powerSpec.idd6 = p->IDD6 * 1000;
- powerSpec.idd62 = p->IDD62 * 1000;
- powerSpec.vdd = p->VDD;
- powerSpec.vdd2 = p->VDD2;
+ powerSpec.idd0 = p.IDD0 * 1000;
+ powerSpec.idd02 = p.IDD02 * 1000;
+ powerSpec.idd2p0 = p.IDD2P0 * 1000;
+ powerSpec.idd2p02 = p.IDD2P02 * 1000;
+ powerSpec.idd2p1 = p.IDD2P1 * 1000;
+ powerSpec.idd2p12 = p.IDD2P12 * 1000;
+ powerSpec.idd2n = p.IDD2N * 1000;
+ powerSpec.idd2n2 = p.IDD2N2 * 1000;
+ powerSpec.idd3p0 = p.IDD3P0 * 1000;
+ powerSpec.idd3p02 = p.IDD3P02 * 1000;
+ powerSpec.idd3p1 = p.IDD3P1 * 1000;
+ powerSpec.idd3p12 = p.IDD3P12 * 1000;
+ powerSpec.idd3n = p.IDD3N * 1000;
+ powerSpec.idd3n2 = p.IDD3N2 * 1000;
+ powerSpec.idd4r = p.IDD4R * 1000;
+ powerSpec.idd4r2 = p.IDD4R2 * 1000;
+ powerSpec.idd4w = p.IDD4W * 1000;
+ powerSpec.idd4w2 = p.IDD4W2 * 1000;
+ powerSpec.idd5 = p.IDD5 * 1000;
+ powerSpec.idd52 = p.IDD52 * 1000;
+ powerSpec.idd6 = p.IDD6 * 1000;
+ powerSpec.idd62 = p.IDD62 * 1000;
+ powerSpec.vdd = p.VDD;
+ powerSpec.vdd2 = p.VDD2;
return powerSpec;
}
Data::MemorySpecification
-DRAMPower::getMemSpec(const DRAMInterfaceParams* p)
+DRAMPower::getMemSpec(const DRAMInterfaceParams &p)
{
Data::MemorySpecification memSpec;
memSpec.memArchSpec = getArchParams(p);
}
bool
-DRAMPower::hasTwoVDD(const DRAMInterfaceParams* p)
+DRAMPower::hasTwoVDD(const DRAMInterfaceParams &p)
{
- return p->VDD2 == 0 ? false : true;
+ return p.VDD2 == 0 ? false : true;
}
uint8_t
-DRAMPower::getDataRate(const DRAMInterfaceParams* p)
+DRAMPower::getDataRate(const DRAMInterfaceParams &p)
{
- uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
- uint8_t data_rate = p->burst_length / burst_cycles;
+ uint32_t burst_cycles = divCeil(p.tBURST_MAX, p.tCK);
+ uint8_t data_rate = p.burst_length / burst_cycles;
// 4 for GDDR5
if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate != 8)
fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
* DRAMInterfaceParams to the memSpec of DRAMPower
*/
static Data::MemArchitectureSpec getArchParams(
- const DRAMInterfaceParams* p);
+ const DRAMInterfaceParams &p);
/**
* Transforms the timing parameters defined in DRAMInterfaceParams to
* the memSpec of DRAMPower
*/
- static Data::MemTimingSpec getTimingParams(const DRAMInterfaceParams* p);
+ static Data::MemTimingSpec getTimingParams(const DRAMInterfaceParams &p);
/**
* Transforms the power and current parameters defined in
* DRAMInterfaceParams to the memSpec of DRAMPower
*/
- static Data::MemPowerSpec getPowerParams(const DRAMInterfaceParams* p);
+ static Data::MemPowerSpec getPowerParams(const DRAMInterfaceParams &p);
/**
* Determine data rate, either one or two.
*/
- static uint8_t getDataRate(const DRAMInterfaceParams* p);
+ static uint8_t getDataRate(const DRAMInterfaceParams &p);
/**
* Determine if DRAM has two voltage domains (or one)
*/
- static bool hasTwoVDD(const DRAMInterfaceParams* p);
+ static bool hasTwoVDD(const DRAMInterfaceParams &p);
/**
* Return an instance of MemSpec based on the DRAMInterfaceParams
*/
- static Data::MemorySpecification getMemSpec(const DRAMInterfaceParams* p);
+ static Data::MemorySpecification getMemSpec(const DRAMInterfaceParams &p);
public:
// Instance of DRAMPower Library
libDRAMPower powerlib;
- DRAMPower(const DRAMInterfaceParams* p, bool include_io);
+ DRAMPower(const DRAMInterfaceParams &p, bool include_io);
};
#include "debug/Drain.hh"
#include "sim/system.hh"
-DRAMSim2::DRAMSim2(const Params* p) :
+DRAMSim2::DRAMSim2(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
- wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
- p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
+ wrapper(p.deviceConfigFile, p.systemConfigFile, p.filePath,
+ p.traceFile, p.range.size() / 1024 / 1024, p.enableDebug),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
sendResponseEvent([this]{ sendResponse(); }, name()),
}
DRAMSim2*
-DRAMSim2Params::create()
+DRAMSim2Params::create() const
{
- return new DRAMSim2(this);
+ return new DRAMSim2(*this);
}
public:
typedef DRAMSim2Params Params;
- DRAMSim2(const Params *p);
+ DRAMSim2(const Params &p);
/**
* Read completion callback.
#include "debug/Drain.hh"
#include "sim/system.hh"
-DRAMsim3::DRAMsim3(const Params* p) :
+DRAMsim3::DRAMsim3(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
read_cb(std::bind(&DRAMsim3::readComplete,
this, 0, std::placeholders::_1)),
write_cb(std::bind(&DRAMsim3::writeComplete,
this, 0, std::placeholders::_1)),
- wrapper(p->configFile, p->filePath, read_cb, write_cb),
+ wrapper(p.configFile, p.filePath, read_cb, write_cb),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
sendResponseEvent([this]{ sendResponse(); }, name()),
}
DRAMsim3*
-DRAMsim3Params::create()
+DRAMsim3Params::create() const
{
- return new DRAMsim3(this);
+ return new DRAMsim3(*this);
}
public:
typedef DRAMsim3Params Params;
- DRAMsim3(const Params *p);
+ DRAMsim3(const Params &p);
/**
* Read completion callback.
std::map<std::string, ExternalMaster::Handler *>
ExternalMaster::portHandlers;
-ExternalMaster::ExternalMaster(ExternalMasterParams *params) :
+ExternalMaster::ExternalMaster(const ExternalMasterParams ¶ms) :
SimObject(params),
externalPort(NULL),
- portName(params->name + ".port"),
- portType(params->port_type),
- portData(params->port_data),
- id(params->system->getRequestorId(this))
+ portName(params.name + ".port"),
+ portType(params.port_type),
+ portData(params.port_data),
+ id(params.system->getRequestorId(this))
{}
Port &
}
ExternalMaster *
-ExternalMasterParams::create()
+ExternalMasterParams::create() const
{
- return new ExternalMaster(this);
+ return new ExternalMaster(*this);
}
void
static std::map<std::string, Handler *> portHandlers;
public:
- ExternalMaster(ExternalMasterParams *params);
+ ExternalMaster(const ExternalMasterParams ¶ms);
/** Port interface. Responds only to port "port" */
Port &getPort(const std::string &if_name,
return owner.addrRanges;
}
-ExternalSlave::ExternalSlave(ExternalSlaveParams *params) :
+ExternalSlave::ExternalSlave(const ExternalSlaveParams ¶ms) :
SimObject(params),
externalPort(NULL),
- portName(params->name + ".port"),
- portType(params->port_type),
- portData(params->port_data),
- addrRanges(params->addr_ranges.begin(), params->addr_ranges.end())
+ portName(params.name + ".port"),
+ portType(params.port_type),
+ portData(params.port_data),
+ addrRanges(params.addr_ranges.begin(), params.addr_ranges.end())
{
/* Register the stub handler if it hasn't already been registered */
if (portHandlers.find("stub") == portHandlers.end())
}
ExternalSlave *
-ExternalSlaveParams::create()
+ExternalSlaveParams::create() const
{
- return new ExternalSlave(this);
+ return new ExternalSlave(*this);
}
void
static std::map<std::string, Handler *> portHandlers;
public:
- ExternalSlave(ExternalSlaveParams *params);
+ ExternalSlave(const ExternalSlaveParams ¶ms);
/** Port interface. Responds only to port "port" */
Port &getPort(const std::string &if_name,
#include "base/trace.hh"
#include "debug/HMCController.hh"
-HMCController::HMCController(const HMCControllerParams* p) :
+HMCController::HMCController(const HMCControllerParams &p) :
NoncoherentXBar(p),
- numMemSidePorts(p->port_mem_side_ports_connection_count),
+ numMemSidePorts(p.port_mem_side_ports_connection_count),
rr_counter(0)
{
- assert(p->port_cpu_side_ports_connection_count == 1);
+ assert(p.port_cpu_side_ports_connection_count == 1);
}
HMCController*
-HMCControllerParams::create()
+HMCControllerParams::create() const
{
- return new HMCController(this);
+ return new HMCController(*this);
}
// Since this module is a load distributor, all its request ports have the same
{
public:
- HMCController(const HMCControllerParams *p);
+ HMCController(const HMCControllerParams &p);
private:
}
MemChecker*
-MemCheckerParams::create()
+MemCheckerParams::create() const
{
- return new MemChecker(this);
+ return new MemChecker(*this);
}
public:
- MemChecker(const MemCheckerParams *p)
+ MemChecker(const MemCheckerParams &p)
: SimObject(p),
nextSerial(SERIAL_INITIAL)
{}
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
-MemCheckerMonitor::MemCheckerMonitor(Params* params)
+MemCheckerMonitor::MemCheckerMonitor(const Params ¶ms)
: SimObject(params),
memSidePort(name() + "-memSidePort", *this),
cpuSidePort(name() + "-cpuSidePort", *this),
- warnOnly(params->warn_only),
- memchecker(params->memchecker)
+ warnOnly(params.warn_only),
+ memchecker(params.memchecker)
{}
MemCheckerMonitor::~MemCheckerMonitor()
{}
MemCheckerMonitor*
-MemCheckerMonitorParams::create()
+MemCheckerMonitorParams::create() const
{
- return new MemCheckerMonitor(this);
+ return new MemCheckerMonitor(*this);
}
void
/** Parameters of memchecker monitor */
typedef MemCheckerMonitorParams Params;
- const Params* params() const
- { return reinterpret_cast<const Params*>(_params); }
+ const Params &
+ params() const
+ {
+ return reinterpret_cast<const Params &>(_params);
+ }
/**
* Constructor based on the Python params
*
* @param params Python parameters
*/
- MemCheckerMonitor(Params* params);
+ MemCheckerMonitor(const Params ¶ms);
/** Destructor */
~MemCheckerMonitor();
using namespace std;
-MemCtrl::MemCtrl(const MemCtrlParams* p) :
+MemCtrl::MemCtrl(const MemCtrlParams &p) :
QoS::MemCtrl(p),
port(name() + ".port", *this), isTimingMode(false),
retryRdReq(false), retryWrReq(false),
nextReqEvent([this]{ processNextReqEvent(); }, name()),
respondEvent([this]{ processRespondEvent(); }, name()),
- dram(p->dram), nvm(p->nvm),
+ dram(p.dram), nvm(p.nvm),
readBufferSize((dram ? dram->readBufferSize : 0) +
(nvm ? nvm->readBufferSize : 0)),
writeBufferSize((dram ? dram->writeBufferSize : 0) +
(nvm ? nvm->writeBufferSize : 0)),
- writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
- writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
- minWritesPerSwitch(p->min_writes_per_switch),
+ writeHighThreshold(writeBufferSize * p.write_high_thresh_perc / 100.0),
+ writeLowThreshold(writeBufferSize * p.write_low_thresh_perc / 100.0),
+ minWritesPerSwitch(p.min_writes_per_switch),
writesThisTime(0), readsThisTime(0),
- memSchedPolicy(p->mem_sched_policy),
- frontendLatency(p->static_frontend_latency),
- backendLatency(p->static_backend_latency),
- commandWindow(p->command_window),
+ memSchedPolicy(p.mem_sched_policy),
+ frontendLatency(p.static_frontend_latency),
+ backendLatency(p.static_backend_latency),
+ commandWindow(p.command_window),
nextBurstAt(0), prevArrival(0),
nextReqTime(0),
stats(*this)
{
DPRINTF(MemCtrl, "Setting up controller\n");
- readQueue.resize(p->qos_priorities);
- writeQueue.resize(p->qos_priorities);
+ readQueue.resize(p.qos_priorities);
+ writeQueue.resize(p.qos_priorities);
// Hook up interfaces to the controller
if (dram)
fatal_if(!dram && !nvm, "Memory controller must have an interface");
// perform a basic check of the write thresholds
- if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
+ if (p.write_low_thresh_perc >= p.write_high_thresh_perc)
fatal("Write buffer low threshold %d must be smaller than the "
- "high threshold %d\n", p->write_low_thresh_perc,
- p->write_high_thresh_perc);
+ "high threshold %d\n", p.write_low_thresh_perc,
+ p.write_high_thresh_perc);
}
void
}
MemCtrl*
-MemCtrlParams::create()
+MemCtrlParams::create() const
{
- return new MemCtrl(this);
+ return new MemCtrl(*this);
}
public:
- MemCtrl(const MemCtrlParams* p);
+ MemCtrl(const MemCtrlParams &p);
/**
* Ensure that all interfaced have drained commands
#include "params/MemDelay.hh"
#include "params/SimpleMemDelay.hh"
-MemDelay::MemDelay(const MemDelayParams *p)
+MemDelay::MemDelay(const MemDelayParams &p)
: ClockedObject(p),
requestPort(name() + "-mem_side_port", *this),
responsePort(name() + "-cpu_side_port", *this),
-SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
+SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams &p)
: MemDelay(p),
- readReqDelay(p->read_req),
- readRespDelay(p->read_resp),
- writeReqDelay(p->write_req),
- writeRespDelay(p->write_resp)
+ readReqDelay(p.read_req),
+ readRespDelay(p.read_resp),
+ writeReqDelay(p.write_req),
+ writeRespDelay(p.write_resp)
{
}
SimpleMemDelay *
-SimpleMemDelayParams::create()
+SimpleMemDelayParams::create() const
{
- return new SimpleMemDelay(this);
+ return new SimpleMemDelay(*this);
}
{
public:
- MemDelay(const MemDelayParams *params);
+ MemDelay(const MemDelayParams ¶ms);
void init() override;
class SimpleMemDelay : public MemDelay
{
public:
- SimpleMemDelay(const SimpleMemDelayParams *params);
+ SimpleMemDelay(const SimpleMemDelayParams ¶ms);
protected:
Tick delayReq(PacketPtr pkt) override;
using namespace std;
using namespace Data;
-MemInterface::MemInterface(const MemInterfaceParams* _p)
+MemInterface::MemInterface(const MemInterfaceParams &_p)
: AbstractMemory(_p),
- addrMapping(_p->addr_mapping),
- burstSize((_p->devices_per_rank * _p->burst_length *
- _p->device_bus_width) / 8),
- deviceSize(_p->device_size),
- deviceRowBufferSize(_p->device_rowbuffer_size),
- devicesPerRank(_p->devices_per_rank),
+ addrMapping(_p.addr_mapping),
+ burstSize((_p.devices_per_rank * _p.burst_length *
+ _p.device_bus_width) / 8),
+ deviceSize(_p.device_size),
+ deviceRowBufferSize(_p.device_rowbuffer_size),
+ devicesPerRank(_p.devices_per_rank),
rowBufferSize(devicesPerRank * deviceRowBufferSize),
burstsPerRowBuffer(rowBufferSize / burstSize),
burstsPerStripe(range.interleaved() ?
range.granularity() / burstSize : 1),
- ranksPerChannel(_p->ranks_per_channel),
- banksPerRank(_p->banks_per_rank), rowsPerBank(0),
- tCK(_p->tCK), tCS(_p->tCS), tBURST(_p->tBURST),
- tRTW(_p->tRTW),
- tWTR(_p->tWTR),
- readBufferSize(_p->read_buffer_size),
- writeBufferSize(_p->write_buffer_size)
+ ranksPerChannel(_p.ranks_per_channel),
+ banksPerRank(_p.banks_per_rank), rowsPerBank(0),
+ tCK(_p.tCK), tCS(_p.tCS), tBURST(_p.tBURST),
+ tRTW(_p.tRTW),
+ tWTR(_p.tWTR),
+ readBufferSize(_p.read_buffer_size),
+ writeBufferSize(_p.write_buffer_size)
{}
void
}
}
-DRAMInterface::DRAMInterface(const DRAMInterfaceParams* _p)
+DRAMInterface::DRAMInterface(const DRAMInterfaceParams &_p)
: MemInterface(_p),
- bankGroupsPerRank(_p->bank_groups_per_rank),
- bankGroupArch(_p->bank_groups_per_rank > 0),
- tCL(_p->tCL),
- tBURST_MIN(_p->tBURST_MIN), tBURST_MAX(_p->tBURST_MAX),
- tCCD_L_WR(_p->tCCD_L_WR), tCCD_L(_p->tCCD_L), tRCD(_p->tRCD),
- tRP(_p->tRP), tRAS(_p->tRAS), tWR(_p->tWR), tRTP(_p->tRTP),
- tRFC(_p->tRFC), tREFI(_p->tREFI), tRRD(_p->tRRD), tRRD_L(_p->tRRD_L),
- tPPD(_p->tPPD), tAAD(_p->tAAD),
- tXAW(_p->tXAW), tXP(_p->tXP), tXS(_p->tXS),
- clkResyncDelay(tCL + _p->tBURST_MAX),
- dataClockSync(_p->data_clock_sync),
+ bankGroupsPerRank(_p.bank_groups_per_rank),
+ bankGroupArch(_p.bank_groups_per_rank > 0),
+ tCL(_p.tCL),
+ tBURST_MIN(_p.tBURST_MIN), tBURST_MAX(_p.tBURST_MAX),
+ tCCD_L_WR(_p.tCCD_L_WR), tCCD_L(_p.tCCD_L), tRCD(_p.tRCD),
+ tRP(_p.tRP), tRAS(_p.tRAS), tWR(_p.tWR), tRTP(_p.tRTP),
+ tRFC(_p.tRFC), tREFI(_p.tREFI), tRRD(_p.tRRD), tRRD_L(_p.tRRD_L),
+ tPPD(_p.tPPD), tAAD(_p.tAAD),
+ tXAW(_p.tXAW), tXP(_p.tXP), tXS(_p.tXS),
+ clkResyncDelay(tCL + _p.tBURST_MAX),
+ dataClockSync(_p.data_clock_sync),
burstInterleave(tBURST != tBURST_MIN),
- twoCycleActivate(_p->two_cycle_activate),
- activationLimit(_p->activation_limit),
- wrToRdDlySameBG(tCL + _p->tBURST_MAX + _p->tWTR_L),
- rdToWrDlySameBG(_p->tRTW + _p->tBURST_MAX),
- pageMgmt(_p->page_policy),
- maxAccessesPerRow(_p->max_accesses_per_row),
+ twoCycleActivate(_p.two_cycle_activate),
+ activationLimit(_p.activation_limit),
+ wrToRdDlySameBG(tCL + _p.tBURST_MAX + _p.tWTR_L),
+ rdToWrDlySameBG(_p.tRTW + _p.tBURST_MAX),
+ pageMgmt(_p.page_policy),
+ maxAccessesPerRow(_p.max_accesses_per_row),
timeStampOffset(0), activeRank(0),
- enableDRAMPowerdown(_p->enable_dram_powerdown),
+ enableDRAMPowerdown(_p.enable_dram_powerdown),
lastStatsResetTick(0),
stats(*this)
{
}
DRAMInterface*
-DRAMInterfaceParams::create()
+DRAMInterfaceParams::create() const
{
- return new DRAMInterface(this);
+ return new DRAMInterface(*this);
}
-DRAMInterface::Rank::Rank(const DRAMInterfaceParams* _p,
+DRAMInterface::Rank::Rank(const DRAMInterfaceParams &_p,
int _rank, DRAMInterface& _dram)
: EventManager(&_dram), dram(_dram),
pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
refreshState(REF_IDLE), inLowPowerState(false), rank(_rank),
readEntries(0), writeEntries(0), outstandingEvents(0),
- wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank),
- numBanksActive(0), actTicks(_p->activation_limit, 0), lastBurstTick(0),
+ wakeUpAllowedAt(0), power(_p, false), banks(_p.banks_per_rank),
+ numBanksActive(0), actTicks(_p.activation_limit, 0), lastBurstTick(0),
writeDoneEvent([this]{ processWriteDoneEvent(); }, name()),
activateEvent([this]{ processActivateEvent(); }, name()),
prechargeEvent([this]{ processPrechargeEvent(); }, name()),
wakeUpEvent([this]{ processWakeUpEvent(); }, name()),
stats(_dram, *this)
{
- for (int b = 0; b < _p->banks_per_rank; b++) {
+ for (int b = 0; b < _p.banks_per_rank; b++) {
banks[b].bank = b;
// GDDR addressing of banks to BG is linear.
// Here we assume that all DRAM generations address bank groups as
// follows:
- if (_p->bank_groups_per_rank > 0) {
+ if (_p.bank_groups_per_rank > 0) {
// Simply assign lower bits to bank group in order to
// rotate across bank groups as banks are incremented
// e.g. with 4 banks per bank group and 16 banks total:
// banks 1,5,9,13 are in bank group 1
// banks 2,6,10,14 are in bank group 2
// banks 3,7,11,15 are in bank group 3
- banks[b].bankgr = b % _p->bank_groups_per_rank;
+ banks[b].bankgr = b % _p.bank_groups_per_rank;
} else {
// No bank groups; simply assign to bank number
banks[b].bankgr = b;
rank.computeStats();
}
-NVMInterface::NVMInterface(const NVMInterfaceParams* _p)
+NVMInterface::NVMInterface(const NVMInterfaceParams &_p)
: MemInterface(_p),
- maxPendingWrites(_p->max_pending_writes),
- maxPendingReads(_p->max_pending_reads),
- twoCycleRdWr(_p->two_cycle_rdwr),
- tREAD(_p->tREAD), tWRITE(_p->tWRITE), tSEND(_p->tSEND),
+ maxPendingWrites(_p.max_pending_writes),
+ maxPendingReads(_p.max_pending_reads),
+ twoCycleRdWr(_p.two_cycle_rdwr),
+ tREAD(_p.tREAD), tWRITE(_p.tWRITE), tSEND(_p.tSEND),
stats(*this),
writeRespondEvent([this]{ processWriteRespondEvent(); }, name()),
readReadyEvent([this]{ processReadReadyEvent(); }, name()),
}
NVMInterface*
-NVMInterfaceParams::create()
+NVMInterfaceParams::create() const
{
- return new NVMInterface(this);
+ return new NVMInterface(*this);
}
-NVMInterface::Rank::Rank(const NVMInterfaceParams* _p,
+NVMInterface::Rank::Rank(const NVMInterfaceParams &_p,
int _rank, NVMInterface& _nvm)
- : EventManager(&_nvm), rank(_rank), banks(_p->banks_per_rank)
+ : EventManager(&_nvm), rank(_rank), banks(_p.banks_per_rank)
{
- for (int b = 0; b < _p->banks_per_rank; b++) {
+ for (int b = 0; b < _p.banks_per_rank; b++) {
banks[b].bank = b;
// No bank groups; simply assign to bank number
banks[b].bankgr = b;
virtual void addRankToRankDelay(Tick cmd_at) = 0;
typedef MemInterfaceParams Params;
- MemInterface(const Params* _p);
+ MemInterface(const Params &_p);
};
/**
*/
Tick lastBurstTick;
- Rank(const DRAMInterfaceParams* _p, int _rank,
+ Rank(const DRAMInterfaceParams &_p, int _rank,
DRAMInterface& _dram);
const std::string name() const { return csprintf("%d", rank); }
*/
void checkRefreshState(uint8_t rank);
- DRAMInterface(const DRAMInterfaceParams* _p);
+ DRAMInterface(const DRAMInterfaceParams &_p);
};
/**
*/
std::vector<Bank> banks;
- Rank(const NVMInterfaceParams* _p, int _rank,
+ Rank(const NVMInterfaceParams &_p, int _rank,
NVMInterface& _nvm);
};
std::pair<Tick, Tick>
doBurstAccess(MemPacket* pkt, Tick next_burst_at);
- NVMInterface(const NVMInterfaceParams* _p);
+ NVMInterface(const NVMInterfaceParams &_p);
};
#endif //__MEM_INTERFACE_HH__
public:
[[deprecated(
"MemObject is deprecated. Use ClockedObject or SimObject instead")]]
- MemObject(const MemObjectParams *params) : ClockedObject(params)
+ MemObject(const MemObjectParams ¶ms) : ClockedObject(params)
{}
};
#include "debug/NoncoherentXBar.hh"
#include "debug/XBar.hh"
-NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
+NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams &p)
: BaseXBar(p)
{
// create the ports based on the size of the memory-side port and
// CPU-side port vector ports, and the presence of the default port,
// the ports are enumerated starting from zero
- for (int i = 0; i < p->port_mem_side_ports_connection_count; ++i) {
+ for (int i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
std::string portName = csprintf("%s.mem_side_port[%d]", name(), i);
RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this, i);
memSidePorts.push_back(bp);
// see if we have a default CPU-side-port device connected and if so add
// our corresponding memory-side port
- if (p->port_default_connection_count) {
+ if (p.port_default_connection_count) {
defaultPortID = memSidePorts.size();
std::string portName = name() + ".default";
RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this,
}
// create the CPU-side ports, once again starting at zero
- for (int i = 0; i < p->port_cpu_side_ports_connection_count; ++i) {
+ for (int i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
std::string portName = csprintf("%s.cpu_side_ports[%d]", name(), i);
QueuedResponsePort* bp = new NoncoherentXBarResponsePort(portName,
*this, i);
}
NoncoherentXBar*
-NoncoherentXBarParams::create()
+NoncoherentXBarParams::create() const
{
- return new NoncoherentXBar(this);
+ return new NoncoherentXBar(*this);
}
public:
- NoncoherentXBar(const NoncoherentXBarParams *p);
+ NoncoherentXBar(const NoncoherentXBarParams &p);
virtual ~NoncoherentXBar();
};
#include "params/BaseMemProbe.hh"
-BaseMemProbe::BaseMemProbe(BaseMemProbeParams *p)
+BaseMemProbe::BaseMemProbe(const BaseMemProbeParams &p)
: SimObject(p)
{
}
void
BaseMemProbe::regProbeListeners()
{
- const BaseMemProbeParams *p(
- dynamic_cast<const BaseMemProbeParams *>(params()));
- assert(p);
+ const BaseMemProbeParams &p =
+ dynamic_cast<const BaseMemProbeParams &>(params());
- listeners.resize(p->manager.size());
- for (int i = 0; i < p->manager.size(); i++) {
- ProbeManager *const mgr(p->manager[i]->getProbeManager());
- listeners[i].reset(new PacketListener(*this, mgr, p->probe_name));
+ listeners.resize(p.manager.size());
+ for (int i = 0; i < p.manager.size(); i++) {
+ ProbeManager *const mgr(p.manager[i]->getProbeManager());
+ listeners[i].reset(new PacketListener(*this, mgr, p.probe_name));
}
}
class BaseMemProbe : public SimObject
{
public:
- BaseMemProbe(BaseMemProbeParams *params);
+ BaseMemProbe(const BaseMemProbeParams ¶ms);
void regProbeListeners() override;
#include "base/intmath.hh"
#include "params/MemFootprintProbe.hh"
-MemFootprintProbe::MemFootprintProbe(MemFootprintProbeParams *p)
+MemFootprintProbe::MemFootprintProbe(const MemFootprintProbeParams &p)
: BaseMemProbe(p),
- cacheLineSizeLg2(floorLog2(p->system->cacheLineSize())),
- pageSizeLg2(floorLog2(p->page_size)),
- totalCacheLinesInMem(p->system->memSize() / p->system->cacheLineSize()),
- totalPagesInMem(p->system->memSize() / p->page_size),
+ cacheLineSizeLg2(floorLog2(p.system->cacheLineSize())),
+ pageSizeLg2(floorLog2(p.page_size)),
+ totalCacheLinesInMem(p.system->memSize() / p.system->cacheLineSize()),
+ totalPagesInMem(p.system->memSize() / p.page_size),
cacheLines(),
cacheLinesAll(),
pages(),
pagesAll(),
- system(p->system)
+ system(p.system)
{
fatal_if(!isPowerOf2(system->cacheLineSize()),
"MemFootprintProbe expects cache line size is power of 2.");
- fatal_if(!isPowerOf2(p->page_size),
+ fatal_if(!isPowerOf2(p.page_size),
"MemFootprintProbe expects page size parameter is power of 2");
}
}
MemFootprintProbe *
-MemFootprintProbeParams::create()
+MemFootprintProbeParams::create() const
{
- return new MemFootprintProbe(this);
+ return new MemFootprintProbe(*this);
}
public:
typedef std::unordered_set<Addr> AddrSet;
- MemFootprintProbe(MemFootprintProbeParams *p);
+ MemFootprintProbe(const MemFootprintProbeParams &p);
void regStats() override;
// Fix footprint tracking state on stat reset
void statReset();
#include "proto/packet.pb.h"
#include "sim/system.hh"
-MemTraceProbe::MemTraceProbe(MemTraceProbeParams *p)
+MemTraceProbe::MemTraceProbe(const MemTraceProbeParams &p)
: BaseMemProbe(p),
traceStream(nullptr),
- system(p->system),
- withPC(p->with_pc)
+ system(p.system),
+ withPC(p.with_pc)
{
std::string filename;
- if (p->trace_file != "") {
+ if (p.trace_file != "") {
// If the trace file is not specified as an absolute path,
// append the current simulation output directory
- filename = simout.resolve(p->trace_file);
+ filename = simout.resolve(p.trace_file);
const std::string suffix = ".gz";
// If trace_compress has been set, check the suffix. Append
// accordingly.
- if (p->trace_compress &&
+ if (p.trace_compress &&
filename.compare(filename.size() - suffix.size(), suffix.size(),
suffix) != 0)
filename = filename + suffix;
// Generate a filename from the name of the SimObject. Append .trc
// and .gz if we want compression enabled.
filename = simout.resolve(name() + ".trc" +
- (p->trace_compress ? ".gz" : ""));
+ (p.trace_compress ? ".gz" : ""));
}
traceStream = new ProtoOutputStream(filename);
MemTraceProbe *
-MemTraceProbeParams::create()
+MemTraceProbeParams::create() const
{
- return new MemTraceProbe(this);
+ return new MemTraceProbe(*this);
}
class MemTraceProbe : public BaseMemProbe
{
public:
- MemTraceProbe(MemTraceProbeParams *params);
+ MemTraceProbe(const MemTraceProbeParams ¶ms);
protected:
void handleRequest(const ProbePoints::PacketInfo &pkt_info) override;
#include "params/StackDistProbe.hh"
#include "sim/system.hh"
-StackDistProbe::StackDistProbe(StackDistProbeParams *p)
+StackDistProbe::StackDistProbe(const StackDistProbeParams &p)
: BaseMemProbe(p),
- lineSize(p->line_size),
- disableLinearHists(p->disable_linear_hists),
- disableLogHists(p->disable_log_hists),
- calc(p->verify)
+ lineSize(p.line_size),
+ disableLinearHists(p.disable_linear_hists),
+ disableLogHists(p.disable_log_hists),
+ calc(p.verify)
{
- fatal_if(p->system->cacheLineSize() > p->line_size,
+ fatal_if(p.system->cacheLineSize() > p.line_size,
"The stack distance probe must use a cache line size that is "
"larger or equal to the system's cahce line size.");
}
{
BaseMemProbe::regStats();
- const StackDistProbeParams *p(
- dynamic_cast<const StackDistProbeParams *>(params()));
- assert(p);
+ const StackDistProbeParams &p =
+ dynamic_cast<const StackDistProbeParams &>(params());
using namespace Stats;
readLinearHist
- .init(p->linear_hist_bins)
+ .init(p.linear_hist_bins)
.name(name() + ".readLinearHist")
.desc("Reads linear distribution")
.flags(disableLinearHists ? nozero : pdf);
readLogHist
- .init(p->log_hist_bins)
+ .init(p.log_hist_bins)
.name(name() + ".readLogHist")
.desc("Reads logarithmic distribution")
.flags(disableLogHists ? nozero : pdf);
writeLinearHist
- .init(p->linear_hist_bins)
+ .init(p.linear_hist_bins)
.name(name() + ".writeLinearHist")
.desc("Writes linear distribution")
.flags(disableLinearHists ? nozero : pdf);
writeLogHist
- .init(p->log_hist_bins)
+ .init(p.log_hist_bins)
.name(name() + ".writeLogHist")
.desc("Writes logarithmic distribution")
.flags(disableLogHists ? nozero : pdf);
StackDistProbe *
-StackDistProbeParams::create()
+StackDistProbeParams::create() const
{
- return new StackDistProbe(this);
+ return new StackDistProbe(*this);
}
class StackDistProbe : public BaseMemProbe
{
public:
- StackDistProbe(StackDistProbeParams *params);
+ StackDistProbe(const StackDistProbeParams ¶ms);
void regStats() override;
namespace QoS {
-MemCtrl::MemCtrl(const QoSMemCtrlParams * p)
+MemCtrl::MemCtrl(const QoSMemCtrlParams &p)
: ClockedObject(p),
- policy(p->qos_policy),
- turnPolicy(p->qos_turnaround_policy),
+ policy(p.qos_policy),
+ turnPolicy(p.qos_turnaround_policy),
queuePolicy(QueuePolicy::create(p)),
- _numPriorities(p->qos_priorities),
- qosPriorityEscalation(p->qos_priority_escalation),
- qosSyncroScheduler(p->qos_syncro_scheduler),
+ _numPriorities(p.qos_priorities),
+ qosPriorityEscalation(p.qos_priority_escalation),
+ qosSyncroScheduler(p.qos_syncro_scheduler),
totalReadQueueSize(0), totalWriteQueueSize(0),
busState(READ), busStateNext(READ),
stats(*this),
- _system(p->system)
+ _system(p.system)
{
// Set the priority policy
if (policy) {
*
* @param p pointer to QoSMemCtrl parameters
*/
- MemCtrl(const QoSMemCtrlParams*);
+ MemCtrl(const QoSMemCtrlParams &);
virtual ~MemCtrl();
namespace QoS {
-MemSinkCtrl::MemSinkCtrl(const QoSMemSinkCtrlParams* p)
- : MemCtrl(p), requestLatency(p->request_latency),
- responseLatency(p->response_latency),
- memoryPacketSize(p->memory_packet_size),
- readBufferSize(p->read_buffer_size),
- writeBufferSize(p->write_buffer_size), port(name() + ".port", *this),
- interface(p->interface),
+MemSinkCtrl::MemSinkCtrl(const QoSMemSinkCtrlParams &p)
+ : MemCtrl(p), requestLatency(p.request_latency),
+ responseLatency(p.response_latency),
+ memoryPacketSize(p.memory_packet_size),
+ readBufferSize(p.read_buffer_size),
+ writeBufferSize(p.write_buffer_size), port(name() + ".port", *this),
+ interface(p.interface),
retryRdReq(false), retryWrReq(false), nextRequest(0), nextReqEvent(this)
{
// Resize read and write queue to allocate space
} // namespace QoS
QoS::MemSinkCtrl*
-QoSMemSinkCtrlParams::create()
+QoSMemSinkCtrlParams::create() const
{
- return new QoS::MemSinkCtrl(this);
+ return new QoS::MemSinkCtrl(*this);
}
-QoSMemSinkInterface::QoSMemSinkInterface(const QoSMemSinkInterfaceParams* _p)
+QoSMemSinkInterface::QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p)
: AbstractMemory(_p)
{
}
QoSMemSinkInterface*
-QoSMemSinkInterfaceParams::create()
+QoSMemSinkInterfaceParams::create() const
{
- return new QoSMemSinkInterface(this);
+ return new QoSMemSinkInterface(*this);
}
*
* @param p QoS Memory Sink configuration parameters
*/
- MemSinkCtrl(const QoSMemSinkCtrlParams*);
+ MemSinkCtrl(const QoSMemSinkCtrlParams &);
virtual ~MemSinkCtrl();
/** Pointer to the controller */
QoS::MemSinkCtrl* ctrl;
- QoSMemSinkInterface(const QoSMemSinkInterfaceParams* _p);
+ QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p);
};
namespace QoS {
-Policy::Policy(const Params* p)
+Policy::Policy(const Params &p)
: SimObject(p)
{}
{
public:
using Params = QoSPolicyParams;
- Policy(const Params* p);
+ Policy(const Params &p);
virtual ~Policy();
namespace QoS {
-FixedPriorityPolicy::FixedPriorityPolicy(const Params* p)
- : Policy(p), defaultPriority(p->qos_fixed_prio_default_prio)
+FixedPriorityPolicy::FixedPriorityPolicy(const Params &p)
+ : Policy(p), defaultPriority(p.qos_fixed_prio_default_prio)
{}
FixedPriorityPolicy::~FixedPriorityPolicy()
} // namespace QoS
QoS::FixedPriorityPolicy *
-QoSFixedPriorityPolicyParams::create()
+QoSFixedPriorityPolicyParams::create() const
{
- return new QoS::FixedPriorityPolicy(this);
+ return new QoS::FixedPriorityPolicy(*this);
}
using Params = QoSFixedPriorityPolicyParams;
public:
- FixedPriorityPolicy(const Params*);
+ FixedPriorityPolicy(const Params &);
virtual ~FixedPriorityPolicy();
void init() override;
namespace QoS {
-PropFairPolicy::PropFairPolicy(const Params* p)
- : Policy(p), weight(p->weight)
+PropFairPolicy::PropFairPolicy(const Params &p)
+ : Policy(p), weight(p.weight)
{
fatal_if(weight < 0 || weight > 1,
"weight must be a value between 0 and 1");
} // namespace QoS
QoS::PropFairPolicy *
-QoSPropFairPolicyParams::create()
+QoSPropFairPolicyParams::create() const
{
- return new QoS::PropFairPolicy(this);
+ return new QoS::PropFairPolicy(*this);
}
class PropFairPolicy : public Policy
{
using Params = QoSPropFairPolicyParams;
- const Params *params() const
- { return static_cast<const Params *>(_params); }
+ const Params &
+ params() const
+ {
+ return static_cast<const Params &>(_params);
+ }
public:
- PropFairPolicy(const Params*);
+ PropFairPolicy(const Params &);
virtual ~PropFairPolicy();
/**
namespace QoS {
QueuePolicy*
-QueuePolicy::create(const QoSMemCtrlParams* p)
+QueuePolicy::create(const QoSMemCtrlParams &p)
{
- switch (p->qos_q_policy) {
+ switch (p.qos_q_policy) {
case Enums::QoSQPolicy::fifo:
return new FifoQueuePolicy(p);
case Enums::QoSQPolicy::lrg:
* @param p QoS::MemCtrl parameter variable
* @return Pointer to the QueuePolicy
*/
- static QueuePolicy* create(const QoSMemCtrlParams* p);
+ static QueuePolicy* create(const QoSMemCtrlParams &p);
/**
* This method is called by the memory controller after it enqueues a
virtual ~QueuePolicy() {};
protected:
- QueuePolicy(const QoSMemCtrlParams* p)
+ QueuePolicy(const QoSMemCtrlParams &p)
: memCtrl(nullptr)
{}
class LifoQueuePolicy : public QueuePolicy
{
public:
- LifoQueuePolicy(const QoSMemCtrlParams* p)
+ LifoQueuePolicy(const QoSMemCtrlParams &p)
: QueuePolicy(p)
{}
class FifoQueuePolicy : public QueuePolicy
{
public:
- FifoQueuePolicy(const QoSMemCtrlParams* p)
+ FifoQueuePolicy(const QoSMemCtrlParams &p)
: QueuePolicy(p)
{}
class LrgQueuePolicy : public QueuePolicy
{
public:
- LrgQueuePolicy(const QoSMemCtrlParams* p)
+ LrgQueuePolicy(const QoSMemCtrlParams &p)
: QueuePolicy(p)
{}
using Params = QoSTurnaroundPolicyParams;
public:
- TurnaroundPolicy(const Params* p) : SimObject(p) {};
+ TurnaroundPolicy(const Params &p) : SimObject(p) {};
virtual ~TurnaroundPolicy() {};
namespace QoS {
-TurnaroundPolicyIdeal::TurnaroundPolicyIdeal(const Params* p)
+TurnaroundPolicyIdeal::TurnaroundPolicyIdeal(const Params &p)
: TurnaroundPolicy(p)
{}
} // namespace QoS
QoS::TurnaroundPolicyIdeal *
-QoSTurnaroundPolicyIdealParams::create()
+QoSTurnaroundPolicyIdealParams::create() const
{
- return new QoS::TurnaroundPolicyIdeal(this);
+ return new QoS::TurnaroundPolicyIdeal(*this);
}
class TurnaroundPolicyIdeal: public TurnaroundPolicy
{
public:
- TurnaroundPolicyIdeal(const Params*);
+ TurnaroundPolicyIdeal(const Params &);
virtual ~TurnaroundPolicyIdeal();
#include "mem/ruby/network/BasicLink.hh"
-BasicLink::BasicLink(const Params *p)
+BasicLink::BasicLink(const Params &p)
: SimObject(p)
{
- m_latency = p->latency;
- m_bandwidth_factor = p->bandwidth_factor;
- m_weight = p->weight;
- mVnets = p->supported_vnets;
+ m_latency = p.latency;
+ m_bandwidth_factor = p.bandwidth_factor;
+ m_weight = p.weight;
+ mVnets = p.supported_vnets;
}
void
}
BasicLink *
-BasicLinkParams::create()
+BasicLinkParams::create() const
{
- return new BasicLink(this);
+ return new BasicLink(*this);
}
-BasicExtLink::BasicExtLink(const Params *p)
+BasicExtLink::BasicExtLink(const Params &p)
: BasicLink(p)
{
}
BasicExtLink *
-BasicExtLinkParams::create()
+BasicExtLinkParams::create() const
{
- return new BasicExtLink(this);
+ return new BasicExtLink(*this);
}
-BasicIntLink::BasicIntLink(const Params *p)
+BasicIntLink::BasicIntLink(const Params &p)
: BasicLink(p)
{
}
BasicIntLink *
-BasicIntLinkParams::create()
+BasicIntLinkParams::create() const
{
- return new BasicIntLink(this);
+ return new BasicIntLink(*this);
}
{
public:
typedef BasicLinkParams Params;
- BasicLink(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ BasicLink(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
void init();
{
public:
typedef BasicExtLinkParams Params;
- BasicExtLink(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ BasicExtLink(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
friend class Topology;
};
{
public:
typedef BasicIntLinkParams Params;
- BasicIntLink(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ BasicIntLink(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
friend class Topology;
};
#include "mem/ruby/network/BasicRouter.hh"
-BasicRouter::BasicRouter(const Params *p)
+BasicRouter::BasicRouter(const Params &p)
: ClockedObject(p)
{
- m_id = p->router_id;
- m_latency = p->latency;
+ m_id = p.router_id;
+ m_latency = p.latency;
}
void
}
BasicRouter *
-BasicRouterParams::create()
+BasicRouterParams::create() const
{
- return new BasicRouter(this);
+ return new BasicRouter(*this);
}
{
public:
typedef BasicRouterParams Params;
- BasicRouter(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ BasicRouter(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
void init();
using namespace std;
using m5::stl_helpers::operator<<;
-MessageBuffer::MessageBuffer(const Params *p)
+MessageBuffer::MessageBuffer(const Params &p)
: SimObject(p), m_stall_map_size(0),
- m_max_size(p->buffer_size), m_time_last_time_size_checked(0),
+ m_max_size(p.buffer_size), m_time_last_time_size_checked(0),
m_time_last_time_enqueue(0), m_time_last_time_pop(0),
- m_last_arrival_time(0), m_strict_fifo(p->ordered),
- m_randomization(p->randomization),
- m_allow_zero_latency(p->allow_zero_latency)
+ m_last_arrival_time(0), m_strict_fifo(p.ordered),
+ m_randomization(p.randomization),
+ m_allow_zero_latency(p.allow_zero_latency)
{
m_msg_counter = 0;
m_consumer = NULL;
}
MessageBuffer *
-MessageBufferParams::create()
+MessageBufferParams::create() const
{
- return new MessageBuffer(this);
+ return new MessageBuffer(*this);
}
{
public:
typedef MessageBufferParams Params;
- MessageBuffer(const Params *p);
+ MessageBuffer(const Params &p);
void reanalyzeMessages(Addr addr, Tick current_time);
void reanalyzeAllMessages(Tick current_time);
uint32_t Network::m_control_msg_size;
uint32_t Network::m_data_msg_size;
-Network::Network(const Params *p)
+Network::Network(const Params &p)
: ClockedObject(p)
{
- m_virtual_networks = p->number_of_virtual_networks;
- m_control_msg_size = p->control_msg_size;
+ m_virtual_networks = p.number_of_virtual_networks;
+ m_control_msg_size = p.control_msg_size;
- fatal_if(p->data_msg_size > p->ruby_system->getBlockSizeBytes(),
+ fatal_if(p.data_msg_size > p.ruby_system->getBlockSizeBytes(),
"%s: data message size > cache line size", name());
- m_data_msg_size = p->data_msg_size + m_control_msg_size;
+ m_data_msg_size = p.data_msg_size + m_control_msg_size;
- params()->ruby_system->registerNetwork(this);
+ params().ruby_system->registerNetwork(this);
// Populate localNodeVersions with the version of each MachineType in
// this network. This will be used to compute a global to local ID.
// ext_node per ext_link and it points to an AbstractController.
// For RubySystems with one network global and local ID are the same.
std::unordered_map<MachineType, std::vector<NodeID>> localNodeVersions;
- for (auto &it : params()->ext_links) {
- AbstractController *cntrl = it->params()->ext_node;
+ for (auto &it : params().ext_links) {
+ AbstractController *cntrl = it->params().ext_node;
localNodeVersions[cntrl->getType()].push_back(cntrl->getVersion());
- params()->ruby_system->registerMachineID(cntrl->getMachineID(), this);
+ params().ruby_system->registerMachineID(cntrl->getMachineID(), this);
}
// Compute a local ID for each MachineType using the same order as SLICC
assert(m_nodes != 0);
assert(m_virtual_networks != 0);
- m_topology_ptr = new Topology(m_nodes, p->routers.size(),
+ m_topology_ptr = new Topology(m_nodes, p.routers.size(),
m_virtual_networks,
- p->ext_links, p->int_links);
+ p.ext_links, p.int_links);
// Allocate to and from queues
// Queues that are getting messages from protocol
}
// Initialize the controller's network pointers
- for (std::vector<BasicExtLink*>::const_iterator i = p->ext_links.begin();
- i != p->ext_links.end(); ++i) {
+ for (std::vector<BasicExtLink*>::const_iterator i = p.ext_links.begin();
+ i != p.ext_links.end(); ++i) {
BasicExtLink *ext_link = (*i);
- AbstractController *abs_cntrl = ext_link->params()->ext_node;
+ AbstractController *abs_cntrl = ext_link->params().ext_node;
abs_cntrl->initNetworkPtr(this);
const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
if (!ranges.empty()) {
// Register a callback function for combining the statistics
Stats::registerDumpCallback([this]() { collateStats(); });
- for (auto &it : dynamic_cast<Network *>(this)->params()->ext_links) {
- it->params()->ext_node->initNetQueues();
+ for (auto &it : dynamic_cast<Network *>(this)->params().ext_links) {
+ it->params().ext_node->initNetQueues();
}
}
{
public:
typedef RubyNetworkParams Params;
- Network(const Params *p);
- const Params * params() const
- { return dynamic_cast<const Params *>(_params); }
+ Network(const Params &p);
+ const Params &
+ params() const
+ {
+ return dynamic_cast<const Params &>(_params);
+ }
virtual ~Network();
for (vector<BasicExtLink*>::const_iterator i = ext_links.begin();
i != ext_links.end(); ++i) {
BasicExtLink *ext_link = (*i);
- AbstractController *abs_cntrl = ext_link->params()->ext_node;
- BasicRouter *router = ext_link->params()->int_node;
+ AbstractController *abs_cntrl = ext_link->params().ext_node;
+ BasicRouter *router = ext_link->params().int_node;
int machine_base_idx = MachineType_base_number(abs_cntrl->getType());
int ext_idx1 = machine_base_idx + abs_cntrl->getVersion();
int ext_idx2 = ext_idx1 + m_nodes;
- int int_idx = router->params()->router_id + 2*m_nodes;
+ int int_idx = router->params().router_id + 2*m_nodes;
// create the internal uni-directional links in both directions
// ext to int
for (vector<BasicIntLink*>::const_iterator i = int_links.begin();
i != int_links.end(); ++i) {
BasicIntLink *int_link = (*i);
- BasicRouter *router_src = int_link->params()->src_node;
- BasicRouter *router_dst = int_link->params()->dst_node;
+ BasicRouter *router_src = int_link->params().src_node;
+ BasicRouter *router_dst = int_link->params().dst_node;
- PortDirection src_outport = int_link->params()->src_outport;
- PortDirection dst_inport = int_link->params()->dst_inport;
+ PortDirection src_outport = int_link->params().src_outport;
+ PortDirection dst_inport = int_link->params().dst_inport;
// Store the IntLink pointers for later
m_int_link_vector.push_back(int_link);
- int src = router_src->params()->router_id + 2*m_nodes;
- int dst = router_dst->params()->router_id + 2*m_nodes;
+ int src = router_src->params().router_id + 2*m_nodes;
+ int dst = router_dst->params().router_id + 2*m_nodes;
// create the internal uni-directional link from src to dst
addLink(src, dst, int_link, src_outport, dst_inport);
#define MAX(a,b) ((a > b) ? (a) : (b))
-FaultModel::FaultModel(const Params *p) : SimObject(p)
+FaultModel::FaultModel(const Params &p) : SimObject(p)
{
// read configurations into "configurations" vector
// format: <buff/vc> <vcs> <10 fault types>
for (int i = 0; more_records; i += (fields_per_conf_record)){
system_conf configuration;
configuration.buff_per_vc =
- p->baseline_fault_vector_database[i + conf_record_buff_per_vc];
+ p.baseline_fault_vector_database[i + conf_record_buff_per_vc];
configuration.vcs =
- p->baseline_fault_vector_database[i + conf_record_vcs];
+ p.baseline_fault_vector_database[i + conf_record_vcs];
for (int fault_index = 0; fault_index < number_of_fault_types;
fault_index++){
configuration.fault_type[fault_index] =
- p->baseline_fault_vector_database[i +
+ p.baseline_fault_vector_database[i +
conf_record_first_fault_type + fault_index] / 100;
}
configurations.push_back(configuration);
- if (p->baseline_fault_vector_database[i+fields_per_conf_record] < 0){
+ if (p.baseline_fault_vector_database[i+fields_per_conf_record] < 0){
more_records = false;
}
}
more_records = true;
for (int i = 0; more_records; i += (fields_per_temperature_record)){
int record_temperature =
- p->temperature_weights_database[i + temperature_record_temp];
+ p.temperature_weights_database[i + temperature_record_temp];
int record_weight =
- p->temperature_weights_database[i + temperature_record_weight];
+ p.temperature_weights_database[i + temperature_record_weight];
static int first_record = true;
if (first_record){
for (int temperature = 0; temperature < record_temperature;
}
assert(record_temperature == temperature_weights.size());
temperature_weights.push_back(record_weight);
- if (p->temperature_weights_database[i +
+ if (p.temperature_weights_database[i +
fields_per_temperature_record] < 0){
more_records = false;
}
}
FaultModel *
-FaultModelParams::create()
+FaultModelParams::create() const
{
- return new FaultModel(this);
+ return new FaultModel(*this);
}
{
public:
typedef FaultModelParams Params;
- FaultModel(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ FaultModel(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
/************************************************************************/
/********** THE FAULT TYPES SUPPORTED BY THE FAULT MODEL ***************/
{
public:
typedef CreditLinkParams Params;
- CreditLink(const Params *p) : NetworkLink(p) {}
+ CreditLink(const Params &p) : NetworkLink(p) {}
};
#endif // __MEM_RUBY_NETWORK_GARNET_0_CREDITLINK_HH__
#include "mem/ruby/network/garnet/NetworkBridge.hh"
#include "mem/ruby/network/garnet/NetworkLink.hh"
-GarnetIntLink::GarnetIntLink(const Params *p)
+GarnetIntLink::GarnetIntLink(const Params &p)
: BasicIntLink(p)
{
// Uni-directional
- m_network_link = p->network_link;
- m_credit_link = p->credit_link;
+ m_network_link = p.network_link;
+ m_credit_link = p.credit_link;
- srcCdcEn = p->src_cdc;
- dstCdcEn = p->dst_cdc;
+ srcCdcEn = p.src_cdc;
+ dstCdcEn = p.dst_cdc;
- srcSerdesEn = p->src_serdes;
- dstSerdesEn = p->dst_serdes;
+ srcSerdesEn = p.src_serdes;
+ dstSerdesEn = p.dst_serdes;
srcBridgeEn = false;
dstBridgeEn = false;
if (srcCdcEn || srcSerdesEn) {
srcBridgeEn = true;
- srcNetBridge = p->src_net_bridge;
- srcCredBridge = p->src_cred_bridge;
+ srcNetBridge = p.src_net_bridge;
+ srcCredBridge = p.src_cred_bridge;
}
if (dstCdcEn || dstSerdesEn) {
dstBridgeEn = true;
- dstNetBridge = p->dst_net_bridge;
- dstCredBridge = p->dst_cred_bridge;
+ dstNetBridge = p.dst_net_bridge;
+ dstCredBridge = p.dst_cred_bridge;
}
-
}
void
}
GarnetIntLink *
-GarnetIntLinkParams::create()
+GarnetIntLinkParams::create() const
{
- return new GarnetIntLink(this);
+ return new GarnetIntLink(*this);
}
-GarnetExtLink::GarnetExtLink(const Params *p)
+GarnetExtLink::GarnetExtLink(const Params &p)
: BasicExtLink(p)
{
// Bi-directional
// In
- m_network_links[0] = p->network_links[0];
- m_credit_links[0] = p->credit_links[0];
+ m_network_links[0] = p.network_links[0];
+ m_credit_links[0] = p.credit_links[0];
// Out
- m_network_links[1] = p->network_links[1];
- m_credit_links[1] = p->credit_links[1];
+ m_network_links[1] = p.network_links[1];
+ m_credit_links[1] = p.credit_links[1];
- extCdcEn = p->ext_cdc;
- intCdcEn = p->int_cdc;
+ extCdcEn = p.ext_cdc;
+ intCdcEn = p.int_cdc;
- extSerdesEn = p->ext_serdes;
- intSerdesEn = p->int_serdes;
+ extSerdesEn = p.ext_serdes;
+ intSerdesEn = p.int_serdes;
extBridgeEn = false;
intBridgeEn = false;
if (extCdcEn || extSerdesEn) {
extBridgeEn = true;
- extNetBridge[0] = p->ext_net_bridge[0];
- extCredBridge[0] = p->ext_cred_bridge[0];
- extNetBridge[1] = p->ext_net_bridge[1];
- extCredBridge[1] = p->ext_cred_bridge[1];
+ extNetBridge[0] = p.ext_net_bridge[0];
+ extCredBridge[0] = p.ext_cred_bridge[0];
+ extNetBridge[1] = p.ext_net_bridge[1];
+ extCredBridge[1] = p.ext_cred_bridge[1];
}
if (intCdcEn || intSerdesEn) {
intBridgeEn = true;
- intNetBridge[0] = p->int_net_bridge[0];
- intNetBridge[1] = p->int_net_bridge[1];
- intCredBridge[0] = p->int_cred_bridge[0];
- intCredBridge[1] = p->int_cred_bridge[1];
+ intNetBridge[0] = p.int_net_bridge[0];
+ intNetBridge[1] = p.int_net_bridge[1];
+ intCredBridge[0] = p.int_cred_bridge[0];
+ intCredBridge[1] = p.int_cred_bridge[1];
}
-
}
void
}
GarnetExtLink *
-GarnetExtLinkParams::create()
+GarnetExtLinkParams::create() const
{
- return new GarnetExtLink(this);
+ return new GarnetExtLink(*this);
}
{
public:
typedef GarnetIntLinkParams Params;
- GarnetIntLink(const Params *p);
+ GarnetIntLink(const Params &p);
void init();
{
public:
typedef GarnetExtLinkParams Params;
- GarnetExtLink(const Params *p);
+ GarnetExtLink(const Params &p);
void init();
* (see configs/network/Network.py)
*/
-GarnetNetwork::GarnetNetwork(const Params *p)
+GarnetNetwork::GarnetNetwork(const Params &p)
: Network(p)
{
- m_num_rows = p->num_rows;
- m_ni_flit_size = p->ni_flit_size;
+ m_num_rows = p.num_rows;
+ m_ni_flit_size = p.ni_flit_size;
m_max_vcs_per_vnet = 0;
- m_buffers_per_data_vc = p->buffers_per_data_vc;
- m_buffers_per_ctrl_vc = p->buffers_per_ctrl_vc;
- m_routing_algorithm = p->routing_algorithm;
+ m_buffers_per_data_vc = p.buffers_per_data_vc;
+ m_buffers_per_ctrl_vc = p.buffers_per_ctrl_vc;
+ m_routing_algorithm = p.routing_algorithm;
- m_enable_fault_model = p->enable_fault_model;
+ m_enable_fault_model = p.enable_fault_model;
if (m_enable_fault_model)
- fault_model = p->fault_model;
+ fault_model = p.fault_model;
m_vnet_type.resize(m_virtual_networks);
}
// record the routers
- for (vector<BasicRouter*>::const_iterator i = p->routers.begin();
- i != p->routers.end(); ++i) {
+ for (vector<BasicRouter*>::const_iterator i = p.routers.begin();
+ i != p.routers.end(); ++i) {
Router* router = safe_cast<Router*>(*i);
m_routers.push_back(router);
}
// record the network interfaces
- for (vector<ClockedObject*>::const_iterator i = p->netifs.begin();
- i != p->netifs.end(); ++i) {
+ for (vector<ClockedObject*>::const_iterator i = p.netifs.begin();
+ i != p.netifs.end(); ++i) {
NetworkInterface *ni = safe_cast<NetworkInterface *>(*i);
m_nis.push_back(ni);
ni->init_net_ptr(this);
void
GarnetNetwork::collateStats()
{
- RubySystem *rs = params()->ruby_system;
+ RubySystem *rs = params().ruby_system;
double time_delta = double(curCycle() - rs->getStartCycle());
for (int i = 0; i < m_networklinks.size(); i++) {
}
GarnetNetwork *
-GarnetNetworkParams::create()
+GarnetNetworkParams::create() const
{
- return new GarnetNetwork(this);
+ return new GarnetNetwork(*this);
}
uint32_t
{
public:
typedef GarnetNetworkParams Params;
- GarnetNetwork(const Params *p);
+ GarnetNetwork(const Params &p);
~GarnetNetwork() = default;
void init();
#include "debug/RubyNetwork.hh"
#include "params/GarnetIntLink.hh"
-NetworkBridge::NetworkBridge(const Params *p)
+NetworkBridge::NetworkBridge(const Params &p)
:CreditLink(p)
{
enCdc = true;
enSerDes = true;
- mType = p->vtype;
+ mType = p.vtype;
- cdcLatency = p->cdc_latency;
- serDesLatency = p->serdes_latency;
+ cdcLatency = p.cdc_latency;
+ serDesLatency = p.serdes_latency;
lastScheduledAt = 0;
- nLink = p->link;
+ nLink = p.link;
if (mType == Enums::LINK_OBJECT) {
nLink->setLinkConsumer(this);
setSourceQueue(nLink->getBuffer(), nLink);
}
NetworkBridge *
-NetworkBridgeParams::create()
+NetworkBridgeParams::create() const
{
- return new NetworkBridge(this);
+ return new NetworkBridge(*this);
}
{
public:
typedef NetworkBridgeParams Params;
- NetworkBridge(const Params *p);
+ NetworkBridge(const Params &p);
~NetworkBridge();
void initBridge(NetworkBridge *coBrid, bool cdc_en, bool serdes_en);
using namespace std;
-NetworkInterface::NetworkInterface(const Params *p)
- : ClockedObject(p), Consumer(this), m_id(p->id),
- m_virtual_networks(p->virt_nets), m_vc_per_vnet(0),
+NetworkInterface::NetworkInterface(const Params &p)
+ : ClockedObject(p), Consumer(this), m_id(p.id),
+ m_virtual_networks(p.virt_nets), m_vc_per_vnet(0),
m_vc_allocator(m_virtual_networks, 0),
- m_deadlock_threshold(p->garnet_deadlock_threshold),
+ m_deadlock_threshold(p.garnet_deadlock_threshold),
vc_busy_counter(m_virtual_networks, 0)
{
m_stall_count.resize(m_virtual_networks);
}
NetworkInterface *
-GarnetNetworkInterfaceParams::create()
+GarnetNetworkInterfaceParams::create() const
{
- return new NetworkInterface(this);
+ return new NetworkInterface(*this);
}
{
public:
typedef GarnetNetworkInterfaceParams Params;
- NetworkInterface(const Params *p);
+ NetworkInterface(const Params &p);
~NetworkInterface() = default;
void addInPort(NetworkLink *in_link, CreditLink *credit_link);
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet/CreditLink.hh"
-NetworkLink::NetworkLink(const Params *p)
- : ClockedObject(p), Consumer(this), m_id(p->link_id),
+NetworkLink::NetworkLink(const Params &p)
+ : ClockedObject(p), Consumer(this), m_id(p.link_id),
m_type(NUM_LINK_TYPES_),
- m_latency(p->link_latency), m_link_utilized(0),
- m_virt_nets(p->virt_nets), linkBuffer(),
+ m_latency(p.link_latency), m_link_utilized(0),
+ m_virt_nets(p.virt_nets), linkBuffer(),
link_consumer(nullptr), link_srcQueue(nullptr)
{
- int num_vnets = (p->supported_vnets).size();
+ int num_vnets = (p.supported_vnets).size();
mVnets.resize(num_vnets);
- bitWidth = p->width;
+ bitWidth = p.width;
for (int i = 0; i < num_vnets; i++) {
- mVnets[i] = p->supported_vnets[i];
+ mVnets[i] = p.supported_vnets[i];
}
}
}
NetworkLink *
-NetworkLinkParams::create()
+NetworkLinkParams::create() const
{
- return new NetworkLink(this);
+ return new NetworkLink(*this);
}
CreditLink *
-CreditLinkParams::create()
+CreditLinkParams::create() const
{
- return new CreditLink(this);
+ return new CreditLink(*this);
}
uint32_t
{
public:
typedef NetworkLinkParams Params;
- NetworkLink(const Params *p);
+ NetworkLink(const Params &p);
~NetworkLink() = default;
void setLinkConsumer(Consumer *consumer);
using namespace std;
-Router::Router(const Params *p)
- : BasicRouter(p), Consumer(this), m_latency(p->latency),
- m_virtual_networks(p->virt_nets), m_vc_per_vnet(p->vcs_per_vnet),
- m_num_vcs(m_virtual_networks * m_vc_per_vnet), m_bit_width(p->width),
+Router::Router(const Params &p)
+ : BasicRouter(p), Consumer(this), m_latency(p.latency),
+ m_virtual_networks(p.virt_nets), m_vc_per_vnet(p.vcs_per_vnet),
+ m_num_vcs(m_virtual_networks * m_vc_per_vnet), m_bit_width(p.width),
m_network_ptr(nullptr), routingUnit(this), switchAllocator(this),
crossbarSwitch(this)
{
}
Router *
-GarnetRouterParams::create()
+GarnetRouterParams::create() const
{
- return new Router(this);
+ return new Router(*this);
}
{
public:
typedef GarnetRouterParams Params;
- Router(const Params *p);
+ Router(const Params &p);
~Router() = default;
#include "mem/ruby/network/simple/SimpleLink.hh"
-SimpleExtLink::SimpleExtLink(const Params *p)
+SimpleExtLink::SimpleExtLink(const Params &p)
: BasicExtLink(p)
{
// For the simple links, the bandwidth factor translates to the
// bandwidth multiplier. The multipiler, in combination with the
// endpoint bandwidth multiplier - message size multiplier ratio,
// determines the link bandwidth in bytes
- m_bw_multiplier = p->bandwidth_factor;
+ m_bw_multiplier = p.bandwidth_factor;
}
void
}
SimpleExtLink *
-SimpleExtLinkParams::create()
+SimpleExtLinkParams::create() const
{
- return new SimpleExtLink(this);
+ return new SimpleExtLink(*this);
}
-SimpleIntLink::SimpleIntLink(const Params *p)
+SimpleIntLink::SimpleIntLink(const Params &p)
: BasicIntLink(p)
{
// For the simple links, the bandwidth factor translates to the
// bandwidth multiplier. The multipiler, in combination with the
// endpoint bandwidth multiplier - message size multiplier ratio,
// determines the link bandwidth in bytes
- m_bw_multiplier = p->bandwidth_factor;
+ m_bw_multiplier = p.bandwidth_factor;
}
void
}
SimpleIntLink *
-SimpleIntLinkParams::create()
+SimpleIntLinkParams::create() const
{
- return new SimpleIntLink(this);
+ return new SimpleIntLink(*this);
}
{
public:
typedef SimpleExtLinkParams Params;
- SimpleExtLink(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ SimpleExtLink(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
friend class Topology;
void print(std::ostream& out) const;
{
public:
typedef SimpleIntLinkParams Params;
- SimpleIntLink(const Params *p);
- const Params *params() const { return (const Params *)_params; }
+ SimpleIntLink(const Params &p);
+ const Params ¶ms() const { return (const Params &)_params; }
friend class Topology;
void print(std::ostream& out) const;
using namespace std;
-SimpleNetwork::SimpleNetwork(const Params *p)
- : Network(p), m_buffer_size(p->buffer_size),
- m_endpoint_bandwidth(p->endpoint_bandwidth),
- m_adaptive_routing(p->adaptive_routing)
+SimpleNetwork::SimpleNetwork(const Params &p)
+ : Network(p), m_buffer_size(p.buffer_size),
+ m_endpoint_bandwidth(p.endpoint_bandwidth),
+ m_adaptive_routing(p.adaptive_routing)
{
// record the routers
- for (vector<BasicRouter*>::const_iterator i = p->routers.begin();
- i != p->routers.end(); ++i) {
+ for (vector<BasicRouter*>::const_iterator i = p.routers.begin();
+ i != p.routers.end(); ++i) {
Switch* s = safe_cast<Switch*>(*i);
m_switches.push_back(s);
s->init_net_ptr(this);
}
- m_int_link_buffers = p->int_link_buffers;
+ m_int_link_buffers = p.int_link_buffers;
m_num_connected_buffers = 0;
}
}
SimpleNetwork *
-SimpleNetworkParams::create()
+SimpleNetworkParams::create() const
{
- return new SimpleNetwork(this);
+ return new SimpleNetwork(*this);
}
/*
{
public:
typedef SimpleNetworkParams Params;
- SimpleNetwork(const Params *p);
+ SimpleNetwork(const Params &p);
~SimpleNetwork() = default;
void init();
using namespace std;
using m5::stl_helpers::operator<<;
-Switch::Switch(const Params *p)
- : BasicRouter(p), perfectSwitch(m_id, this, p->virt_nets),
+Switch::Switch(const Params &p)
+ : BasicRouter(p), perfectSwitch(m_id, this, p.virt_nets),
m_num_connected_buffers(0)
{
- m_port_buffers.reserve(p->port_buffers.size());
- for (auto& buffer : p->port_buffers) {
+ m_port_buffers.reserve(p.port_buffers.size());
+ for (auto& buffer : p.port_buffers) {
m_port_buffers.emplace_back(buffer);
}
}
Cycles link_latency, int bw_multiplier)
{
// Create a throttle
- throttles.emplace_back(m_id, m_network_ptr->params()->ruby_system,
+ throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
throttles.size(), link_latency, bw_multiplier,
m_network_ptr->getEndpointBandwidth(), this);
}
Switch *
-SwitchParams::create()
+SwitchParams::create() const
{
- return new Switch(this);
+ return new Switch(*this);
}
{
public:
typedef SwitchParams Params;
- Switch(const Params *p);
+ Switch(const Params &p);
~Switch() = default;
void init();
using namespace std;
using m5::stl_helpers::operator<<;
-Profiler::Profiler(const RubySystemParams *p, RubySystem *rs)
- : m_ruby_system(rs), m_hot_lines(p->hot_lines),
- m_all_instructions(p->all_instructions),
- m_num_vnets(p->number_of_virtual_networks)
+Profiler::Profiler(const RubySystemParams &p, RubySystem *rs)
+ : m_ruby_system(rs), m_hot_lines(p.hot_lines),
+ m_all_instructions(p.all_instructions),
+ m_num_vnets(p.number_of_virtual_networks)
{
- m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
+ m_address_profiler_ptr = new AddressProfiler(p.num_of_sequencers, this);
m_address_profiler_ptr->setHotLines(m_hot_lines);
m_address_profiler_ptr->setAllInstructions(m_all_instructions);
if (m_all_instructions) {
- m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
+ m_inst_profiler_ptr = new AddressProfiler(p.num_of_sequencers, this);
m_inst_profiler_ptr->setHotLines(m_hot_lines);
m_inst_profiler_ptr->setAllInstructions(m_all_instructions);
}
class Profiler
{
public:
- Profiler(const RubySystemParams *params, RubySystem *rs);
+ Profiler(const RubySystemParams ¶ms, RubySystem *rs);
~Profiler();
RubySystem *m_ruby_system;
#include "mem/ruby/system/Sequencer.hh"
#include "sim/system.hh"
-AbstractController::AbstractController(const Params *p)
- : ClockedObject(p), Consumer(this), m_version(p->version),
- m_clusterID(p->cluster_id),
- m_id(p->system->getRequestorId(this)), m_is_blocking(false),
- m_number_of_TBEs(p->number_of_TBEs),
- m_transitions_per_cycle(p->transitions_per_cycle),
- m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
- m_mandatory_queue_latency(p->mandatory_queue_latency),
+AbstractController::AbstractController(const Params &p)
+ : ClockedObject(p), Consumer(this), m_version(p.version),
+ m_clusterID(p.cluster_id),
+ m_id(p.system->getRequestorId(this)), m_is_blocking(false),
+ m_number_of_TBEs(p.number_of_TBEs),
+ m_transitions_per_cycle(p.transitions_per_cycle),
+ m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
+ m_mandatory_queue_latency(p.mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this),
- addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
+ addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
{
if (m_version == 0) {
// Combine the statistics from all controllers
// different types. If this is the case, mapAddressToDownstreamMachine
// needs to specify the machine type
downstreamDestinations.resize();
- for (auto abs_cntrl : params()->downstream_destinations) {
+ for (auto abs_cntrl : params().downstream_destinations) {
MachineID mid = abs_cntrl->getMachineID();
const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
for (const auto addr_range : ranges) {
{
public:
typedef RubyControllerParams Params;
- AbstractController(const Params *p);
+ AbstractController(const Params &p);
void init();
- const Params *params() const { return (const Params *)_params; }
+ const Params ¶ms() const { return (const Params &)_params; }
NodeID getVersion() const { return m_machineID.getNum(); }
MachineType getType() const { return m_machineID.getType(); }
}
CacheMemory *
-RubyCacheParams::create()
+RubyCacheParams::create() const
{
- return new CacheMemory(this);
+ return new CacheMemory(*this);
}
-CacheMemory::CacheMemory(const Params *p)
+CacheMemory::CacheMemory(const Params &p)
: SimObject(p),
- dataArray(p->dataArrayBanks, p->dataAccessLatency,
- p->start_index_bit, p->ruby_system),
- tagArray(p->tagArrayBanks, p->tagAccessLatency,
- p->start_index_bit, p->ruby_system)
-{
- m_cache_size = p->size;
- m_cache_assoc = p->assoc;
- m_replacementPolicy_ptr = p->replacement_policy;
- m_start_index_bit = p->start_index_bit;
- m_is_instruction_only_cache = p->is_icache;
- m_resource_stalls = p->resourceStalls;
- m_block_size = p->block_size; // may be 0 at this point. Updated in init()
+ dataArray(p.dataArrayBanks, p.dataAccessLatency,
+ p.start_index_bit, p.ruby_system),
+ tagArray(p.tagArrayBanks, p.tagAccessLatency,
+ p.start_index_bit, p.ruby_system)
+{
+ m_cache_size = p.size;
+ m_cache_assoc = p.assoc;
+ m_replacementPolicy_ptr = p.replacement_policy;
+ m_start_index_bit = p.start_index_bit;
+ m_is_instruction_only_cache = p.is_icache;
+ m_resource_stalls = p.resourceStalls;
+ m_block_size = p.block_size; // may be 0 at this point. Updated in init()
m_use_occupancy = dynamic_cast<ReplacementPolicy::WeightedLRU*>(
m_replacementPolicy_ptr) ? true : false;
}
public:
typedef RubyCacheParams Params;
typedef std::shared_ptr<ReplacementPolicy::ReplacementData> ReplData;
- CacheMemory(const Params *p);
+ CacheMemory(const Params &p);
~CacheMemory();
void init();
using namespace std;
-DirectoryMemory::DirectoryMemory(const Params *p)
- : SimObject(p), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
+DirectoryMemory::DirectoryMemory(const Params &p)
+ : SimObject(p), addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
{
m_size_bytes = 0;
for (const auto &r: addrRanges) {
}
DirectoryMemory *
-RubyDirectoryMemoryParams::create()
+RubyDirectoryMemoryParams::create() const
{
- return new DirectoryMemory(this);
+ return new DirectoryMemory(*this);
}
{
public:
typedef RubyDirectoryMemoryParams Params;
- DirectoryMemory(const Params *p);
+ DirectoryMemory(const Params &p);
~DirectoryMemory();
void init();
#include "mem/ruby/system/RubySystem.hh"
RubyPrefetcher*
-RubyPrefetcherParams::create()
+RubyPrefetcherParams::create() const
{
- return new RubyPrefetcher(this);
+ return new RubyPrefetcher(*this);
}
-RubyPrefetcher::RubyPrefetcher(const Params *p)
- : SimObject(p), m_num_streams(p->num_streams),
- m_array(p->num_streams), m_train_misses(p->train_misses),
- m_num_startup_pfs(p->num_startup_pfs),
- unitFilter(p->unit_filter),
- negativeFilter(p->unit_filter),
- nonUnitFilter(p->nonunit_filter),
- m_prefetch_cross_pages(p->cross_page),
- m_page_shift(p->sys->getPageShift())
+RubyPrefetcher::RubyPrefetcher(const Params &p)
+ : SimObject(p), m_num_streams(p.num_streams),
+ m_array(p.num_streams), m_train_misses(p.train_misses),
+ m_num_startup_pfs(p.num_startup_pfs),
+ unitFilter(p.unit_filter),
+ negativeFilter(p.unit_filter),
+ nonUnitFilter(p.nonunit_filter),
+ m_prefetch_cross_pages(p.cross_page),
+ m_page_shift(p.sys->getPageShift())
{
assert(m_num_streams > 0);
assert(m_num_startup_pfs <= MAX_PF_INFLIGHT);
{
public:
typedef RubyPrefetcherParams Params;
- RubyPrefetcher(const Params *p);
+ RubyPrefetcher(const Params &p);
~RubyPrefetcher() = default;
void issueNextPrefetch(Addr address, PrefetchEntry *stream);
// ****************************************************************
// CONSTRUCTOR
-WireBuffer::WireBuffer(const Params *p)
+WireBuffer::WireBuffer(const Params &p)
: SimObject(p)
{
m_msg_counter = 0;
}
WireBuffer *
-RubyWireBufferParams::create()
+RubyWireBufferParams::create() const
{
- return new WireBuffer(this);
+ return new WireBuffer(*this);
}
{
public:
typedef RubyWireBufferParams Params;
- WireBuffer(const Params *p);
+ WireBuffer(const Params &p);
void init();
~WireBuffer();
{
}
-DMASequencer::DMASequencer(const Params *p)
+DMASequencer::DMASequencer(const Params &p)
: RubyPort(p), m_outstanding_count(0),
- m_max_outstanding_requests(p->max_outstanding_requests)
+ m_max_outstanding_requests(p.max_outstanding_requests)
{
}
}
DMASequencer *
-DMASequencerParams::create()
+DMASequencerParams::create() const
{
- return new DMASequencer(this);
+ return new DMASequencer(*this);
}
{
public:
typedef DMASequencerParams Params;
- DMASequencer(const Params *);
+ DMASequencer(const Params &);
void init() override;
/* external interface */
}
}
-GPUCoalescer::GPUCoalescer(const Params *p)
+GPUCoalescer::GPUCoalescer(const Params &p)
: RubyPort(p),
issueEvent([this]{ completeIssue(); }, "Issue coalesced request",
false, Event::Progress_Event_Pri),
m_outstanding_count = 0;
- coalescingWindow = p->max_coalesces_per_cycle;
+ coalescingWindow = p.max_coalesces_per_cycle;
m_max_outstanding_requests = 0;
m_instCache_ptr = nullptr;
m_dataCache_ptr = nullptr;
- m_instCache_ptr = p->icache;
- m_dataCache_ptr = p->dcache;
- m_max_outstanding_requests = p->max_outstanding_requests;
- m_deadlock_threshold = p->deadlock_threshold;
+ m_instCache_ptr = p.icache;
+ m_dataCache_ptr = p.dcache;
+ m_max_outstanding_requests = p.max_outstanding_requests;
+ m_deadlock_threshold = p.deadlock_threshold;
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
assert(m_instCache_ptr);
assert(m_dataCache_ptr);
- m_runningGarnetStandalone = p->garnet_standalone;
+ m_runningGarnetStandalone = p.garnet_standalone;
}
GPUCoalescer::~GPUCoalescer()
};
typedef RubyGPUCoalescerParams Params;
- GPUCoalescer(const Params *);
+ GPUCoalescer(const Params &);
~GPUCoalescer();
Port &getPort(const std::string &if_name,
}
HTMSequencer *
-RubyHTMSequencerParams::create()
+RubyHTMSequencerParams::create() const
{
- return new HTMSequencer(this);
+ return new HTMSequencer(*this);
}
-HTMSequencer::HTMSequencer(const RubyHTMSequencerParams *p)
+HTMSequencer::HTMSequencer(const RubyHTMSequencerParams &p)
: Sequencer(p)
{
m_htmstart_tick = 0;
class HTMSequencer : public Sequencer
{
public:
- HTMSequencer(const RubyHTMSequencerParams *p);
+ HTMSequencer(const RubyHTMSequencerParams &p);
~HTMSequencer();
// callback to acknowledge HTM requests and
#include "sim/full_system.hh"
#include "sim/system.hh"
-RubyPort::RubyPort(const Params *p)
- : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
+RubyPort::RubyPort(const Params &p)
+ : ClockedObject(p), m_ruby_system(p.ruby_system), m_version(p.version),
m_controller(NULL), m_mandatory_q_ptr(NULL),
- m_usingRubyTester(p->using_ruby_tester), system(p->system),
+ m_usingRubyTester(p.using_ruby_tester), system(p.system),
pioRequestPort(csprintf("%s.pio-request-port", name()), this),
pioResponsePort(csprintf("%s.pio-response-port", name()), this),
memRequestPort(csprintf("%s.mem-request-port", name()), this),
memResponsePort(csprintf("%s-mem-response-port", name()), this,
- p->ruby_system->getAccessBackingStore(), -1,
- p->no_retry_on_stall),
- gotAddrRanges(p->port_interrupt_out_port_connection_count),
- m_isCPUSequencer(p->is_cpu_sequencer)
+ p.ruby_system->getAccessBackingStore(), -1,
+ p.no_retry_on_stall),
+ gotAddrRanges(p.port_interrupt_out_port_connection_count),
+ m_isCPUSequencer(p.is_cpu_sequencer)
{
assert(m_version != -1);
// create the response ports based on the number of connected ports
- for (size_t i = 0; i < p->port_in_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_in_ports_connection_count; ++i) {
response_ports.push_back(new MemResponsePort(csprintf
("%s.response_ports%d", name(), i), this,
- p->ruby_system->getAccessBackingStore(),
- i, p->no_retry_on_stall));
+ p.ruby_system->getAccessBackingStore(),
+ i, p.no_retry_on_stall));
}
// create the request ports based on the number of connected ports
- for (size_t i = 0; i < p->port_interrupt_out_port_connection_count; ++i) {
+ for (size_t i = 0; i < p.port_interrupt_out_port_connection_count; ++i) {
request_ports.push_back(new PioRequestPort(csprintf(
"%s.request_ports%d", name(), i), this));
}
};
typedef RubyPortParams Params;
- RubyPort(const Params *p);
+ RubyPort(const Params &p);
virtual ~RubyPort() {}
void init() override;
#include "mem/ruby/system/RubyPortProxy.hh"
-RubyPortProxy::RubyPortProxy(const RubyPortProxyParams* p) :
- RubyPort(p) {
+RubyPortProxy::RubyPortProxy(const RubyPortProxyParams &p) :
+ RubyPort(p)
+{
}
RubyPortProxy::~RubyPortProxy()
}
RubyPortProxy*
-RubyPortProxyParams::create()
+RubyPortProxyParams::create() const
{
- return new RubyPortProxy(this);
+ return new RubyPortProxy(*this);
}
*
* @param p Parameters inherited from the RubyPort
*/
- RubyPortProxy(const RubyPortProxyParams* p);
+ RubyPortProxy(const RubyPortProxyParams &p);
/**
* Destruct a RubyPortProxy.
unsigned RubySystem::m_systems_to_warmup = 0;
bool RubySystem::m_cooldown_enabled = false;
-RubySystem::RubySystem(const Params *p)
- : ClockedObject(p), m_access_backing_store(p->access_backing_store),
+RubySystem::RubySystem(const Params &p)
+ : ClockedObject(p), m_access_backing_store(p.access_backing_store),
m_cache_recorder(NULL)
{
- m_randomization = p->randomization;
+ m_randomization = p.randomization;
- m_block_size_bytes = p->block_size_bytes;
+ m_block_size_bytes = p.block_size_bytes;
assert(isPowerOf2(m_block_size_bytes));
m_block_size_bits = floorLog2(m_block_size_bytes);
- m_memory_size_bits = p->memory_size_bits;
+ m_memory_size_bits = p.memory_size_bits;
// Resize to the size of different machine types
m_abstract_controls.resize(MachineType_NUM);
Stats::registerDumpCallback([this]() { collateStats(); });
// Create the profiler
m_profiler = new Profiler(p, this);
- m_phys_mem = p->phys_mem;
+ m_phys_mem = p.phys_mem;
}
void
}
// Default all other requestor IDs to network 0
- for (auto id = 0; id < params()->system->maxRequestors(); ++id) {
+ for (auto id = 0; id < params().system->maxRequestors(); ++id) {
if (!requestorToNetwork.count(id)) {
requestorToNetwork.insert(std::make_pair(id, 0));
}
}
RubySystem *
-RubySystemParams::create()
+RubySystemParams::create() const
{
- return new RubySystem(this);
+ return new RubySystem(*this);
}
{
public:
typedef RubySystemParams Params;
- RubySystem(const Params *p);
+ RubySystem(const Params &p);
~RubySystem();
- const Params *params() const { return (const Params *)_params; }
+ const Params ¶ms() const { return (const Params &)_params; }
// config accessors
static int getRandomization() { return m_randomization; }
using namespace std;
Sequencer *
-RubySequencerParams::create()
+RubySequencerParams::create() const
{
- return new Sequencer(this);
+ return new Sequencer(*this);
}
-Sequencer::Sequencer(const Params *p)
+Sequencer::Sequencer(const Params &p)
: RubyPort(p), m_IncompleteTimes(MachineType_NUM),
deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check")
{
m_outstanding_count = 0;
- m_dataCache_ptr = p->dcache;
- m_max_outstanding_requests = p->max_outstanding_requests;
- m_deadlock_threshold = p->deadlock_threshold;
+ m_dataCache_ptr = p.dcache;
+ m_max_outstanding_requests = p.max_outstanding_requests;
+ m_deadlock_threshold = p.deadlock_threshold;
- m_coreId = p->coreid; // for tracking the two CorePair sequencers
+ m_coreId = p.coreid; // for tracking the two CorePair sequencers
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
- m_runningGarnetStandalone = p->garnet_standalone;
+ m_runningGarnetStandalone = p.garnet_standalone;
}
Sequencer::~Sequencer()
{
public:
typedef RubySequencerParams Params;
- Sequencer(const Params *);
+ Sequencer(const Params &);
~Sequencer();
/**
using namespace std;
VIPERCoalescer *
-VIPERCoalescerParams::create()
+VIPERCoalescerParams::create() const
{
- return new VIPERCoalescer(this);
+ return new VIPERCoalescer(*this);
}
-VIPERCoalescer::VIPERCoalescer(const Params *p)
+VIPERCoalescer::VIPERCoalescer(const Params &p)
: GPUCoalescer(p),
m_cache_inv_pkt(nullptr),
m_num_pending_invs(0)
{
public:
typedef VIPERCoalescerParams Params;
- VIPERCoalescer(const Params *);
+ VIPERCoalescer(const Params &);
~VIPERCoalescer();
void writeCompleteCallback(Addr address, uint64_t instSeqNum);
void invTCPCallback(Addr address);
{
}
-SerialLink::SerialLink(SerialLinkParams *p)
+SerialLink::SerialLink(const SerialLinkParams &p)
: ClockedObject(p),
- cpu_side_port(p->name + ".cpu_side_port", *this, mem_side_port,
- ticksToCycles(p->delay), p->resp_size, p->ranges),
- mem_side_port(p->name + ".mem_side_port", *this, cpu_side_port,
- ticksToCycles(p->delay), p->req_size),
- num_lanes(p->num_lanes),
- link_speed(p->link_speed)
-
+ cpu_side_port(p.name + ".cpu_side_port", *this, mem_side_port,
+ ticksToCycles(p.delay), p.resp_size, p.ranges),
+ mem_side_port(p.name + ".mem_side_port", *this, cpu_side_port,
+ ticksToCycles(p.delay), p.req_size),
+ num_lanes(p.num_lanes),
+ link_speed(p.link_speed)
{
}
}
SerialLink *
-SerialLinkParams::create()
+SerialLinkParams::create() const
{
- return new SerialLink(this);
+ return new SerialLink(*this);
}
typedef SerialLinkParams Params;
- SerialLink(SerialLinkParams *p);
+ SerialLink(const SerialLinkParams &p);
};
#endif //__MEM_SERIAL_LINK_HH__
#include "base/trace.hh"
#include "debug/Drain.hh"
-SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
+SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
AbstractMemory(p),
- port(name() + ".port", *this), latency(p->latency),
- latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
+ port(name() + ".port", *this), latency(p.latency),
+ latency_var(p.latency_var), bandwidth(p.bandwidth), isBusy(false),
retryReq(false), retryResp(false),
releaseEvent([this]{ release(); }, name()),
dequeueEvent([this]{ dequeue(); }, name())
}
SimpleMemory*
-SimpleMemoryParams::create()
+SimpleMemoryParams::create() const
{
- return new SimpleMemory(this);
+ return new SimpleMemory(*this);
}
public:
- SimpleMemory(const SimpleMemoryParams *p);
+ SimpleMemory(const SimpleMemoryParams &p);
DrainState drain() override;
{
public:
typedef ${c_ident}Params Params;
- $c_ident(const Params *p);
+ $c_ident(const Params &p);
static int getNumControllers();
void init();
code('''
$c_ident *
-${c_ident}Params::create()
+${c_ident}Params::create() const
{
- return new $c_ident(this);
+ return new $c_ident(*this);
}
int $c_ident::m_num_controllers = 0;
#endif
/** \\brief constructor */
-$c_ident::$c_ident(const Params *p)
+$c_ident::$c_ident(const Params &p)
: AbstractController(p)
{
m_machineID.type = MachineType_${ident};
m_machineID.num = m_version;
m_num_controllers++;
- p->ruby_system->registerAbstractController(this);
+ p.ruby_system->registerAbstractController(this);
m_in_ports = $num_in_ports;
''')
#
for param in self.config_parameters:
if param.pointer:
- code('m_${{param.ident}}_ptr = p->${{param.ident}};')
+ code('m_${{param.ident}}_ptr = p.${{param.ident}};')
else:
- code('m_${{param.ident}} = p->${{param.ident}};')
+ code('m_${{param.ident}} = p.${{param.ident}};')
if re.compile("sequencer").search(param.ident) or \
param.type_ast.type.c_ident == "GPUCoalescer" or \
event < ${ident}_Event_NUM; ++event) {
Stats::Vector *t = new Stats::Vector();
t->init(m_num_controllers);
- t->name(params()->ruby_system->name() + ".${c_ident}." +
+ t->name(params().ruby_system->name() + ".${c_ident}." +
${ident}_Event_to_string(event));
t->flags(Stats::pdf | Stats::total | Stats::oneline |
Stats::nozero);
Stats::Vector *t = new Stats::Vector();
t->init(m_num_controllers);
- t->name(params()->ruby_system->name() + ".${c_ident}." +
+ t->name(params().ruby_system->name() + ".${c_ident}." +
${ident}_State_to_string(state) +
"." + ${ident}_Event_to_string(event));
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
for (unsigned int i = 0; i < m_num_controllers; ++i) {
- RubySystem *rs = params()->ruby_system;
+ RubySystem *rs = params().ruby_system;
std::map<uint32_t, AbstractController *>::iterator it =
rs->m_abstract_controls[MachineType_${ident}].find(i);
assert(it != rs->m_abstract_controls[MachineType_${ident}].end());
event < ${ident}_Event_NUM; ++event) {
for (unsigned int i = 0; i < m_num_controllers; ++i) {
- RubySystem *rs = params()->ruby_system;
+ RubySystem *rs = params().ruby_system;
std::map<uint32_t, AbstractController *>::iterator it =
rs->m_abstract_controls[MachineType_${ident}].find(i);
assert(it != rs->m_abstract_controls[MachineType_${ident}].end());
}
SnoopFilter *
-SnoopFilterParams::create()
+SnoopFilterParams::create() const
{
- return new SnoopFilter(this);
+ return new SnoopFilter(*this);
}
typedef std::vector<QueuedResponsePort*> SnoopList;
- SnoopFilter (const SnoopFilterParams *p) :
+ SnoopFilter (const SnoopFilterParams &p) :
SimObject(p), reqLookupResult(cachedLocations.end()),
- linesize(p->system->cacheLineSize()), lookupLatency(p->lookup_latency),
- maxEntryCount(p->max_capacity / p->system->cacheLineSize())
+ linesize(p.system->cacheLineSize()), lookupLatency(p.lookup_latency),
+ maxEntryCount(p.max_capacity / p.system->cacheLineSize())
{
}
#include "debug/Drain.hh"
#include "debug/XBar.hh"
-BaseXBar::BaseXBar(const BaseXBarParams *p)
+BaseXBar::BaseXBar(const BaseXBarParams &p)
: ClockedObject(p),
- frontendLatency(p->frontend_latency),
- forwardLatency(p->forward_latency),
- responseLatency(p->response_latency),
- headerLatency(p->header_latency),
- width(p->width),
- gotAddrRanges(p->port_default_connection_count +
- p->port_mem_side_ports_connection_count, false),
+ frontendLatency(p.frontend_latency),
+ forwardLatency(p.forward_latency),
+ responseLatency(p.response_latency),
+ headerLatency(p.header_latency),
+ width(p.width),
+ gotAddrRanges(p.port_default_connection_count +
+ p.port_mem_side_ports_connection_count, false),
gotAllAddrRanges(false), defaultPortID(InvalidPortID),
- useDefaultRange(p->use_default_range),
+ useDefaultRange(p.use_default_range),
transDist(this, "trans_dist", "Transaction distribution"),
pktCount(this, "pkt_count",
addresses not handled by another port to default device. */
const bool useDefaultRange;
- BaseXBar(const BaseXBarParams *p);
+ BaseXBar(const BaseXBarParams &p);
/**
* Stats for transaction distribution and data passing through the
code("{")
if not hasattr(cls, 'abstract') or not cls.abstract:
if 'type' in cls.__dict__:
- code(" ${{cls.cxx_type}} create();")
+ code(" ${{cls.cxx_type}} create() const;")
code.indent()
if cls == SimObject:
clock.scalar(cd._clockPeriod);
}
-ClockDomain::ClockDomain(const Params *p, VoltageDomain *voltage_domain)
+ClockDomain::ClockDomain(const Params &p, VoltageDomain *voltage_domain)
: SimObject(p),
_clockPeriod(0),
_voltageDomain(voltage_domain),
return _voltageDomain->voltage();
}
-SrcClockDomain::SrcClockDomain(const Params *p) :
- ClockDomain(p, p->voltage_domain),
- freqOpPoints(p->clock),
- _domainID(p->domain_id),
- _perfLevel(p->init_perf_level)
+SrcClockDomain::SrcClockDomain(const Params &p) :
+ ClockDomain(p, p.voltage_domain),
+ freqOpPoints(p.clock),
+ _domainID(p.domain_id),
+ _perfLevel(p.init_perf_level)
{
- VoltageDomain *vdom = p->voltage_domain;
+ VoltageDomain *vdom = p.voltage_domain;
fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
"domain %d %s\n", _domainID, name());
}
SrcClockDomain *
-SrcClockDomainParams::create()
+SrcClockDomainParams::create() const
{
- return new SrcClockDomain(this);
+ return new SrcClockDomain(*this);
}
-DerivedClockDomain::DerivedClockDomain(const Params *p) :
- ClockDomain(p, p->clk_domain->voltageDomain()),
- parent(*p->clk_domain),
- clockDivider(p->clk_divider)
+DerivedClockDomain::DerivedClockDomain(const Params &p) :
+ ClockDomain(p, p.clk_domain->voltageDomain()),
+ parent(*p.clk_domain),
+ clockDivider(p.clk_divider)
{
// Ensure that clock divider setting works as frequency divider and never
// work as frequency multiplier
}
DerivedClockDomain *
-DerivedClockDomainParams::create()
+DerivedClockDomainParams::create() const
{
- return new DerivedClockDomain(this);
+ return new DerivedClockDomain(*this);
}
public:
typedef ClockDomainParams Params;
- ClockDomain(const Params *p, VoltageDomain *voltage_domain);
+ ClockDomain(const Params &p, VoltageDomain *voltage_domain);
/**
* Get the clock period.
public:
typedef SrcClockDomainParams Params;
- SrcClockDomain(const Params *p);
+ SrcClockDomain(const Params &p);
/**
* Set new clock value
public:
typedef DerivedClockDomainParams Params;
- DerivedClockDomain(const Params *p);
+ DerivedClockDomain(const Params &p);
/**
* Called by the parent clock domain to propagate changes. This
#include "base/logging.hh"
#include "sim/power/power_model.hh"
-ClockedObject::ClockedObject(const ClockedObjectParams *p) :
- SimObject(p), Clocked(*p->clk_domain), powerState(p->power_state)
+ClockedObject::ClockedObject(const ClockedObjectParams &p) :
+ SimObject(p), Clocked(*p.clk_domain), powerState(p.power_state)
{
// Register the power_model with the object
// Slightly counter-intuitively, power models need to to register with the
// clocked object and not the power stated object because the power model
// needs information from the clock domain, which is an attribute of the
// clocked object.
- for (auto & power_model: p->power_model)
+ for (auto & power_model: p.power_model)
power_model->setClockedObject(this);
}
class ClockedObject : public SimObject, public Clocked
{
public:
- ClockedObject(const ClockedObjectParams *p);
+ ClockedObject(const ClockedObjectParams &p);
/** Parameters of ClockedObject */
typedef ClockedObjectParams Params;
- const Params *
+ const Params &
params() const
{
- return reinterpret_cast<const Params*>(_params);
+ return reinterpret_cast<const Params&>(_params);
}
void serialize(CheckpointOut &cp) const override;
// DVFSHandler methods implementation
//
-DVFSHandler::DVFSHandler(const Params *p)
+DVFSHandler::DVFSHandler(const Params &p)
: SimObject(p),
- sysClkDomain(p->sys_clk_domain),
- enableHandler(p->enable),
- _transLatency(p->transition_latency)
+ sysClkDomain(p.sys_clk_domain),
+ enableHandler(p.enable),
+ _transLatency(p.transition_latency)
{
// Check supplied list of domains for sanity and add them to the
// domain ID -> domain* hash
- for (auto dit = p->domains.begin(); dit != p->domains.end(); ++dit) {
+ for (auto dit = p.domains.begin(); dit != p.domains.end(); ++dit) {
SrcClockDomain *d = *dit;
DomainID domain_id = d->domainID();
}
DVFSHandler*
-DVFSHandlerParams::create()
+DVFSHandlerParams::create() const
{
- return new DVFSHandler(this);
+ return new DVFSHandler(*this);
}
{
public:
typedef DVFSHandlerParams Params;
- DVFSHandler(const Params *p);
+ DVFSHandler(const Params &p);
typedef SrcClockDomain::DomainID DomainID;
typedef SrcClockDomain::PerfLevel PerfLevel;
const std::string &filename;
public:
- EmulatedDriver(EmulatedDriverParams *p)
- : SimObject(p), filename(p->filename)
+ EmulatedDriver(const EmulatedDriverParams &p)
+ : SimObject(p), filename(p.filename)
{
}
class InstTracer : public SimObject
{
public:
- InstTracer(const Params *p) : SimObject(p)
+ InstTracer(const Params &p) : SimObject(p)
{}
virtual ~InstTracer()
#include "params/KernelWorkload.hh"
#include "sim/system.hh"
-KernelWorkload::KernelWorkload(const Params &p) : Workload(&p), _params(p),
+KernelWorkload::KernelWorkload(const Params &p) : Workload(p), _params(p),
_loadAddrMask(p.load_addr_mask), _loadAddrOffset(p.load_addr_offset),
commandLine(p.command_line)
{
}
KernelWorkload *
-KernelWorkloadParams::create()
+KernelWorkloadParams::create() const
{
return new KernelWorkload(*this);
}
#include "sim/power/thermal_model.hh"
#include "sim/sim_object.hh"
-MathExprPowerModel::MathExprPowerModel(const Params *p)
- : PowerModelState(p), dyn_expr(p->dyn), st_expr(p->st)
+MathExprPowerModel::MathExprPowerModel(const Params &p)
+ : PowerModelState(p), dyn_expr(p.dyn), st_expr(p.st)
{
}
}
MathExprPowerModel*
-MathExprPowerModelParams::create()
+MathExprPowerModelParams::create() const
{
- return new MathExprPowerModel(this);
+ return new MathExprPowerModel(*this);
}
public:
typedef MathExprPowerModelParams Params;
- MathExprPowerModel(const Params *p);
+ MathExprPowerModel(const Params &p);
/**
* Get the dynamic power consumption.
#include "sim/clocked_object.hh"
#include "sim/sub_system.hh"
-PowerModelState::PowerModelState(const Params *p)
+PowerModelState::PowerModelState(const Params &p)
: SimObject(p), _temp(0), clocked_object(NULL)
{
}
-PowerModel::PowerModel(const Params *p)
- : SimObject(p), states_pm(p->pm), subsystem(p->subsystem),
- clocked_object(NULL), power_model_type(p->pm_type)
+PowerModel::PowerModel(const Params &p)
+ : SimObject(p), states_pm(p.pm), subsystem(p.subsystem),
+ clocked_object(NULL), power_model_type(p.pm_type)
{
panic_if(subsystem == NULL,
"Subsystem is NULL! This is not acceptable for a PowerModel!\n");
// The temperature passed here will be overwritten, if there is
// a thermal model present
for (auto & pms: states_pm){
- pms->setTemperature(p->ambient_temp);
+ pms->setTemperature(p.ambient_temp);
}
}
}
PowerModel*
-PowerModelParams::create()
+PowerModelParams::create() const
{
- return new PowerModel(this);
+ return new PowerModel(*this);
}
double
public:
typedef PowerModelStateParams Params;
- PowerModelState(const Params *p);
+ PowerModelState(const Params &p);
/**
* Get the dynamic power consumption.
dynamicPower
.method(this, &PowerModelState::getDynamicPower)
- .name(params()->name + ".dynamic_power")
+ .name(params().name + ".dynamic_power")
.desc("Dynamic power for this object (Watts)")
;
staticPower
.method(this, &PowerModelState::getStaticPower)
- .name(params()->name + ".static_power")
+ .name(params().name + ".static_power")
.desc("Static power for this object (Watts)")
;
}
public:
typedef PowerModelParams Params;
- PowerModel(const Params *p);
+ PowerModel(const Params &p);
/**
* Get the dynamic power consumption.
dynamicPower
.method(this, &PowerModel::getDynamicPower)
- .name(params()->name + ".dynamic_power")
+ .name(params().name + ".dynamic_power")
.desc("Dynamic power for this power state")
;
staticPower
.method(this, &PowerModel::getStaticPower)
- .name(params()->name + ".static_power")
+ .name(params().name + ".static_power")
.desc("Static power for this power state")
;
}
#include "sim/probe/probe.hh"
#include "sim/sub_system.hh"
-ThermalDomain::ThermalDomain(const Params *p)
- : SimObject(p), _initTemperature(p->initial_temperature),
+ThermalDomain::ThermalDomain(const Params &p)
+ : SimObject(p), _initTemperature(p.initial_temperature),
node(NULL), subsystem(NULL)
{
}
currentTemp
.method(this, &ThermalDomain::currentTemperature)
- .name(params()->name + ".temp")
+ .name(params().name + ".temp")
.desc("Temperature in centigrate degrees")
;
}
}
ThermalDomain *
-ThermalDomainParams::create()
+ThermalDomainParams::create() const
{
- return new ThermalDomain(this);
+ return new ThermalDomain(*this);
}
void
public:
typedef ThermalDomainParams Params;
- ThermalDomain(const Params *p);
+ ThermalDomain(const Params &p);
/**
* Get the startup temperature.
/**
* ThermalReference
*/
-ThermalReference::ThermalReference(const Params *p)
- : SimObject(p), _temperature(p->temperature), node(NULL)
+ThermalReference::ThermalReference(const Params &p)
+ : SimObject(p), _temperature(p.temperature), node(NULL)
{
}
ThermalReference *
-ThermalReferenceParams::create()
+ThermalReferenceParams::create() const
{
- return new ThermalReference(this);
+ return new ThermalReference(*this);
}
void
/**
* ThermalResistor
*/
-ThermalResistor::ThermalResistor(const Params *p)
- : SimObject(p), _resistance(p->resistance), node1(NULL), node2(NULL)
+ThermalResistor::ThermalResistor(const Params &p)
+ : SimObject(p), _resistance(p.resistance), node1(NULL), node2(NULL)
{
}
ThermalResistor *
-ThermalResistorParams::create()
+ThermalResistorParams::create() const
{
- return new ThermalResistor(this);
+ return new ThermalResistor(*this);
}
void
/**
* ThermalCapacitor
*/
-ThermalCapacitor::ThermalCapacitor(const Params *p)
- : SimObject(p), _capacitance(p->capacitance), node1(NULL), node2(NULL)
+ThermalCapacitor::ThermalCapacitor(const Params &p)
+ : SimObject(p), _capacitance(p.capacitance), node1(NULL), node2(NULL)
{
}
ThermalCapacitor *
-ThermalCapacitorParams::create()
+ThermalCapacitorParams::create() const
{
- return new ThermalCapacitor(this);
+ return new ThermalCapacitor(*this);
}
void
/**
* ThermalModel
*/
-ThermalModel::ThermalModel(const Params *p)
- : ClockedObject(p), stepEvent([this]{ doStep(); }, name()), _step(p->step)
+ThermalModel::ThermalModel(const Params &p)
+ : ClockedObject(p), stepEvent([this]{ doStep(); }, name()), _step(p.step)
{
}
ThermalModel *
-ThermalModelParams::create()
+ThermalModelParams::create() const
{
- return new ThermalModel(this);
+ return new ThermalModel(*this);
}
void
{
public:
typedef ThermalResistorParams Params;
- ThermalResistor(const Params *p);
+ ThermalResistor(const Params &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
{
public:
typedef ThermalCapacitorParams Params;
- ThermalCapacitor(const Params *p);
+ ThermalCapacitor(const Params &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
{
public:
typedef ThermalReferenceParams Params;
- ThermalReference(const Params *p);
+ ThermalReference(const Params &p);
- void setNode(ThermalNode * n) {
+ void
+ setNode(ThermalNode *n)
+ {
node = n;
}
{
public:
typedef ThermalModelParams Params;
- ThermalModel(const Params *p);
+ ThermalModel(const Params &p);
void addDomain(ThermalDomain * d);
void addReference(ThermalReference * r);
/**
* ThermalNode
*/
-ThermalNode::ThermalNode(const ThermalNodeParams *p)
+ThermalNode::ThermalNode(const ThermalNodeParams &p)
: SimObject(p), id(-1), isref(false), temp(0.0f)
{
}
ThermalNode *
-ThermalNodeParams::create()
+ThermalNodeParams::create() const
{
- return new ThermalNode(this);
+ return new ThermalNode(*this);
}
class ThermalNode : public SimObject
{
public:
- ThermalNode(const ThermalNodeParams *p);
+ ThermalNode(const ThermalNodeParams &p);
int id;
bool isref;
#include "base/trace.hh"
#include "debug/PowerDomain.hh"
-PowerDomain::PowerDomain(const PowerDomainParams* p) :
+PowerDomain::PowerDomain(const PowerDomainParams &p) :
PowerState(p),
- leaders(p->leaders),
+ leaders(p.leaders),
pwrStateUpdateEvent(*this),
stats(*this)
{
}
PowerDomain*
-PowerDomainParams::create()
+PowerDomainParams::create() const
{
- return new PowerDomain(this);
+ return new PowerDomain(*this);
}
class PowerDomain : public PowerState
{
public:
- PowerDomain(const PowerDomainParams* p);
+ PowerDomain(const PowerDomainParams &p);
typedef PowerDomainParams Params;
~PowerDomain() override {};
#include "debug/PowerDomain.hh"
#include "sim/power_domain.hh"
-PowerState::PowerState(const PowerStateParams *p) :
- SimObject(p), _currState(p->default_state),
- possibleStates(p->possible_states.begin(),
- p->possible_states.end()),
+PowerState::PowerState(const PowerStateParams &p) :
+ SimObject(p), _currState(p.default_state),
+ possibleStates(p.possible_states.begin(),
+ p.possible_states.end()),
stats(*this)
{
- for (auto &pm: p->leaders) {
+ for (auto &pm: p.leaders) {
// Register this object as a follower. This object is
// dependent on pm for power state transitions
pm->addFollower(this);
using namespace Stats;
- const PowerStateParams *p = powerState.params();
+ const PowerStateParams &p = powerState.params();
numTransitions.flags(nozero);
numPwrMatchStateTransitions.flags(nozero);
// Each sample is time in ticks
- unsigned num_bins = std::max(p->clk_gate_bins, 10U);
+ unsigned num_bins = std::max(p.clk_gate_bins, 10U);
ticksClkGated
- .init(p->clk_gate_min, p->clk_gate_max,
- (p->clk_gate_max / num_bins))
+ .init(p.clk_gate_min, p.clk_gate_max, (p.clk_gate_max / num_bins))
.flags(pdf | nozero | nonan)
;
}
PowerState*
-PowerStateParams::create()
+PowerStateParams::create() const
{
- return new PowerState(this);
+ return new PowerState(*this);
}
class PowerState : public SimObject
{
public:
- PowerState(const PowerStateParams *p);
+ PowerState(const PowerStateParams &p);
/** Parameters of PowerState object */
typedef PowerStateParams Params;
- const Params* params() const
+ const Params &
+ params() const
{
- return reinterpret_cast<const Params*>(_params);
+ return reinterpret_cast<const Params &>(_params);
}
virtual void addFollower(PowerState* pwr_obj) {};
}
}
-ProbeListenerObject::ProbeListenerObject(const ProbeListenerObjectParams *params)
+ProbeListenerObject::ProbeListenerObject(
+ const ProbeListenerObjectParams ¶ms)
: SimObject(params),
- manager(params->manager->getProbeManager())
+ manager(params.manager->getProbeManager())
{
}
}
ProbeListenerObject*
-ProbeListenerObjectParams::create()
+ProbeListenerObjectParams::create() const
{
- return new ProbeListenerObject(this);
+ return new ProbeListenerObject(*this);
}
bool
std::vector<ProbeListener *> listeners;
public:
- ProbeListenerObject(const ProbeListenerObjectParams *params);
+ ProbeListenerObject(const ProbeListenerObjectParams ¶ms);
virtual ~ProbeListenerObject();
ProbeManager* getProbeManager() { return manager; }
};
}
Process *
-Process::tryLoaders(ProcessParams *params, ::Loader::ObjectFile *obj_file)
+Process::tryLoaders(const ProcessParams ¶ms,
+ ::Loader::ObjectFile *obj_file)
{
for (auto &loader: process_loaders()) {
Process *p = loader->load(params, obj_file);
}
static std::string
-normalize(std::string& directory)
+normalize(const std::string& directory)
{
if (directory.back() != '/')
- directory += '/';
+ return directory + '/';
return directory;
}
-Process::Process(ProcessParams *params, EmulationPageTable *pTable,
+Process::Process(const ProcessParams ¶ms, EmulationPageTable *pTable,
::Loader::ObjectFile *obj_file)
- : SimObject(params), system(params->system),
- useArchPT(params->useArchPT),
- kvmInSE(params->kvmInSE),
+ : SimObject(params), system(params.system),
+ useArchPT(params.useArchPT),
+ kvmInSE(params.kvmInSE),
useForClone(false),
pTable(pTable),
objFile(obj_file),
- argv(params->cmd), envp(params->env),
- executable(params->executable),
- tgtCwd(normalize(params->cwd)),
+ argv(params.cmd), envp(params.env),
+ executable(params.executable == "" ? params.cmd[0] : params.executable),
+ tgtCwd(normalize(params.cwd)),
hostCwd(checkPathRedirect(tgtCwd)),
- release(params->release),
- _uid(params->uid), _euid(params->euid),
- _gid(params->gid), _egid(params->egid),
- _pid(params->pid), _ppid(params->ppid),
- _pgid(params->pgid), drivers(params->drivers),
- fds(make_shared<FDArray>(params->input, params->output, params->errout)),
+ release(params.release),
+ _uid(params.uid), _euid(params.euid),
+ _gid(params.gid), _egid(params.egid),
+ _pid(params.pid), _ppid(params.ppid),
+ _pgid(params.pgid), drivers(params.drivers),
+ fds(make_shared<FDArray>(params.input, params.output, params.errout)),
childClearTID(0)
{
if (_pid >= System::maxPID)
* with a new, equivalent value. If CLONE_THREAD is specified, patch
* the tgid value with the old process' value.
*/
- _tgid = params->pid;
+ _tgid = params.pid;
exitGroup = new bool();
sigchld = new bool();
}
Process *
-ProcessParams::create()
+ProcessParams::create() const
{
// If not specified, set the executable parameter equal to the
// simulated system's zeroth command line parameter
- if (executable == "") {
- executable = cmd[0];
- }
+ const std::string &exec = (executable == "") ? cmd[0] : executable;
- auto *obj_file = Loader::createObjectFile(executable);
- fatal_if(!obj_file, "Cannot load object file %s.", executable);
+ auto *obj_file = Loader::createObjectFile(exec);
+ fatal_if(!obj_file, "Cannot load object file %s.", exec);
- Process *process = Process::tryLoaders(this, obj_file);
+ Process *process = Process::tryLoaders(*this, obj_file);
fatal_if(!process, "Unknown error creating process object.");
return process;
class Process : public SimObject
{
public:
- Process(ProcessParams *params, EmulationPageTable *pTable,
+ Process(const ProcessParams ¶ms, EmulationPageTable *pTable,
::Loader::ObjectFile *obj_file);
void serialize(CheckpointOut &cp) const override;
* error like file IO errors, etc., those should fail non-silently
* with a panic or fail as normal.
*/
- virtual Process *load(ProcessParams *params,
+ virtual Process *load(const ProcessParams ¶ms,
::Loader::ObjectFile *obj_file) = 0;
};
// Try all the Loader instance's "load" methods one by one until one is
// successful. If none are, complain and fail.
- static Process *tryLoaders(ProcessParams *params,
+ static Process *tryLoaders(const ProcessParams ¶ms,
::Loader::ObjectFile *obj_file);
::Loader::ObjectFile *objFile;
if (!FullSystem)
panicFsOnlyPseudoInst("loadsymbol");
- const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
+ const string &filename = tc->getCpuPtr()->system->params().symbolfile;
if (filename.empty()) {
return;
}
resetstats(ThreadContext *tc, Tick delay, Tick period)
{
DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period);
- if (!tc->getCpuPtr()->params()->do_statistics_insts)
+ if (!tc->getCpuPtr()->params().do_statistics_insts)
return;
dumpstats(ThreadContext *tc, Tick delay, Tick period)
{
DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period);
- if (!tc->getCpuPtr()->params()->do_statistics_insts)
+ if (!tc->getCpuPtr()->params().do_statistics_insts)
return;
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
{
DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period);
- if (!tc->getCpuPtr()->params()->do_statistics_insts)
+ if (!tc->getCpuPtr()->params().do_statistics_insts)
return;
m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
{
DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
- if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
+ if (!tc->getCpuPtr()->params().do_checkpoint_insts)
return;
if (DistIface::readyToCkpt(delay, period)) {
return 0;
}
- const string &file = tc->getSystemPtr()->params()->readfile;
+ const string &file = tc->getSystemPtr()->params().readfile;
if (file.empty()) {
return ULL(0);
}
{
DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid);
System *sys = tc->getSystemPtr();
- const System::Params *params = sys->params();
+ const System::Params ¶ms = sys->params();
- if (params->exit_on_work_items) {
+ if (params.exit_on_work_items) {
exitSimLoop("workbegin", static_cast<int>(workid));
return;
}
// If specified, determine if this is the specific work item the user
// identified
//
- if (params->work_item_id == -1 || params->work_item_id == workid) {
+ if (params.work_item_id == -1 || params.work_item_id == workid) {
uint64_t systemWorkBeginCount = sys->incWorkItemsBegin();
int cpuId = tc->getCpuPtr()->cpuId();
- if (params->work_cpus_ckpt_count != 0 &&
- sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
+ if (params.work_cpus_ckpt_count != 0 &&
+ sys->markWorkItem(cpuId) >= params.work_cpus_ckpt_count) {
//
// If active cpus equals checkpoint count, create checkpoint
//
exitSimLoop("checkpoint");
}
- if (systemWorkBeginCount == params->work_begin_ckpt_count) {
+ if (systemWorkBeginCount == params.work_begin_ckpt_count) {
//
// Note: the string specified as the cause of the exit event must
// exactly equal "checkpoint" inorder to create a checkpoint
exitSimLoop("checkpoint");
}
- if (systemWorkBeginCount == params->work_begin_exit_count) {
+ if (systemWorkBeginCount == params.work_begin_exit_count) {
//
// If a certain number of work items started, exit simulation
//
exitSimLoop("work started count reach");
}
- if (cpuId == params->work_begin_cpu_id_exit) {
+ if (cpuId == params.work_begin_cpu_id_exit) {
//
// If work started on the cpu id specified, exit simulation
//
{
DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid);
System *sys = tc->getSystemPtr();
- const System::Params *params = sys->params();
+ const System::Params ¶ms = sys->params();
- if (params->exit_on_work_items) {
+ if (params.exit_on_work_items) {
exitSimLoop("workend", static_cast<int>(workid));
return;
}
// If specified, determine if this is the specific work item the user
// identified
//
- if (params->work_item_id == -1 || params->work_item_id == workid) {
+ if (params.work_item_id == -1 || params.work_item_id == workid) {
uint64_t systemWorkEndCount = sys->incWorkItemsEnd();
int cpuId = tc->getCpuPtr()->cpuId();
- if (params->work_cpus_ckpt_count != 0 &&
- sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
+ if (params.work_cpus_ckpt_count != 0 &&
+ sys->markWorkItem(cpuId) >= params.work_cpus_ckpt_count) {
//
// If active cpus equals checkpoint count, create checkpoint
//
exitSimLoop("checkpoint");
}
- if (params->work_end_ckpt_count != 0 &&
- systemWorkEndCount == params->work_end_ckpt_count) {
+ if (params.work_end_ckpt_count != 0 &&
+ systemWorkEndCount == params.work_end_ckpt_count) {
//
// If total work items completed equals checkpoint count, create
// checkpoint
exitSimLoop("checkpoint");
}
- if (params->work_end_exit_count != 0 &&
- systemWorkEndCount == params->work_end_exit_count) {
+ if (params.work_end_exit_count != 0 &&
+ systemWorkEndCount == params.work_end_exit_count) {
//
// If total work items completed equals exit count, exit simulation
//
return path;
}
-RedirectPath::RedirectPath(const RedirectPathParams *p)
+RedirectPath::RedirectPath(const RedirectPathParams &p)
: SimObject(p)
{
- _appPath = normalizePath(p->app_path);
+ _appPath = normalizePath(p.app_path);
- for (auto hp : p->host_paths) {
+ for (auto hp : p.host_paths) {
_hostPaths.push_back(normalizePath(hp));
}
}
RedirectPath*
-RedirectPathParams::create()
+RedirectPathParams::create() const
{
- return new RedirectPath(this);
+ return new RedirectPath(*this);
}
class RedirectPath : public SimObject
{
public:
- RedirectPath(const RedirectPathParams *p);
+ RedirectPath(const RedirectPathParams &p);
const std::string& appPath() { return _appPath; };
const std::vector<std::string>& hostPaths() { return _hostPaths; };
timeSyncEnable(en);
}
-Root::Root(RootParams *p)
- : SimObject(p), _enabled(false), _periodTick(p->time_sync_period),
+Root::Root(const RootParams &p)
+ : SimObject(p), _enabled(false), _periodTick(p.time_sync_period),
syncEvent([this]{ timeSync(); }, name())
{
- _period.setTick(p->time_sync_period);
- _spinThreshold.setTick(p->time_sync_spin_threshold);
+ _period.setTick(p.time_sync_period);
+ _spinThreshold.setTick(p.time_sync_spin_threshold);
assert(_root == NULL);
_root = this;
lastTime.setTimer();
- simQuantum = p->sim_quantum;
+ simQuantum = p.sim_quantum;
// Some of the statistics are global and need to be accessed by
// stat formulas. The most convenient way to implement that is by
void
Root::startup()
{
- timeSyncEnable(params()->time_sync_enable);
+ timeSyncEnable(params().time_sync_enable);
}
void
unsigned int FullSystemInt;
Root *
-RootParams::create()
+RootParams::create() const
{
static bool created = false;
if (created)
FullSystem = full_system;
FullSystemInt = full_system ? 1 : 0;
- return new Root(this);
+ return new Root(*this);
}
void timeSyncSpinThreshold(Time newThreshold);
typedef RootParams Params;
- const Params *
+ const Params &
params() const
{
- return dynamic_cast<const Params *>(_params);
+ return dynamic_cast<const Params &>(_params);
}
- Root(Params *p);
+ Root(const Params &p);
/** Schedule the timesync event at startup().
*/
#include "params/SEWorkload.hh"
#include "sim/process.hh"
-SEWorkload::SEWorkload(const Params &p) : Workload(&p), _params(p)
+SEWorkload::SEWorkload(const Params &p) : Workload(p), _params(p)
{}
void
}
SEWorkload *
-SEWorkloadParams::create()
+SEWorkloadParams::create() const
{
return new SEWorkload(*this);
}
//
// SimObject constructor: used to maintain static simObjectList
//
-SimObject::SimObject(const Params *p)
- : EventManager(getEventQueue(p->eventq_index)),
+SimObject::SimObject(const Params &p)
+ : EventManager(getEventQueue(p.eventq_index)),
Stats::Group(nullptr),
_params(p)
{
*
* @ingroup api_simobject
*/
- const SimObjectParams *_params;
+ const SimObjectParams &_params;
public:
typedef SimObjectParams Params;
*
* @ingroup api_simobject
*/
- const Params *params() const { return _params; }
+ const Params ¶ms() const { return _params; }
/**
* @ingroup api_simobject
*/
- SimObject(const Params *_params);
+ SimObject(const Params &_params);
virtual ~SimObject();
/**
* @ingroup api_simobject
*/
- virtual const std::string name() const { return params()->name; }
+ virtual const std::string name() const { return params().name; }
/**
* init() is called after all C++ SimObjects have been created and
#include "sim/power/power_model.hh"
#include "sim/power/thermal_domain.hh"
-SubSystem::SubSystem(const Params *p)
+SubSystem::SubSystem(const Params &p)
: SimObject(p)
{
// Link thermalDomain <-> SubSystem
- if (p->thermal_domain)
- p->thermal_domain->setSubSystem(this);
+ if (p.thermal_domain)
+ p.thermal_domain->setSubSystem(this);
}
double
}
SubSystem *
-SubSystemParams::create()
+SubSystemParams::create() const
{
- return new SubSystem(this);
+ return new SubSystem(*this);
}
{
public:
typedef SubSystemParams Params;
- SubSystem(const Params *p);
+ SubSystem(const Params &p);
double getDynamicPower() const;
int System::numSystemsRunning = 0;
-System::System(Params *p)
+System::System(const Params &p)
: SimObject(p), _systemPort("system_port", this),
- multiThread(p->multi_thread),
+ multiThread(p.multi_thread),
pagePtr(0),
- init_param(p->init_param),
- physProxy(_systemPort, p->cache_line_size),
- workload(p->workload),
+ init_param(p.init_param),
+ physProxy(_systemPort, p.cache_line_size),
+ workload(p.workload),
#if USE_KVM
- kvmVM(p->kvm_vm),
+ kvmVM(p.kvm_vm),
#else
kvmVM(nullptr),
#endif
- physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve,
- p->shared_backstore),
- memoryMode(p->mem_mode),
- _cacheLineSize(p->cache_line_size),
+ physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
+ p.shared_backstore),
+ memoryMode(p.mem_mode),
+ _cacheLineSize(p.cache_line_size),
workItemsBegin(0),
workItemsEnd(0),
- numWorkIds(p->num_work_ids),
- thermalModel(p->thermal_model),
+ numWorkIds(p.num_work_ids),
+ thermalModel(p.thermal_model),
_params(p),
- _m5opRange(p->m5ops_base ?
- RangeSize(p->m5ops_base, 0x10000) :
+ _m5opRange(p.m5ops_base ?
+ RangeSize(p.m5ops_base, 0x10000) :
AddrRange(1, 0)), // Create an empty range if disabled
totalNumInsts(0),
- redirectPaths(p->redirect_paths)
+ redirectPaths(p.redirect_paths)
{
if (workload)
workload->system = this;
numSystemsRunning++;
// Set back pointers to the system in all memories
- for (int x = 0; x < params()->memories.size(); x++)
- params()->memories[x]->system(this);
+ for (int x = 0; x < params().memories.size(); x++)
+ params().memories[x]->system(this);
}
System::~System()
}
System *
-SystemParams::create()
+SystemParams::create() const
{
- return new System(this);
+ return new System(*this);
}
ByteOrder
getGuestByteOrder() const
{
- return _params->byte_order;
+ return _params.byte_order;
}
/**
typedef SystemParams Params;
protected:
- Params *_params;
+ const Params &_params;
/**
* Range for memory-mapped m5 pseudo ops. The range will be
const AddrRange _m5opRange;
public:
- System(Params *p);
+ System(const Params &p);
~System();
- const Params *params() const { return (const Params *)_params; }
+ const Params ¶ms() const { return (const Params &)_params; }
/**
* Range used by memory-mapped m5 pseudo-ops if enabled. Returns
lastStopped = Cycles(lastStoppedUint);
}
-TickedObject::TickedObject(const TickedObjectParams *params,
+TickedObject::TickedObject(const TickedObjectParams ¶ms,
Event::Priority priority) :
ClockedObject(params),
/* Make numCycles in Ticked */
class TickedObject : public ClockedObject, public Ticked
{
public:
- TickedObject(const TickedObjectParams *params,
+ TickedObject(const TickedObjectParams ¶ms,
Event::Priority priority = Event::CPU_Tick_Pri);
/** Disambiguate to make these functions overload correctly */
#include "params/VoltageDomain.hh"
#include "sim/sim_object.hh"
-VoltageDomain::VoltageDomain(const Params *p)
- : SimObject(p), voltageOpPoints(p->voltage), _perfLevel(0), stats(*this)
+VoltageDomain::VoltageDomain(const Params &p)
+ : SimObject(p), voltageOpPoints(p.voltage), _perfLevel(0), stats(*this)
{
fatal_if(voltageOpPoints.empty(), "DVFS: Empty set of voltages for "\
"voltage domain %s\n", name());
}
VoltageDomain *
-VoltageDomainParams::create()
+VoltageDomainParams::create() const
{
- return new VoltageDomain(this);
+ return new VoltageDomain(*this);
}
void
public:
typedef VoltageDomainParams Params;
- VoltageDomain(const Params *p);
+ VoltageDomain(const Params &p);
typedef SrcClockDomain::PerfLevel PerfLevel;
} stats;
public:
- Workload(const WorkloadParams *_params) : SimObject(_params), stats(this)
+ Workload(const WorkloadParams &_params) : SimObject(_params), stats(this)
{}
void recordQuiesce() { stats.quiesce++; }
sc_core::sc_status Kernel::status() { return _status; }
void Kernel::status(sc_core::sc_status s) { _status = s; }
-Kernel::Kernel(Params *params) :
+Kernel::Kernel(const Params ¶ms) :
SimObject(params), t0Event(this, false, EventBase::Default_Pri - 1)
{
// Install ourselves as the scheduler's event manager.
} // namespace sc_gem5
sc_gem5::Kernel *
-SystemC_KernelParams::create()
+SystemC_KernelParams::create() const
{
panic_if(sc_gem5::kernel,
"Only one systemc kernel object may be defined.\n");
- sc_gem5::kernel = new sc_gem5::Kernel(this);
+ sc_gem5::kernel = new sc_gem5::Kernel(*this);
return sc_gem5::kernel;
}
{
public:
typedef SystemC_KernelParams Params;
- Kernel(Params *params);
+ Kernel(const Params ¶ms);
void init() override;
void regStats() override;
template <unsigned int BITWIDTH>
Gem5ToTlmBridge<BITWIDTH>::Gem5ToTlmBridge(
- Params *params, const sc_core::sc_module_name &mn) :
+ const Params ¶ms, const sc_core::sc_module_name &mn) :
Gem5ToTlmBridgeBase(mn),
bridgeResponsePort(std::string(name()) + ".gem5", *this),
socket("tlm_socket"),
wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
- system(params->system), blockingRequest(nullptr),
+ system(params.system), blockingRequest(nullptr),
needToSendRequestRetry(false), blockingResponse(nullptr),
- addrRanges(params->addr_ranges.begin(), params->addr_ranges.end())
+ addrRanges(params.addr_ranges.begin(), params.addr_ranges.end())
{
}
} // namespace sc_gem5
sc_gem5::Gem5ToTlmBridge<32> *
-Gem5ToTlmBridge32Params::create()
+Gem5ToTlmBridge32Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<32>(
- this, sc_core::sc_module_name(name.c_str()));
+ *this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::Gem5ToTlmBridge<64> *
-Gem5ToTlmBridge64Params::create()
+Gem5ToTlmBridge64Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<64>(
- this, sc_core::sc_module_name(name.c_str()));
+ *this, sc_core::sc_module_name(name.c_str()));
}
::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
typedef Gem5ToTlmBridgeBaseParams Params;
- Gem5ToTlmBridge(Params *p, const sc_core::sc_module_name &mn);
+ Gem5ToTlmBridge(const Params &p, const sc_core::sc_module_name &mn);
tlm_utils::simple_initiator_socket<Gem5ToTlmBridge<BITWIDTH>, BITWIDTH> &
getSocket()
template <unsigned int BITWIDTH>
TlmToGem5Bridge<BITWIDTH>::TlmToGem5Bridge(
- Params *params, const sc_core::sc_module_name &mn) :
+ const Params ¶ms, const sc_core::sc_module_name &mn) :
TlmToGem5BridgeBase(mn), peq(this, &TlmToGem5Bridge<BITWIDTH>::peq_cb),
waitForRetry(false), pendingRequest(nullptr), pendingPacket(nullptr),
needToSendRetry(false), responseInProgress(false),
bmp(std::string(name()) + "master", *this), socket("tlm_socket"),
wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
- system(params->system),
- _id(params->system->getGlobalRequestorId(
+ system(params.system),
+ _id(params.system->getGlobalRequestorId(
std::string("[systemc].") + name()))
{
}
} // namespace sc_gem5
sc_gem5::TlmToGem5Bridge<32> *
-TlmToGem5Bridge32Params::create()
+TlmToGem5Bridge32Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<32>(
- this, sc_core::sc_module_name(name.c_str()));
+ *this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::TlmToGem5Bridge<64> *
-TlmToGem5Bridge64Params::create()
+TlmToGem5Bridge64Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<64>(
- this, sc_core::sc_module_name(name.c_str()));
+ *this, sc_core::sc_module_name(name.c_str()));
}
::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
typedef TlmToGem5BridgeBaseParams Params;
- TlmToGem5Bridge(Params *p, const sc_core::sc_module_name &mn);
+ TlmToGem5Bridge(const Params &p, const sc_core::sc_module_name &mn);
tlm_utils::simple_target_socket<TlmToGem5Bridge<BITWIDTH>, BITWIDTH> &
getSocket()
projects / gem5.git / commitdiff