| PO | RT | 0 | FRB | XO | RCS | X-Form |
```
-if RCS[0] = 1 then # if Single mode
- RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses
-else
- RT <- (FRB)
+ if RCS[0] = 1 then # if Single mode
+ RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses
+ else
+ RT <- (FRB)
```
move a 32/64-bit float from a FPR to a GPR, just copying bits of the IEEE 754 representation directly. This is equivalent to `stfs` followed by `lwz` or equivalent to `stfd` followed by `ld`.
| PO | FRT | 0 | RB | XO | RCS | X-Form |
```
-if RCS[0] = 1 then # if Single mode
- FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses
-else
- FRT <- (RB)
+ if RCS[0] = 1 then # if Single mode
+ FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses
+ else
+ FRT <- (RB)
```
move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE 754 representation directly. This is equivalent to `stw` followed by `lfs` or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits, `FPSCR` is not affected in any way.
`fcvtfg FRT, RB, IT, RCS`
```
-if IT[0] = 0 and RCS[0] = 0 then # 32-bit int -> 64-bit float
- # rounding never necessary, so don't touch FPSCR
- # based off xvcvsxwdp
- if IT = 0 then # Signed 32-bit
- src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
- else # IT = 1 -- Unsigned 32-bit
- src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
- FRT <- bfp64_CONVERT_FROM_BFP(src)
-else
- # rounding may be necessary
- # based off xscvuxdsp
- reset_xflags()
- switch(IT)
- case(0): # Signed 32-bit
+ if IT[0] = 0 and RCS[0] = 0 then # 32-bit int -> 64-bit float
+ # rounding never necessary, so don't touch FPSCR
+ # based off xvcvsxwdp
+ if IT = 0 then # Signed 32-bit
src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
- case(1): # Unsigned 32-bit
+ else # IT = 1 -- Unsigned 32-bit
src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
- case(2): # Signed 64-bit
- src <- bfp_CONVERT_FROM_SI64((RB))
- default: # Unsigned 64-bit
- src <- bfp_CONVERT_FROM_UI64((RB))
- if RCS[0] = 1 then # Single
- rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
- result32 <- bfp32_CONVERT_FROM_BFP(rnd)
- cls <- fprf_CLASS_BFP32(result32)
- result <- DOUBLE(result32)
+ FRT <- bfp64_CONVERT_FROM_BFP(src)
else
- rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
- result <- bfp64_CONVERT_FROM_BFP(rnd)
- cls <- fprf_CLASS_BFP64(result)
+ # rounding may be necessary
+ # based off xscvuxdsp
+ reset_xflags()
+ switch(IT)
+ case(0): # Signed 32-bit
+ src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
+ case(1): # Unsigned 32-bit
+ src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
+ case(2): # Signed 64-bit
+ src <- bfp_CONVERT_FROM_SI64((RB))
+ default: # Unsigned 64-bit
+ src <- bfp_CONVERT_FROM_UI64((RB))
+ if RCS[0] = 1 then # Single
+ rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
+ result32 <- bfp32_CONVERT_FROM_BFP(rnd)
+ cls <- fprf_CLASS_BFP32(result32)
+ result <- DOUBLE(result32)
+ else
+ rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
+ result <- bfp64_CONVERT_FROM_BFP(rnd)
+ cls <- fprf_CLASS_BFP64(result)
- if xx_flag = 1 then SetFX(FPSCR.XX)
+ if xx_flag = 1 then SetFX(FPSCR.XX)
- FRT <- result
- FPSCR.FPRF <- cls
- FPSCR.FR <- inc_flag
- FPSCR.FI <- xx_flag
+ FRT <- result
+ FPSCR.FPRF <- cls
+ FPSCR.FR <- inc_flag
+ FPSCR.FI <- xx_flag
```
Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit float in FRT, following the usual 32-bit float in 64-bit float format.
OpenPower conversion semantics (section A.2 page 1009 (page 1035) of Power ISA v3.1B):
```
-def fp_to_int_open_power<fp, int>(v: fp) -> int:
- if v is NaN:
- return int::MIN_VALUE
- if v >= int::MAX_VALUE:
- return int::MAX_VALUE
- if v <= int::MIN_VALUE:
- return int::MIN_VALUE
- return (int)rint(v, rounding_mode)
+ def fp_to_int_open_power<fp, int>(v: fp) -> int:
+ if v is NaN:
+ return int::MIN_VALUE
+ if v >= int::MAX_VALUE:
+ return int::MAX_VALUE
+ if v <= int::MIN_VALUE:
+ return int::MIN_VALUE
+ return (int)rint(v, rounding_mode)
```
<div id="fp-to-int-java-saturating-conversion-semantics"></div>
(with adjustment to add non-truncate rounding modes):
```
-def fp_to_int_java_saturating<fp, int>(v: fp) -> int:
- if v is NaN:
- return 0
- if v >= int::MAX_VALUE:
- return int::MAX_VALUE
- if v <= int::MIN_VALUE:
- return int::MIN_VALUE
- return (int)rint(v, rounding_mode)
+ def fp_to_int_java_saturating<fp, int>(v: fp) -> int:
+ if v is NaN:
+ return 0
+ if v >= int::MAX_VALUE:
+ return int::MAX_VALUE
+ if v <= int::MIN_VALUE:
+ return int::MIN_VALUE
+ return (int)rint(v, rounding_mode)
```
<div id="fp-to-int-javascript-conversion-semantics"></div>
[conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):
```
-def fp_to_int_java_script<fp, int>(v: fp) -> int:
- if v is NaN or infinite:
- return 0
- v = rint(v, rounding_mode) # assume no loss of precision in result
- v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative
- bits = (uint)v
- return (int)bits
+ def fp_to_int_java_script<fp, int>(v: fp) -> int:
+ if v is NaN or infinite:
+ return 0
+ v = rint(v, rounding_mode) # assume no loss of precision in result
+ v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative
+ bits = (uint)v
+ return (int)bits
```
## Floating-point Convert To GPR
`fcvttgo RT, FRB, CVM, IT, RCS`
```
-# based on xscvdpuxws
-reset_xflags()
-
-if RCS[0] = 1 then # if Single mode
- src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
-else
- src <- bfp_CONVERT_FROM_BFP64((FRB))
-
-switch(IT)
- case(0): # Signed 32-bit
- range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
- range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
- js_mask <- 0xFFFF_FFFF
- case(1): # Unsigned 32-bit
- range_min <- bfp_CONVERT_FROM_UI32(0)
- range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
- js_mask <- 0xFFFF_FFFF
- case(2): # Signed 64-bit
- range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
- range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
- default: # Unsigned 64-bit
- range_min <- bfp_CONVERT_FROM_UI64(0)
- range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
-
-if CVM[2] = 1 or FPSCR.RN = 0b01 then
- rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
-else if FPSCR.RN = 0b00 then
- rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
-else if FPSCR.RN = 0b10 then
- rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
-else if FPSCR.RN = 0b11 then
- rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
-
-switch(CVM)
- case(0, 1): # OpenPower semantics
- if IsNaN(rnd) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(range_max)
- case(2, 3): # Java/Saturating semantics
- if IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(range_max)
- default: # JavaScript semantics
- # CVM = 6, 7 are illegal instructions
-
- # this works because the largest type we try to
- # convert from has 53 significand bits, and the
- # largest type we try to convert to has 64 bits,
- # and the sum of those is strictly less than the
- # 128 bits of the intermediate result.
- limit <- bfp_CONVERT_FROM_UI128([1] * 128)
- if IsInf(rnd) or IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
- result <- [0] * 64
- else
- result128 <- si128_CONVERT_FROM_BFP(rnd)
- result <- result128[64:127] & js_mask
-
-switch(IT)
- case(0): # Signed 32-bit
- result <- EXTS64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
- case(1): # Unsigned 32-bit
- result <- EXTZ64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
- case(2): # Signed 64-bit
- result_bfp <- bfp_CONVERT_FROM_SI64(result)
- default: # Unsigned 64-bit
- result_bfp <- bfp_CONVERT_FROM_UI64(result)
-
-if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
-if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
-if xx_flag = 1 then SetFX(FPSCR.XX)
-
-vx_flag <- vxsnan_flag | vxcvi_flag
-vex_flag <- FPSCR.VE & vx_flag
-
-if vex_flag = 0 then
- RT <- result
- FPSCR.FPRF <- undefined
- FPSCR.FR <- inc_flag
- FPSCR.FI <- xx_flag
- if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then
- overflow <- 1 # signals SO only when OE = 1
-else
- FPSCR.FR <- 0
- FPSCR.FI <- 0
+ # based on xscvdpuxws
+ reset_xflags()
+
+ if RCS[0] = 1 then # if Single mode
+ src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
+ else
+ src <- bfp_CONVERT_FROM_BFP64((FRB))
+
+ switch(IT)
+ case(0): # Signed 32-bit
+ range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
+ range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
+ js_mask <- 0xFFFF_FFFF
+ case(1): # Unsigned 32-bit
+ range_min <- bfp_CONVERT_FROM_UI32(0)
+ range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
+ js_mask <- 0xFFFF_FFFF
+ case(2): # Signed 64-bit
+ range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
+ range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
+ js_mask <- 0xFFFF_FFFF_FFFF_FFFF
+ default: # Unsigned 64-bit
+ range_min <- bfp_CONVERT_FROM_UI64(0)
+ range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
+ js_mask <- 0xFFFF_FFFF_FFFF_FFFF
+
+ if CVM[2] = 1 or FPSCR.RN = 0b01 then
+ rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
+ else if FPSCR.RN = 0b00 then
+ rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
+ else if FPSCR.RN = 0b10 then
+ rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
+ else if FPSCR.RN = 0b11 then
+ rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
+
+ switch(CVM)
+ case(0, 1): # OpenPower semantics
+ if IsNaN(rnd) then
+ result <- si64_CONVERT_FROM_BFP(range_min)
+ else if bfp_COMPARE_GT(rnd, range_max) then
+ result <- ui64_CONVERT_FROM_BFP(range_max)
+ else if bfp_COMPARE_LT(rnd, range_min) then
+ result <- si64_CONVERT_FROM_BFP(range_min)
+ else if IT[1] = 1 then # Unsigned 32/64-bit
+ result <- ui64_CONVERT_FROM_BFP(range_max)
+ else # Signed 32/64-bit
+ result <- si64_CONVERT_FROM_BFP(range_max)
+ case(2, 3): # Java/Saturating semantics
+ if IsNaN(rnd) then
+ result <- [0] * 64
+ else if bfp_COMPARE_GT(rnd, range_max) then
+ result <- ui64_CONVERT_FROM_BFP(range_max)
+ else if bfp_COMPARE_LT(rnd, range_min) then
+ result <- si64_CONVERT_FROM_BFP(range_min)
+ else if IT[1] = 1 then # Unsigned 32/64-bit
+ result <- ui64_CONVERT_FROM_BFP(range_max)
+ else # Signed 32/64-bit
+ result <- si64_CONVERT_FROM_BFP(range_max)
+ default: # JavaScript semantics
+ # CVM = 6, 7 are illegal instructions
+
+ # this works because the largest type we try to
+ # convert from has 53 significand bits, and the
+ # largest type we try to convert to has 64 bits,
+ # and the sum of those is strictly less than the
+ # 128 bits of the intermediate result.
+ limit <- bfp_CONVERT_FROM_UI128([1] * 128)
+ if IsInf(rnd) or IsNaN(rnd) then
+ result <- [0] * 64
+ else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
+ result <- [0] * 64
+ else
+ result128 <- si128_CONVERT_FROM_BFP(rnd)
+ result <- result128[64:127] & js_mask
+
+ switch(IT)
+ case(0): # Signed 32-bit
+ result <- EXTS64(result[32:63])
+ result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
+ case(1): # Unsigned 32-bit
+ result <- EXTZ64(result[32:63])
+ result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
+ case(2): # Signed 64-bit
+ result_bfp <- bfp_CONVERT_FROM_SI64(result)
+ default: # Unsigned 64-bit
+ result_bfp <- bfp_CONVERT_FROM_UI64(result)
+
+ if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
+ if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
+ if xx_flag = 1 then SetFX(FPSCR.XX)
+
+ vx_flag <- vxsnan_flag | vxcvi_flag
+ vex_flag <- FPSCR.VE & vx_flag
+
+ if vex_flag = 0 then
+ RT <- result
+ FPSCR.FPRF <- undefined
+ FPSCR.FR <- inc_flag
+ FPSCR.FI <- xx_flag
+ if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then
+ overflow <- 1 # signals SO only when OE = 1
+ else
+ FPSCR.FR <- 0
+ FPSCR.FI <- 0
```
Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer in RT, with the conversion overflow/rounding semantics following the chosen `CVM` value, following the usual 32-bit float in 64-bit float format.
projects / libreriscv.git / commitdiff