[Arm] Add CSDB instruction

CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.

OK? If so, please commit on my behalf as I don't have commit rights
over here.

Thanks, James

---
opcodes/

2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>

	* arm-dis.c (arm_opcodes): Add csdb.
	(thumb32_opcodes): Add csdb.

gas/

2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
	in Arm execution state, and Armv6T2 and above in Thumb execution
	state.
	* testsuite/gas/arm/csdb.s: New.
	* testsuite/gas/arm/csdb.d: New.
	* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
	* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d00ccb2b2da5ca14cc6dffb699a00ce5805494b7..287656b325799ccee0e374762c45cbe9c234ea97 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
+       in Arm execution state, and Armv6T2 and above in Thumb execution
+       state.
+       * testsuite/gas/arm/csdb.s: New.
+       * testsuite/gas/arm/csdb.d: New.
+       * testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
+       * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
+
 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * testsuite/gas/aarch64/system.d: Update expected results to expect

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 85f74a88e28c94bba1ade51ee99fc523f237cbfe..0b81c198dbba590c07a73a398ea35d6e8f1e29f7 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11274,6 +11274,12 @@ do_t_clz (void)
   inst.instruction |= Rm;
 }
 
+static void
+do_t_csdb (void)
+{
+  set_it_insn_type (OUTSIDE_IT_INSN);
+}
+
 static void
 do_t_cps (void)
 {
@@ -19984,6 +19990,15 @@ static const struct asm_opcode insns[] =
  TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
  TC3("strht",  02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
 
+#undef  ARM_VARIANT
+#define ARM_VARIANT    & arm_ext_v3
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v6t2
+
+ TUE("csdb",   320f014, f3af8014, 0, (), noargs, t_csdb),
+
+#undef  ARM_VARIANT
+#define ARM_VARIANT    & arm_ext_v6t2
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT  & arm_ext_v6t2_v8m
  TCE("movw",   3000000, f2400000, 2, (RRnpc, HALF),                mov16, t_mov16),

diff --git a/gas/testsuite/gas/arm/csdb.d b/gas/testsuite/gas/arm/csdb.d
new file mode 100644 (file)
index 0000000..baf5855
--- /dev/null
+++ b/gas/testsuite/gas/arm/csdb.d
@@ -0,0 +1,10 @@
+#name: CSDB
+#source: csdb.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> f3af 8014 ?      csdb
+0+004 <[^>]*> e320f014 ?       csdb
+

diff --git a/gas/testsuite/gas/arm/csdb.s b/gas/testsuite/gas/arm/csdb.s
new file mode 100644 (file)
index 0000000..133a5f0
--- /dev/null
+++ b/gas/testsuite/gas/arm/csdb.s
@@ -0,0 +1,6 @@
+.text
+.thumb
+.syntax unified
+csdb
+.arm
+csdb

diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.l b/gas/testsuite/gas/arm/thumb2_it_bad.l
index aa1f65874b9b045b0df5caee464c96ed06e22594..da9341fccfc598fb50b20b213b156bfdd01e01e5 100644 (file)
--- a/gas/testsuite/gas/arm/thumb2_it_bad.l
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.l
@@ -10,3 +10,4 @@
 [^:]*:19: Error: instruction is always unconditional -- `bkpteq 0'
 [^:]*:20: Error: instruction not allowed in IT block -- `setendeq le'
 [^:]*:22: Error: IT falling in the range of a previous IT block -- `iteq eq'
+[^:]*:25: Error: instruction not allowed in IT block -- `csdbeq'

diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.s b/gas/testsuite/gas/arm/thumb2_it_bad.s
index 6add4fb5171037e51559f0908f43da39f7ffd37b..72f305dc582c2e7672aa2e12dbc282fbf3324962 100644 (file)
--- a/gas/testsuite/gas/arm/thumb2_it_bad.s
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.s
@@ -21,4 +21,6 @@ thumb2_it_bad:
        it      eq
        iteq    eq
        nop
+       it      eq
+       csdbeq
 foo:

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 585169f578517bbb5f54bdf296299d19144f8995..96bc41c900439d124577283480b56daa651c58d5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * arm-dis.c (arm_opcodes): Add csdb.
+       (thumb32_opcodes): Add csdb.
+
 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index db48b32fe725034922ca376d0aab83c0cd085b26..5efe0316222d077a61831c743593e96e2ff6d77e 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1901,6 +1901,9 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 
+  /* CSDB.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
+
   /* ARM V6K NOP hints.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x0320f001, 0x0fffffff, "yield%c"},
@@ -2819,6 +2822,9 @@ static const struct opcode32 thumb32_opcodes[] =
   /* Security extension instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
 
+  /* CSDB.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
+
   /* Instructions defined in the basic V6T2 set.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},