Return an UnimpFault for an ITB translation of an uncachable address. We don't suppor...

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 77bf5e285310f43a7789debb206a7bc2d2c191f1..4f960360eba35cf319fce23d4804cf72dc70a0ad 100644 (file)
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -116,7 +116,7 @@ TLB::lookup(Addr vpn, uint8_t asn)
 
 
 Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(RequestPtr &req, bool itb)
 {
 // in Alpha, cacheability is controlled by upper-level bits of the
 // physical address
@@ -148,6 +148,12 @@ TLB::checkCacheability(RequestPtr &req)
             req->setPaddr(req->getPaddr() & PAddrUncachedMask);
 #endif
         }
+        // We shouldn't be able to read from an uncachable address in Alpha as
+        // we don't have a ROM and we don't want to try to fetch from a device 
+        // register as we destroy any data that is clear-on-read. 
+        if (req->isUncacheable() && itb) 
+            return new UnimpFault("CPU trying to fetch from uncached I/O");
+
     }
     return NoFault;
 }
@@ -390,7 +396,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
     if (req->getPaddr() & ~PAddrImplMask)
         return genMachineCheckFault();
 
-    return checkCacheability(req);
+    return checkCacheability(req, true);
 
 }
 

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index e61ae5c6dbb0da4ddb029af886fd70f2cf15c912..f94d06ccd42ef1c62f95f8b8ccb4a8f7fb8d1be1 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -92,7 +92,7 @@ namespace AlphaISA
             return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
         }
 
-        static Fault checkCacheability(RequestPtr &req);
+        static Fault checkCacheability(RequestPtr &req, bool itb = false);
 
         // Checkpointing
         virtual void serialize(std::ostream &os);