static union instruction *cvp_next_instruction( struct compilation *cp )
{
union instruction *op = cp->csr++;
- op->dword = 0;
+ _mesa_bzero(op, sizeof(*op));
return op;
}
/* Emit any necessary swizzling.
*/
- rsw.dword = 0;
+ _mesa_bzero(&rsw, sizeof(rsw));
rsw.rsw.neg = src->NegateBase ? WRITEMASK_XYZW : 0;
/* we're expecting 2-bit swizzles below... */
+#if 1 /* XXX THESE ASSERTIONS CURRENTLY FAIL DURING GLEAN TESTS! */
ASSERT(GET_SWZ(src->Swizzle, 0) < 4);
ASSERT(GET_SWZ(src->Swizzle, 1) < 4);
ASSERT(GET_SWZ(src->Swizzle, 2) < 4);
ASSERT(GET_SWZ(src->Swizzle, 3) < 4);
-
+#endif
rsw.rsw.swz = ((GET_SWZ(src->Swizzle, 0) << 0) |
(GET_SWZ(src->Swizzle, 1) << 2) |
(GET_SWZ(src->Swizzle, 2) << 4) |
(GET_SWZ(src->Swizzle, 3) << 6));
- noop.dword = 0;
+ _mesa_bzero(&noop, sizeof(noop));
noop.rsw.neg = 0;
noop.rsw.swz = RSW_NOOP;
- if (rsw.dword != noop.dword) {
+ if (_mesa_memcmp(&rsw, &noop, sizeof(rsw)) !=0) {
union instruction *op = cvp_next_instruction(cp);
struct reg rsw_reg = cvp_make_reg(FILE_REG, REG_ARG0 + arg);
- op->dword = rsw.dword;
+ *op = rsw;
op->rsw.opcode = RSW;
op->rsw.file0 = reg.file;
op->rsw.idx0 = reg.idx;
return REG_RES;
}
else {
- fixup->dword = 0;
+ _mesa_bzero(fixup, sizeof(*fixup));
cp->reg_active |= 1 << idx;
return idx;
}
struct reg reg[3];
GLuint result, nr_args, i;
- assert(sizeof(*op) == sizeof(MESA_LONGLONG));
-
/* Need to handle SWZ, ARL specially.
*/
switch (inst->Opcode) {
if (result == REG_RES) {
op = cvp_next_instruction(cp);
- op->dword = fixup.dword;
+ *op = fixup;
}
break;
if (result == REG_RES) {
op = cvp_next_instruction(cp);
- op->dword = fixup.dword;
+ *op = fixup;
}
break;
}
if (result == REG_RES) {
op = cvp_next_instruction(cp);
- op->dword = fixup.dword;
+ *op = fixup;
}
break;
}