MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
}
- /* On a6xx, we use UBO descriptors and LDC instead of UBO pointers in the
- * constbuf.
- */
- if (compiler->gpu_id >= 600)
- shader->num_ubos = nir->info.num_ubos;
- else
- const_state->num_ubos = nir->info.num_ubos;
+ const_state->num_ubos = nir->info.num_ubos;
/* num_driver_params is scalar, align to vec4: */
const_state->num_driver_params = align(const_state->num_driver_params, 4);
struct ir3_compiler *compiler;
- /* Number of UBOs loaded by LDC, as opposed to LDG through pointers in
- * ubo_state.
- */
- unsigned num_ubos;
-
struct ir3_const_state const_state;
struct nir_shader *nir;
fd6_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{
- if (!v->shader->num_ubos)
- return;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
+ int num_ubos = const_state->num_ubos;
- int num_ubos = v->shader->num_ubos;
+ if (!num_ubos)
+ return;
OUT_PKT7(ring, fd6_stage2opcode(v->type), 3 + (2 * num_ubos));
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
static unsigned
user_consts_cmdstream_size(struct ir3_shader_variant *v)
{
- struct ir3_ubo_analysis_state *ubo_state = &ir3_const_state(v)->ubo_state;
+ struct ir3_const_state *const_state = ir3_const_state(v);
+ struct ir3_ubo_analysis_state *ubo_state = &const_state->ubo_state;
if (unlikely(!ubo_state->cmdstream_size)) {
unsigned packets, size;
/* also account for UBO addresses: */
packets += 1;
- size += 2 * v->shader->num_ubos;
+ size += 2 * const_state->num_ubos;
unsigned sizedwords = (4 * packets) + size;
ubo_state->cmdstream_size = sizedwords * 4;
{
const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.ubo;
+
+ /* a6xx+ uses UBO state and ldc instead of pointers emitted in
+ * const state and ldg:
+ */
+ if (ctx->screen->gpu_id >= 600)
+ return;
+
if (v->constlen > offset) {
uint32_t params = const_state->num_ubos;
uint32_t offsets[params];