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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index d00bb83053a4f118a83fd97f8bcb86c47e2f51ff..ccef9b21b230e3cc98072bd2119786a4e28e5a10 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -33,7 +33,9 @@ Note that this is completely different from when VL=0.  VL=0 turns all operation
 # Register Naming
 
 SV Registers are simply the INT, FP and CR register files extended
-linearly to larger sizes.  Where the integer regfile in standard scalar
+linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
+
+Where the integer regfile in standard scalar
 OpenPOWER v3.0B and v3.1B is r0 to r31, SV extends this as r0 to r127.
 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
 extended to 64 entries, CR0 thru CR63.