/* Parse configuration data in .AMDGPU.config section format. */
void ac_parse_shader_binary_config(const char *data, size_t nbytes,
+ unsigned wave_size,
bool really_needs_scratch,
struct ac_shader_config *conf)
{
- uint32_t wavesize = 0;
+ uint32_t scratch_size = 0;
for (size_t i = 0; i < nbytes; i += 8) {
unsigned reg = util_le32_to_cpu(*(uint32_t*)(data + i));
case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
case R_00B848_COMPUTE_PGM_RSRC1:
case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
+ if (wave_size == 32)
+ conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
+ else
+ conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
+
conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
- conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
conf->float_mode = G_00B028_FLOAT_MODE(value);
conf->rsrc1 = value;
break;
case R_0286E8_SPI_TMPRING_SIZE:
case R_00B860_COMPUTE_TMPRING_SIZE:
/* WAVESIZE is in units of 256 dwords. */
- wavesize = value;
+ scratch_size = value;
break;
case SPILLED_SGPRS:
conf->spilled_sgprs = value;
if (really_needs_scratch) {
/* sgprs spills aren't spilling */
- conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(wavesize) * 256 * 4;
+ conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
}
}
};
void ac_parse_shader_binary_config(const char *data, size_t nbytes,
+ unsigned wave_size,
bool really_needs_scratch,
struct ac_shader_config *conf);
memset(binary, 0, sizeof(*binary));
memcpy(&binary->options, &i.options, sizeof(binary->options));
+ binary->wave_size = i.wave_size;
binary->num_parts = i.num_parts;
binary->parts = calloc(sizeof(*binary->parts), i.num_parts);
if (!binary->parts)
/* TODO: be precise about scratch use? */
struct ac_shader_config c = {};
- ac_parse_shader_binary_config(config_data, config_nbytes, true, &c);
+ ac_parse_shader_binary_config(config_data, config_nbytes,
+ binary->wave_size, true, &c);
config->num_sgprs = MAX2(config->num_sgprs, c.num_sgprs);
config->num_vgprs = MAX2(config->num_vgprs, c.num_vgprs);
/* Lightweight wrapper around underlying ELF objects. */
struct ac_rtld_binary {
struct ac_rtld_options options;
+ unsigned wave_size;
/* Required buffer sizes, currently read/executable only. */
uint64_t rx_size;
const struct radeon_info *info;
struct ac_rtld_options options;
gl_shader_stage shader_type;
+ unsigned wave_size;
unsigned num_parts;
const char * const *elf_ptrs; /* in-memory ELF objects of each part */
struct ac_rtld_open_info open_info = {
.info = &device->physical_device->rad_info,
.shader_type = binary->stage,
+ .wave_size = 64,
.num_parts = 1,
.elf_ptrs = &elf_data,
.elf_sizes = &elf_size,
if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
.info = &sel->screen->info,
.shader_type = MESA_SHADER_COMPUTE,
+ .wave_size = 64,
.num_parts = 1,
.elf_ptrs = &program->shader.binary.elf_buffer,
.elf_sizes = &program->shader.binary.elf_size }))
if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){
.info = &screen->info,
.shader_type = tgsi_processor_to_shader_stage(shader_type),
+ .wave_size = 64,
.num_parts = 1,
.elf_ptrs = &binary->elf_buffer,
.elf_sizes = &binary->elf_size }))
.halt_at_entry = screen->options.halt_shaders,
},
.shader_type = tgsi_processor_to_shader_stage(sel->type),
+ .wave_size = 64,
.num_parts = num_parts,
.elf_ptrs = part_elfs,
.elf_sizes = part_sizes,
if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
.info = &screen->info,
.shader_type = tgsi_processor_to_shader_stage(shader_type),
+ .wave_size = 64,
.num_parts = 1,
.elf_ptrs = &binary->elf_buffer,
.elf_sizes = &binary->elf_size }))
if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
.info = &sscreen->info,
.shader_type = tgsi_processor_to_shader_stage(shader_type),
+ .wave_size = 64,
.num_parts = 1,
.elf_ptrs = &binary->elf_buffer,
.elf_sizes = &binary->elf_size }))