Remove tech independent synthesis

diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys
index 84f31ec532ab7fae47017a5019c54b9d9f5a4251..8eeb221dbf7c34beaf09d253ead5816e1c43afd8 100644 (file)
--- a/tests/ice40/add_sub.ys
+++ b/tests/ice40/add_sub.ys
@@ -1,6 +1,5 @@
 read_verilog add_sub.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index d58ce1a82d4e3cbef66a784b644c75550beb2fa1..3c676e5908334d1ff37c3782836d72399d7ce98c 100644 (file)
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,12 +1,12 @@
 read_verilog adffs.v
 proc
 async2sync
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFE
-select -assert-count 4 t:SB_LUT4
-#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
-write_verilog adffs_synth.v
+select -assert-count 1 t:SB_DFFN
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 7 t:SB_LUT4
+select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index ddd8e5734946f4b3b28e72f3d2db2303fdcbe31e..b14346f5a47a1274107c6c99d93a9995cf95a591 100644 (file)
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -1,6 +1,7 @@
 read_verilog dffs.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+proc
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 93285cede9bc63bdd384ab2374fa3b0e0f08475b..613cad760cc0d412922b1286c506621855167627 100644 (file)
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -1,6 +1,6 @@
 read_verilog div_mod.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
index 0abd7f195b67b5ccf0c5c27fe6a307e912499bd3..fe0d1f70ef0b22d9803a191ee4a563cff328b38f 100644 (file)
--- a/tests/ice40/latches.ys
+++ b/tests/ice40/latches.ys
@@ -1,5 +1,6 @@
 read_verilog latches.v
 synth_ice40
-select -assert-count 5 t:SB_LUT4
-#select -assert-none t:SB_LUT4 %% t:* %D
+cd top
+select -assert-count 4 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
 write_verilog latches_synth.v

diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
index a0391e93dcf88fcb8003b500402971c10c8474dc..0a8c48dcaeec5c8ed7589534c1e4454cbf20af50 100644 (file)
--- a/tests/ice40/memory.ys
+++ b/tests/ice40/memory.ys
@@ -1,4 +1,5 @@
 read_verilog memory.v
 synth_ice40
+cd top
 select -assert-count 1 t:SB_RAM40_4K
 write_verilog memory_synth.v

diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys
index adf1b3211974ed932b803dfbe83d115b571ba571..aec7d0b1fa23ce604cc10a1c1e91707de5181399 100644 (file)
--- a/tests/ice40/mul.ys
+++ b/tests/ice40/mul.ys
@@ -1,6 +1,5 @@
 read_verilog mul.v
 hierarchy -top top
-#synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
index 9e3d87b7f1cd9a3a2f5b8504ed52074ae60bd978..63d22001f1da1e5e2cbbee39901755ae18d9d8d5 100644 (file)
--- a/tests/ice40/mux.ys
+++ b/tests/ice40/mux.ys
@@ -1,6 +1,8 @@
 read_verilog mux.v
-synth_ice40
+proc
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
 design -load postopt
-select -assert-count 20 t:SB_LUT4
-select -assert-count 1 t:SB_CARRY
+cd top
+select -assert-count 19 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
index 9b7ea1eab491e1c935eaf6f49929626cbd6d510d..8049a37abd64f56f9743f4078bfbb08c41a130a1 100644 (file)
--- a/tests/ice40/tribuf.ys
+++ b/tests/ice40/tribuf.ys
@@ -1,7 +1,8 @@
 read_verilog tribuf.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_